CN107316808B - Semiconductor device, preparation method thereof and electronic device - Google Patents

Semiconductor device, preparation method thereof and electronic device Download PDF

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Publication number
CN107316808B
CN107316808B CN201610261460.9A CN201610261460A CN107316808B CN 107316808 B CN107316808 B CN 107316808B CN 201610261460 A CN201610261460 A CN 201610261460A CN 107316808 B CN107316808 B CN 107316808B
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floating gate
layer
gate structure
semiconductor substrate
oxide layer
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CN107316808A (en
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任佳
陈卓凡
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

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Abstract

The invention relates to a semiconductor device, a manufacturing method thereof and an electronic device. The method comprises the following steps: providing a semiconductor substrate, forming a plurality of floating gate structures on the semiconductor substrate, and forming shallow trench isolation structures extending downwards into the semiconductor substrate between the adjacent floating gate structures; etching back to remove part of oxide in the shallow trench isolation structure so as to form a groove and expose the floating gate structure; oxidizing the exposed floating gate structure to form an oxide layer on the surface of the floating gate structure; removing the oxide layer to increase the width of the recess between the floating gate structures. The method is more beneficial to the filling of the control grid, can avoid holes generated in the filling process, and can keep wider key size of the active area to obtain larger unit current, thereby further improving the performance and yield of the semiconductor device.

Description

Semiconductor device, preparation method thereof and electronic device
Technical Field
The invention relates to the field of semiconductors, in particular to a semiconductor device, a preparation method thereof and an electronic device.
Background
As the demand for high-capacity semiconductor memory devices has increased, the integration density of these semiconductor memory devices has received much attention, and in order to increase the integration density of the semiconductor memory devices, many different methods have been adopted in the prior art, such as forming more memory cells on a single wafer by reducing the size of the memory cells and/or changing the structural units, and for the method of increasing the integration density by changing the cell structure, attempts have been made to reduce the cell area by changing the planar arrangement of the active regions or changing the cell layout.
NAND flash memory is a better storage scheme than a hard disk drive, and is suitable for storing continuous data such as pictures, audio, or other file data since it reads and writes data in units of pages; meanwhile, the method has the advantages of low cost, large capacity, high writing speed and short erasing time, and is widely applied to the storage field of mobile communication devices and portable multimedia devices. Currently, in order to increase the capacity of the NAND flash memory, the integration density of the NAND flash memory needs to be increased during the manufacturing process.
With the reduction of the device size, the size of the NAND flash memory is also continuously reduced, so that the NAND flash memory has many problems in the preparation process, for example, the filling of the control gate between the floating gates, and due to the reduction of the device size, holes are usually formed in the filling process of the control gate, which causes the increase of electrical loss, thereby finally reducing the performance of the device.
Therefore, how to overcome the problem of forming holes in the process of filling control gates in the process of manufacturing NAND flash memories is a problem that needs to be solved urgently.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
The invention provides a preparation method of a semiconductor device, which comprises the following steps:
providing a semiconductor substrate, forming a plurality of floating gate structures on the semiconductor substrate, and forming shallow trench isolation structures extending downwards into the semiconductor substrate between the adjacent floating gate structures;
etching back to remove part of oxide in the shallow trench isolation structure so as to form a groove and expose the floating gate structure;
oxidizing the exposed floating gate structure to form an oxide layer on the surface of the floating gate structure;
removing the oxide layer to increase the width of the recess between the floating gate structures.
Optionally, the method further comprises:
depositing an isolation layer in the recess and on a surface of the floating gate structure;
depositing a covering layer to fill the groove and cover the floating gate structure;
a control gate is formed over the capping layer.
Optionally, the oxidizing comprises O2Rapid thermal oxidation for annealing, decoupled plasma oxidation, or generation of oxygen plasma microwaves.
Optionally, the thickness of the oxide layer is 10-60 angstroms.
Optionally, the step of removing the oxide layer comprises a pre-cleaning step.
Optionally, the method further comprises a step of etching back the cover layer before forming the control gate on the cover layer.
Optionally, a tunnel oxide layer is further formed between the semiconductor substrate and the floating gate.
Optionally, the floating gate structure comprises polysilicon.
The invention also provides a semiconductor device prepared by the method.
The invention also provides an electronic device comprising the semiconductor device.
In order to solve the problems in the prior art, the invention provides a preparation method of a semiconductor device, which comprises the steps of oxidizing the side wall of a floating gate structure after a core region memory Cell Opening (COPEN) step so as to form an oxide layer on the surface of the floating gate structure and remove the oxide layer, and further expanding a groove opening between the floating gate structures after removing the oxide layer, thereby being more beneficial to filling of a control gate, avoiding holes generated in the filling process, simultaneously keeping the wider key size of an active region, and obtaining larger unit current, thereby further improving the performance and yield of the semiconductor device.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. There are shown in the drawings, embodiments and descriptions thereof, which are used to explain the principles and apparatus of the invention. In the drawings, there is shown in the drawings,
FIG. 1 is a flow chart of a process for fabricating a semiconductor device according to the present invention;
FIGS. 2a-2f are schematic views illustrating a process for fabricating a semiconductor device according to the present invention;
fig. 3 is an external view of an example of a mobile phone handset in the present invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
In order to solve the problems in the prior art, the invention provides a preparation method of a semiconductor device, which comprises the following steps:
providing a semiconductor substrate, forming a plurality of floating gate structures on the semiconductor substrate, and forming shallow trench isolation structures extending downwards into the semiconductor substrate between the adjacent floating gate structures;
etching back to remove part of oxide in the shallow trench isolation structure so as to form a groove and expose the floating gate structure;
oxidizing the exposed floating gate structure to form an oxide layer on the surface of the floating gate structure;
removing the oxide layer to increase the width of the recess between the floating gate structures;
depositing an isolation layer in the groove to cover the surface of the floating gate structure;
depositing a covering layer to fill the groove and cover the floating gate structure;
a control gate is formed over the capping layer.
Wherein the oxidation comprises selecting O2Rapid thermal oxidation for annealing, decoupled plasma oxidation, and generation of oxygen plasma microwaves.
Wherein the thickness of the oxide layer is 10-60 angstroms.
The invention provides a preparation method of a semiconductor device for solving the problems in the prior art, which comprises the steps of oxidizing the side wall of a floating gate structure after a COPEN step to form an oxide layer on the surface of the side wall of the floating gate structure and removing the oxide layer, wherein a groove opening between the floating gate structures can be further enlarged after the oxide layer is removed, so that the filling of a control gate is more facilitated, holes can be prevented from being generated in the filling process, and meanwhile, the key size of a wider active region can be kept to obtain larger unit current, so that the performance and the yield of the semiconductor device are further improved.
Example one
The present invention provides a method for manufacturing a semiconductor device, which is described in detail below with reference to the accompanying drawings.
FIGS. 2a-2f are schematic views illustrating a process for fabricating a semiconductor device according to the present invention; fig. 3 is an external view of an example of a mobile phone handset in the present invention.
Fig. 1 is a flow chart of a manufacturing process of the semiconductor device of the present invention, which specifically includes the following steps:
step S1: providing a semiconductor substrate, forming a plurality of floating gate structures on the semiconductor substrate, and forming shallow trench isolation structures extending downwards into the semiconductor substrate between the adjacent floating gate structures;
step S2: etching back to remove part of oxide in the shallow trench isolation structure so as to form a groove and expose the floating gate structure;
step S3: oxidizing the exposed floating gate structure to form an oxide layer on the surface of the floating gate structure;
step S4: removing the oxide layer to increase the width of the recess between the floating gate structures.
The method is explained in detail below on the basis of the process flow diagram in fig. 1.
And executing a first step, providing a semiconductor substrate, forming a plurality of floating gate structures on the semiconductor substrate, and forming shallow trench isolation structures extending downwards into the semiconductor substrate between the adjacent floating gate structures.
Specifically, as shown in fig. 2a, the semiconductor substrate 201 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others.
Forming a plurality of floating gate structures on the semiconductor substrate, specifically comprising the steps of:
a floating gate layer, a mask layer, and patterning are formed on the semiconductor substrate to form a floating gate structure 204 and shallow trenches. Specifically, a floating gate layer is formed on the semiconductor substrate, and the floating gate layer may be a polysilicon layer to form a floating gate structure in a subsequent step.
The mask layer can be a hard mask layer, such as SiN, so as to protect the floating gate layer from being damaged in the process of forming the shallow trench.
Then, a dry etching process is performed to sequentially etch the hard mask layer, the floating gate layer, and the semiconductor substrate 201 to form a shallow trench. Specifically, a photoresist layer with a pattern may be formed on the hard mask layer, the hard mask layer is dry etched using the photoresist layer as a mask to transfer the pattern to the hard mask layer, the floating gate layer and the semiconductor substrate 201 are etched using the photoresist layer and the hard mask layer as masks to form a trench, and a floating gate structure 204 separated from each other by the trench is formed in the floating gate layer.
The number of floating gate structures is not limited to a certain range of values.
Then, a shallow trench isolation material is filled in the trench to form a shallow trench isolation structure 202. Specifically, shallow trench isolation materials may be formed on the hard mask layer and in the trench, and the shallow trench isolation materials may be silicon oxide, silicon oxynitride and/or other existing low-dielectric constant materials; and performing a chemical mechanical polishing process and stopping on the hard mask layer to form the shallow trench isolation structure.
And finally, removing the hard mask layer. The method of removing the remaining hard mask layer may be a wet etching process, and since the etchant for removing the hard mask layer is well known in the art, it will not be described in detail.
Removing the hard mask layer to obtain a pattern with a shallow trench isolation structure, and optionally, performing well and threshold voltage adjustment on the pattern.
Optionally, a tunnel oxide layer 203 may also be formed between the semiconductor substrate and the floating gate structure. The preparation of the tunnel oxide comprises the steps of firstly carrying out nitrogen ion implantation or doping on a substrate to form a nitride layer, then carrying out high-temperature oxidation on the nitride layer to obtain an oxide layer, and recently carrying out nitridation treatment to ensure that the uppermost layer of the oxide is nitrided to obtain a SiON structure with the top and the bottom rich in nitrogen.
And step two, etching back to remove part of the oxide in the shallow trench isolation structure 202 to form a groove, and exposing the side wall of the floating gate structure 204.
Specifically, as shown in fig. 2a, in this step, a portion of the oxide in the shallow trench isolation structure 202 is removed by blanket etching (Blank etch), and a recess is formed to expose a portion of the sidewall of the floating gate structure 204, so that the floating gate structure 204 can have a larger contact area with the control gate structure in a subsequent step, which is called a step of opening a memory Cell (COPEN), i.e., by removing a portion of the shallow trench isolation oxide between the floating gates to expose a portion of the floating gate structure, so that a stable contact can be formed with the floating gate structure after depositing a polysilicon layer, thereby avoiding the problem of unstable contact due to the reduced device size.
The COPEN process may be a process commonly used in the art, and is not described herein again.
In order to prevent damage to the sidewalls of the floating gate structure during this step, an etching method having a large etching selectivity ratio to the floating gate structure is selected, and optionally, an etching method containing at least O is selected during this step2The etching atmosphere of (2) is selected to contain O2The etching atmosphere not only can improve the etching selection ratio of the oxide and the floating gate structure, but also can enable the exposed side wall to have a smoother profile (rounding profile) so as to improve the coupling effect of the floating gate structure and the control gate structure.
Further, in the embodiments of the present inventionThe etching atmosphere contains O2In addition, C may be further contained4F6，C4F8Or C5F8Or similar C-rich etching gases to further increase the etch selectivity of the floating gate structure to oxide to reduce damage to the sidewalls of the floating gate structure. The side wall of the floating gate structure is more smooth, no defect exists, and the performance of the semiconductor device is greatly improved compared with that of a semiconductor device prepared by other methods.
Optionally, after exposing the floating gate structure 204, the method further comprises a step of performing a wet cleaning. The wet cleaning step adopts DHF, and the wet cleaning not only can reduce the holes of the oxide in the shallow trench isolation structure, but also can reduce the roughness of the surface of the oxide so as to improve the performance and yield of devices.
And a third step is executed, the exposed floating gate structure is oxidized, so that an oxide layer 205 is formed on the surface of the floating gate structure.
Specifically, as shown in FIG. 2b, the oxidation in this step includes the selection of O2Rapid thermal oxidation for annealing, decoupled plasma oxidation, and generation of oxygen plasma microwaves.
Wherein, in one embodiment of the present invention, O is selected2Or contain O2The floating gate structure is subjected to heat treatment in the atmosphere, the heat treatment temperature is 800-1500 ℃, preferably 1100-1200 ℃, the treatment time is 2-30min, and an oxide layer 205 with the thickness of 10-60 angstroms is formed on the floating gate structure through the heat treatment.
In an embodiment of the present invention, the floating gate structure is made of polysilicon, so that a silicon oxide layer is formed on the surface of the floating gate structure.
And step four is executed, the oxide layer is removed, and the width of the groove between the floating gate structures is increased.
Specifically, as shown in fig. 2c, the oxide layer 205 is removed by a pre-cleaning method in this step to increase the opening of the recess.
Optionally at this pointIn the step, diluted hydrofluoric acid DHF (containing HF and H) is used2O2And H2O) pre-cleaning the surface of the bottom wafer 301 to remove the oxide layer 205.
The concentration of DHF is not critical, but preferred is HF: H in the present invention2O2:H2O＝0.1-1.5:1:5。
As an alternative embodiment, a method with a larger etching selectivity ratio to the floating gate structure 204 may be selected in this step, for example, a SiCoNi process is selected to remove the oxide layer 205, the SiCoNi process has a high selectivity to the oxide layer 205, and specific parameters in the SiCoNi process may be selected by those skilled in the art according to process requirements, and are not limited to a certain value.
According to the method, after the COPEN step, the side wall of the floating gate structure is oxidized, so that an oxide layer is formed on the surface of the side wall of the floating gate structure and removed, and after the oxide layer is removed, the opening of the groove between the floating gate structures can be further enlarged, so that the filling of a control gate is facilitated, holes can be avoided in the filling process, meanwhile, the wider key size of an active region can be kept, so that larger unit current can be obtained, and the performance and the yield of a semiconductor device can be further improved.
Step five is executed, and an isolation layer 206 is deposited in the groove to cover the surface of the floating gate structure.
In particular, as shown in fig. 2d, the isolation layer 206 in this step may be made of an insulating material commonly used in the art, such as ONO (oxide-nitride-oxide structure insulating isolation layer), but is not limited to the above-mentioned material.
The thickness of the isolation layer 206 is not limited to a certain range.
And a sixth step of depositing a covering layer 207 to fill the groove and cover the floating gate structure, and finally forming a control gate on the covering layer.
Specifically, as shown in fig. 2e, in this step, the capping layer 207 is deposited, and since the recess between the floating gate structures has a larger opening, the problem of void formation during the filling of the capping layer can be avoided, and the problem of difficult filling due to the reduction of the device size is well solved.
Optionally, the capping layer 207 is made of a semiconductor material, such as, but not limited to, polysilicon.
The step of etching back the capping layer is further included before forming the control gate 208 on the capping layer.
A control gate material layer is then formed over the capping layer, as shown in fig. 2f, wherein the control gate material layer may be made of the same material as the floating gate material layer or a different material, for example, a metal gate may be formed as the control gate 208.
Thus, the description of the steps related to the fabrication of the semiconductor device of the embodiment of the present invention is completed. After the above steps, other related steps may also be included, which are not described herein again. Besides the above steps, the preparation method of this embodiment may further include other steps among the above steps or between different steps, and these steps may be implemented by various processes in the prior art, and are not described herein again.
Example two
In order to solve the problems in the prior art, the invention provides a semiconductor device which is prepared by the method in the first embodiment.
The semiconductor body device includes:
the semiconductor substrate 201;
a shallow trench isolation in the semiconductor substrate,
the floating gate structure is positioned on the semiconductor substrate and between the shallow trench isolations;
the isolation layer is positioned above the floating gate;
a control gate 208 is located on the isolation layer.
Wherein the semiconductor substrate 201 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others.
Forming a plurality of floating gate structures on the semiconductor substrate, specifically comprising the steps of:
optionally, a tunnel oxide layer 203 is further formed between the semiconductor substrate and the floating gate structure. The preparation of the tunnel oxide comprises the steps of firstly carrying out nitrogen ion implantation or doping on a substrate to form a nitride layer, then carrying out high-temperature oxidation on the nitride layer to obtain an oxide layer, and recently carrying out nitridation treatment to ensure that the uppermost layer of the oxide is nitrided to obtain a SiON structure with the top and the bottom rich in nitrogen.
In the preparation process of the floating gate structure of the semiconductor device, the floating gate structure is oxidized to form an oxide layer on the surface of the side wall of the floating gate structure and removed, and after the oxide layer is removed, the opening of the groove between the floating gate structures can be further enlarged, so that the filling of a control gate is facilitated, holes can be avoided in the filling process, meanwhile, the wider key size of an active region can be kept, so that larger unit current can be obtained, and the performance and yield of the semiconductor device can be further improved.
The isolation layer 206 may be made of an insulating material commonly used in the art, such as ONO (oxide-nitride-oxide structure insulating isolation layer), but is not limited to the above-mentioned material.
The thickness of the isolation layer 206 is not limited to a certain range.
Optionally, the device further comprises a capping layer 207 over the floating gate structure.
Optionally, the capping layer 207 is made of a semiconductor material, such as, but not limited to, polysilicon.
The method further comprises the step of etching back the covering layer before forming the control gate on the covering layer.
And then forming a control gate material layer above the covering layer, wherein the control gate material layer may be made of the same material as the floating gate material layer or a different material, for example, a metal gate may be formed as a control gate.
In the preparation process of the semiconductor device, the side wall of the floating gate structure is oxidized after the COPEN step so as to form an oxide layer on the surface of the side wall of the floating gate structure and remove the oxide layer, and after the oxide layer is removed, the opening of the groove between the floating gate structures can be further enlarged, thereby being more beneficial to the filling of a control gate, avoiding generating holes in the filling process, simultaneously keeping the wider key size of an active region, obtaining larger unit current, and further improving the performance and the yield of the semiconductor device.
EXAMPLE III
The invention also provides an electronic device comprising the semiconductor device of the second embodiment, and the semiconductor device is prepared according to the method of the first embodiment.
The electronic device of this embodiment may be any electronic product or device, such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a digital photo frame, a camera, a video camera, a recording pen, an MP3, an MP4, a PSP, and the like, and may also be any intermediate product including a circuit. The electronic device of the embodiment of the invention has better performance due to the use of the circuit.
Wherein figure 3 shows an example of a mobile telephone handset. The mobile phone handset 300 is provided with a display portion 302, operation buttons 303, an external connection port 304, a speaker 305, a microphone 306, and the like, which are included in a housing 301.
The mobile phone comprises the semiconductor device of the second embodiment, the sidewall of the floating gate structure is oxidized after the semiconductor device COPEN step, so that an oxide layer is formed on the surface of the sidewall of the floating gate structure and is removed, and the opening of the groove between the floating gate structures can be further enlarged after the oxide is removed, thereby being more beneficial to filling of a control gate, avoiding generating holes in the filling process, simultaneously keeping the key size of a wider active region, obtaining larger unit current, and further improving the performance and yield of the semiconductor device.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims (10)

1. A method of fabricating a semiconductor device, the method comprising:
providing a semiconductor substrate, forming a plurality of floating gate structures on the semiconductor substrate, and forming shallow trench isolation structures extending downwards into the semiconductor substrate between the adjacent floating gate structures;
etching back to remove part of oxide in the shallow trench isolation structure so as to form a groove and expose the floating gate structure;
oxidizing the exposed floating gate structure to form an oxide layer on the surface of the side wall of the floating gate structure;
and removing the oxide layer to increase the width of the groove between the floating gate structures, thereby avoiding holes generated in the filling process.
2. The method of claim 1, further comprising:
depositing an isolation layer in the recess and on a surface of the floating gate structure;
depositing a covering layer to fill the groove and cover the floating gate structure;
a control gate is formed over the capping layer.
3. The method of claim 1, wherein the oxidizing is with O2Rapid thermal oxidation for annealing, decoupled plasma oxidation, or generation of oxygen plasma microwaves.
4. The method of claim 1, wherein the oxide layer has a thickness of 10 to 60 angstroms.
5. The method of claim 1, wherein the step of removing the oxide layer comprises a pre-cleaning step.
6. The method of claim 2 further comprising the step of etching back the capping layer prior to forming the control gate over the capping layer.
7. The method of claim 1, wherein a tunnel oxide layer is further formed between the semiconductor substrate and the floating gate.
8. The method of claim 1, wherein the floating gate structure comprises polysilicon.
9. A semiconductor device, characterized in that it is produced by a method according to one of claims 1 to 8.
10. An electronic device, characterized in that the electronic device comprises the semiconductor device according to claim 9.
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