CN112750785B - Manufacturing method of split gate type flash memory device - Google Patents
Manufacturing method of split gate type flash memory device Download PDFInfo
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- CN112750785B CN112750785B CN202110088507.7A CN202110088507A CN112750785B CN 112750785 B CN112750785 B CN 112750785B CN 202110088507 A CN202110088507 A CN 202110088507A CN 112750785 B CN112750785 B CN 112750785B
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
- H01L21/28132—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects conducting part of electrode is difined by a sidewall spacer or a similar technique, e.g. oxidation under mask, plating
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
Abstract
The invention provides a manufacturing approach of the split gate flash memory device, through making the top surface of the material layer of control gate level with top surface of the said word line, then, form the photoresist layer on said material layer of control gate and said word line, and expose and develop the process to the said photoresist layer, in order to form the photoresist layer of patterned, because the top surface of the material layer of control gate is level with top surface of the said word line, can avoid the photoresist from remaining between said word line and said material layer of control gate; sequentially etching the exposed control gate material layer and floating gate material layer by taking the patterned photoresist layer as a mask to form a control gate layer and a floating gate layer; and removing the patterned photoresist layer to expose the top surface of the control gate material layer and the top surface of the word line to form metal silicide, wherein the metal silicide covers the top surface of the control gate material layer and the top surface of the word line, so that the contact resistance of the control gate layer can be reduced due to the existence of the metal silicide.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a manufacturing method of a split gate type flash memory device.
Background
Flash memory (Flash) devices are a type of nonvolatile semiconductor memory, including stacked gate Flash memory and split gate Flash memory. Compared with the stacked gate flash memory, the split gate flash memory has the advantages that word lines in the split gate flash memory avoid over-erasure effect and have higher programming efficiency. Please refer to fig. 1-5, which are schematic diagrams of the structure of a split gate flash memory device in the prior art; the existing manufacturing method of split gate flash memory device generally comprises: first, as shown in fig. 1, a semiconductor substrate 1 is provided, and a floating gate material layer 2, an isolation layer 3, a control gate material layer 4, and a mask layer 5 are sequentially formed on the semiconductor substrate 1; wherein, the mask layer 5 has an opening 6, the opening 6 exposes a portion of the control gate material layer 4, then, as shown in fig. 2, a sidewall 7 is formed on a sidewall of the opening 6, and the control gate material layer 4, the isolation layer 3 and the floating gate material layer 2 are etched sequentially with the sidewall 7 as a mask, so that the opening 6 extends through the control gate material layer 4, the isolation layer 3 and the floating gate material layer 2; next, as shown in fig. 3, the word line 8 is filled in the opening 6; next, as shown in fig. 4, the mask layer 5 is removed to expose a portion of the control gate material layer 4, and as shown in fig. 5, a patterned photoresist layer is formed, the patterned photoresist layer covers the exposed control gate material layer 4, and the exposed control gate material layer 4, isolation layer 3, and floating gate material layer 2 are sequentially etched to form a first control gate 4a, a second control gate 4b, a first floating gate 2a, and a second floating gate 2b.
However, in the above steps, after the mask layer 5 is removed, a level difference is formed between the word line 8 and the control gate material layer 4, and after the photoresist is exposed and developed in the subsequent step of forming the patterned photoresist layer, photoresist residues (such as photoresist residues on the sidewalls of the word line) are easily present between the word line 8 and the control gate material layer 4, so that the subsequent etching of the control gate material layer 4 is affected. In addition, since the surfaces of the first control gate and the second control gate are covered by the side wall, metal silicide cannot be formed on the surfaces of the first control gate and the second control gate, and therefore the contact resistance of the first control gate 4a and the second control gate 4b is high.
Disclosure of Invention
The invention aims to provide a manufacturing method of a split gate type flash memory device, which is used for solving the problems of photoresist residues and larger contact resistance of a control gate between a control gate material layer and a word line material layer in the prior art.
In order to solve the above technical problems, the present invention provides a method for manufacturing a split gate flash memory device, the method for manufacturing the split gate flash memory device comprising:
providing a semiconductor substrate, wherein a floating gate material layer, a mask layer, a side wall and a word line are formed on the semiconductor substrate in sequence, the word line penetrates through the floating gate material layer, and the side wall is positioned between the word line and the mask layer;
removing the mask layer to expose the floating gate material layer and the side wall of the side wall far away from the word line side;
forming a control gate material layer on the floating gate material layer, wherein the top surface of the control gate material layer is flush with the top surface of the word line;
forming a photoresist layer on the control gate material layer and the word line, and exposing and developing the photoresist layer to form a patterned photoresist layer, wherein a part of the control gate material layer is exposed out of the patterned photoresist layer;
sequentially etching the exposed control gate material layer and the exposed floating gate material layer by taking the patterned photoresist layer as a mask to form a control gate layer and a floating gate layer;
removing the patterned photoresist layer to expose the top surface of the control gate layer and the top surface of the word line; and
forming a metal silicide, wherein the metal silicide covers the top surface of the control gate layer and the top surface of the word line.
Optionally, in the method for manufacturing the split gate flash memory device, the method for sequentially forming the floating gate material layer, the mask layer, the side wall and the word line on the semiconductor substrate includes:
forming a floating gate material layer and a mask layer on the semiconductor substrate in sequence, wherein the floating gate material layer covers the semiconductor substrate;
forming a first opening in the mask layer, wherein the first opening exposes part of the floating gate material layer;
forming a side wall material layer through a chemical vapor deposition process, wherein the side wall material layer covers the side wall and the bottom wall of the first opening and extends to cover the top surface of the mask layer;
removing the top surface of the mask layer and the side wall material layer of the bottom wall of the first opening to form the side wall, and defining a second opening by the side wall covering the opposite side wall of the first opening;
etching the exposed floating gate material layer by taking the side wall as a mask so that the second opening extends to penetrate through the floating gate material layer;
forming a word line material layer filling the second opening and extending to cover a top surface of the mask layer;
and removing the word line material layer on the top surface of the mask layer to form word lines.
Optionally, in the method for manufacturing a split gate flash memory device, after etching the exposed floating gate material layer with the side wall as a mask, before forming the word line, the method for manufacturing a split gate flash memory device further includes: and forming a tunneling oxide layer, wherein the tunneling oxide layer covers the side wall and the bottom wall of the second opening, and the word line is positioned on the tunneling oxide layer.
Optionally, in the method for manufacturing a split gate flash memory device, a gate oxide layer is further formed between the floating gate material layer and the semiconductor substrate, and the second opening further extends through the gate oxide layer.
Optionally, in the method for manufacturing a split gate flash memory device, when the patterned photoresist layer is used as a mask, etching the exposed control gate material layer and floating gate material layer sequentially further includes: and etching the gate oxide layer to expose a part of the semiconductor substrate.
Optionally, in the method for manufacturing a split gate flash memory device, after removing the mask layer, before forming the control gate material layer on the floating gate material layer, the method for manufacturing a flash memory device further includes:
forming an isolation material layer, wherein the isolation material layer covers the top surface of the floating gate material layer, the top surface of the word line and the exposed side wall of the side wall; the isolation material layer comprises a first oxide layer, a nitride layer covering the first oxide layer and a second oxide layer covering the nitride layer.
Optionally, in the method for manufacturing a split gate flash memory device, the method for forming the control gate material layer on the floating gate material layer includes:
forming a control gate material layer, wherein the control gate material layer covers the isolation material layer;
and removing the isolation material layer and the control grid material layer on the top surface of the word line so that the top surface of the control grid material layer is level with the top surface of the word line.
Optionally, in the method for manufacturing a split gate flash memory device, when the patterned photoresist layer is used as a mask, etching the exposed control gate material layer and the exposed floating gate material layer sequentially further includes: and etching the isolation material layer to form an isolation layer, wherein the isolation layer comprises a first isolation layer and a second isolation layer which are respectively positioned at two sides of the word line.
Optionally, in the method for manufacturing a split gate flash memory device, the control gate layer includes a first control gate and a second control gate respectively located at two sides of the word line, and the floating gate layer includes a first floating gate and a second floating gate respectively located at two sides of the word line, and the first floating gate and the second floating gate expose a portion of the semiconductor substrate.
Optionally, in the method for manufacturing a split gate flash memory device, after forming the metal silicide, the method for manufacturing a split gate flash memory device further includes:
forming a dielectric layer, wherein the dielectric layer covers the metal silicide and the exposed semiconductor substrate; the method comprises the steps of,
and forming a plurality of penetrating contact structures in the dielectric layer, wherein the contact structures are respectively aligned to the first control gate, the second control gate and the word line.
In the manufacturing method of the split gate type flash memory device, firstly, a semiconductor substrate is provided, a floating gate material layer, a mask layer, a side wall and a word line are sequentially formed on the semiconductor substrate, the word line penetrates through the mask layer and the floating gate material layer, and the side wall is positioned between the word line and the mask layer; then, removing the mask layer to expose the top surface of the floating gate material layer and the side wall of the side wall far away from the word line side; forming a control gate material layer on the floating gate material layer, wherein the top surface of the control gate material layer is flush with the top surface of the word line; because the top surface of the control gate material layer is flush with the top surface of the word line, no height difference exists between the top surface of the word line and the top surface of the control gate material layer, and a better process window can be improved for a patterned photoresist layer formed later; then, forming a photoresist layer on the control gate material layer and the word line, and exposing and developing the photoresist layer to form a patterned photoresist layer, wherein a part of the control gate material layer is exposed out of the patterned photoresist layer; because the top surface of the word line is flush with the top surface of the control gate material layer, after the photoresist layer is subjected to the exposure and development process, the photoresist can be prevented from remaining between the word line and the control gate material layer; and then, sequentially etching the exposed control gate material layer and the floating gate material layer by taking the patterned photoresist layer as a mask to form a control gate layer and a floating gate layer, namely defining the parts to be removed in the control gate material layer and the floating gate material layer through the patterned photoresist layer. Then, removing the patterned photoresist layer to expose the top surface of the control gate layer and the top surface of the word line; and forming a metal silicide, wherein the metal silicide covers the top surface of the control gate layer and the top surface of the word line. The presence of the metal silicide may reduce the contact resistance of the control gate layer. Thus solving the problems of photoresist residue and larger contact resistance of the control gate existing between the control gate material layer and the word line material layer in the prior art.
Drawings
Fig. 1 to 5 are schematic structural views of a method for manufacturing a split gate flash memory device according to the related art;
FIG. 6 is a schematic flow chart of a method for manufacturing a split gate flash memory device according to the present invention;
fig. 7 to 20 are schematic structural views formed in the method for manufacturing the split gate flash memory device according to the present invention.
Wherein reference numerals are as follows:
1-a semiconductor substrate; 2-a floating gate material layer; 3-isolating layer; 4-a control gate material layer; 5-a mask layer; 6-opening; 7-side walls; 8-word lines; 2 a-a first floating gate; 2 b-a second floating gate; 4 a-a first control gate; 4 b-a second control gate;
10-a semiconductor substrate; 11-gate oxide; 12-a layer of floating gate material; 13-a mask layer; 14-a first opening; 15-a side wall material layer; 16-side walls; 17-a second opening; 18-tunneling oxide; 19-word lines; 20-a layer of isolation material; 21-a first oxide layer; a 22-nitride layer; 23-a second oxide layer; 30-a control gate material layer; 40-patterning the photoresist layer; 120-a first floating gate; 121-a second floating gate; 201-a first isolation layer; 202-a second isolation layer; 301-a first control gate; 302-a second control gate; 303-metal silicide; 304-a dielectric layer; 305-contact structure; 305 a-a first contact structure; 305 b-a second contact structure; 305 c-third contact structure.
Detailed Description
The manufacturing method of the split gate flash memory device according to the present invention is described in further detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
Fig. 1 is a flowchart illustrating a method for manufacturing a split gate flash memory device according to an embodiment of the invention. As shown in fig. 1, the present invention provides a method for manufacturing a split gate flash memory device, including:
step S1: providing a semiconductor substrate, wherein a floating gate material layer, a mask layer, a side wall and a word line are formed on the semiconductor substrate in sequence, the word line penetrates through the floating gate material layer, and the side wall is positioned on the word line;
step S2: removing the mask layer to expose the floating gate material layer and the side wall of the side wall far away from the word line side;
step S3: forming a control gate material layer on the floating gate material layer, wherein the top surface of the control gate material layer is flush with the top surface of the word line;
step S4: forming a photoresist layer on the control gate material layer and the word line, and exposing and developing the photoresist layer to form a patterned photoresist layer, wherein a part of the control gate material layer is exposed out of the patterned photoresist layer;
step S5: sequentially etching the exposed control gate material layer and the exposed floating gate material layer by taking the patterned photoresist layer as a mask to form a control gate layer and a floating gate layer;
step S6: removing the patterned photoresist layer to expose the top surface of the control gate layer and the top surface of the word line; and
step S7: forming a metal silicide, wherein the metal silicide covers the top surface of the control gate layer and the top surface of the word line.
Next, the above steps will be described in more detail with reference to fig. 7 to 20. Fig. 7 to 20 are schematic structural diagrams formed in the method for manufacturing the split gate flash memory device according to the embodiment of the invention.
Firstly, step S1 is performed, as shown in fig. 7, a semiconductor substrate 10 is provided, a floating gate material layer 12, a mask layer 13, a sidewall 16 and a word line 19 are sequentially formed on the semiconductor substrate 10, the word line 19 penetrates through the mask layer 13 and the floating gate material layer 12, and the sidewall 16 is located between the word line 19 and the mask layer 13; the semiconductor substrate 10 may be a silicon substrate.
Furthermore, a gate oxide layer 11 is formed between the floating gate material layer 12 and the semiconductor substrate 10, and the gate oxide layer 11 is used for isolating the semiconductor substrate 10 from the floating gate material layer 12. The floating gate material layer 12 is used to form a floating gate layer.
Specifically, the method for sequentially forming the gate oxide layer 11, the floating gate material layer 12, the mask layer 13, the sidewall 16 and the word line 19 on the semiconductor substrate includes:
in step S11, referring specifically to fig. 7, a gate oxide layer 11, a floating gate material layer 12, and a mask layer 13 are sequentially formed on the semiconductor substrate 10, where the gate oxide layer 11 covers the semiconductor substrate 10, and the gate oxide layer 11 may be formed by low-pressure chemical vapor deposition, atomic layer deposition, thermal oxidation, or molecular beam epitaxy. The gate oxide layer 11 is made of silicon oxide, such as silicon dioxide, preferably silicon dioxide, to enhance the interfacial adhesion between layers. The floating gate material layer 12 may be formed by chemical vapor deposition, and is used to form a floating gate in a subsequent process, and may be polysilicon, for example. The mask layer 13 is made of at least one of silicon nitride, silicon carbide nitride, silicon boride nitride, silicon oxycarbide nitride and silicon oxynitride.
Step S12: forming a first opening 14 in the mask layer 13, wherein a part of the floating gate material layer 12 is exposed by the first opening 14;
step S13: referring to fig. 9 to 10, a sidewall 16 is formed, and the sidewall 16 covers the sidewall of the first opening 14. Specifically, the method for forming the side wall 16 includes: as shown in fig. 9, a sidewall material layer 15 is formed on the bottom wall and the sidewall of the first opening 14 and the mask layer 13; then, the portions of the sidewall material layer 15 located at the mask layer 13 and the bottom wall of the first opening 14 are removed, that is, the portions of the sidewall material layer 15 covering the sidewalls of the first opening 17 are remained, so as to form the sidewalls 16, and the sidewalls 16 covering the opposite sidewalls of the first opening 14 define the second opening 17.
Step S14: as shown in fig. 10, the exposed floating gate material layer 12 and the exposed gate oxide layer 11 are etched sequentially with the sidewall 16 as a mask, so that the second opening 17 extends through the floating gate material layer 12 and the gate oxide layer 11, and the second opening 17 is used for defining a position of the word line 19.
Step S15: referring to fig. 11, a tunnel oxide layer 18 is formed, the tunnel oxide layer 18 covers the sidewalls and bottom wall of the second opening 17, and the tunnel oxide layer 18 is used to isolate the word line 19 formed later from the floating gate layer and the control gate layer.
Step S16: forming a word line material layer that fills the second opening 17 and extends to cover the top surface of the mask layer 13; specifically, the word line material layer is formed by a chemical vapor deposition method.
Step S17: the word line material layer on the top surface of the mask layer 13 is removed to form a word line 19. In other embodiments of the present invention, a planarization process, such as a chemical mechanical polishing process, may be used when removing the word line material layer on the top surface of the mask layer 13, and a dry etching process may also be used when removing the word line material layer on the top surface of the mask layer 13. Wherein the material of the word line material layer is polysilicon.
Next, step S2 is performed, as shown in fig. 13, the mask layer 13 is removed, and the floating gate material layer 12 and the sidewall of the sidewall 16 away from the word line 19 are exposed. When the mask layer 13 is removed, a wet etching process may be used, and the wet etching process preferably uses an acidic etching solution, for example, phosphoric acid, so that a better etching selectivity is provided between the etching solution and the mask layer 13, and the etching rate is improved.
Next, as shown in fig. 4, an isolation material layer 20 is formed, where the isolation material layer 20 covers the exposed sidewalls of the sidewalls 16, the floating gate material layer 12 and the top surface of the word line 19, that is, the isolation material layer 20 covers the global surface of the semiconductor substrate 10, and the isolation material layer 20 is used to form an isolation layer 201 later, and the isolation layer 201 is used to isolate the control gate layer and the floating gate layer that are formed later. Wherein the isolation material layer 20 includes a first oxide layer 21, a nitride layer 22 covering the first oxide layer 21, and a second oxide layer 23 covering the nitride layer 21.
More specifically, the isolation material layer 20 may be formed using one or more of a plasma chemical vapor deposition process, an atomic layer deposition process, a low pressure chemical vapor deposition process, or a sub-atmospheric pressure chemical vapor deposition process. The low-pressure vapor deposition process and the atomic layer deposition process are preferably used to form the isolation material layer 20 in this embodiment, so that the thickness uniformity of the isolation material layer 20 is better. For example, the first oxide layer 21 and the second oxide layer 23 may be formed using a low pressure vapor deposition (LPCVD) process of tetraethyl orthosilicate (TEOS), and the nitride layer 22 may be formed using an atomic layer deposition process.
Next, step S3 is performed, specifically referring to fig. 15 to 16, a control gate material layer 30 is formed on the floating gate material layer 10, and a top surface of the control gate material layer 30 is flush with a top surface of the word line 19. Specifically, the method for forming the control gate material layer 30 includes:
step S31: as shown in fig. 15, a control gate material layer 30 is formed, the control gate material layer 30 covering the isolation material layer 20; the control gate material layer 30 may be deposited by an ion-assisted chemical vapor deposition process, a low pressure chemical vapor deposition process, or a sub-atmospheric chemical vapor deposition process.
Step S32, as shown in fig. 16, removing the isolation material layer 20 and the control gate material layer 30 on the top surface of the word line 19, so that the top surface of the control gate material layer 30 is flush with the top surface of the word line 19, i.e., the top surface of the word line 19 is exposed. Wherein, when the control gate material layer 30 and the isolation material layer 20 on the top surface of the word line 19 are removed, a dry etching process, preferably an etching gas containing fluorine, is used, and the etching pressure is between 5mT and 10mT; the flow rate of the etching gas is between 100sccm and 200sccm, and the etching time is between 60s and 100s, so as to avoid the residues of the control gate material layer 30 and the isolation material layer 20 on the top surface of the word line 19. In other embodiments of the present invention, a planarization process may be used to remove the isolation material layer 20 and the control gate material layer 30 on the top surface of the word line 19.
Next, step S4 is performed: referring to fig. 17, a photoresist layer is formed on the control gate material layer 30 and the word line 19, and an exposure and development process is performed on the photoresist layer to form a patterned photoresist layer 40, where a portion of the control gate material layer 30 is exposed by the patterned photoresist layer 40, that is, a portion of the control gate material layer 30 that needs to be retained is defined by the patterned photoresist layer 40.
Specifically, the method for forming the patterned photoresist layer 40 includes: photoresist is spin coated on the global surface of the semiconductor substrate 10, including the top surface of the word line 19 and the top surface of the control gate material layer 30, to form a photoresist layer, and the photoresist layer is subjected to an exposure and development process to form a patterned photoresist layer 40. Compared with the prior art, when the photoresist layer 40 is formed, since the top surface of the word line 19 is flush with the top surface of the control gate material layer 30, i.e. there is no height difference between the two, a relatively flat photoresist layer can be formed on the top surfaces of the two (the word line and the control gate material layer), after the photoresist layer is exposed and developed, the photoresist layer can be prevented from remaining between the control gate material layer 30 and the word line 19 after the development process, thereby providing a larger process window for the patterned photoresist layer formed later, and being beneficial to enlarging the process window of the contact structure (the contact structure formed later and located on the control gate), thereby improving the yield of products. Specifically, when the photoresist layer is exposed and developed, there is no difference in height between the top surface of the word line 19 and the top surface of the control gate material layer 30.
Next, step S5 is performed: referring to fig. 18, the control gate material layer 30, the isolation material layer 20 and the floating gate material layer 10 are sequentially etched with the patterned photoresist layer 40 as a mask to form a control gate layer, an isolation layer and a floating gate layer; the control gate layer includes a first control gate 301 and a second control gate 302 respectively located at two sides of the word line 19, the isolation layer includes a first isolation layer 201 and a second isolation layer 202 respectively located at two sides of the word line, the floating gate layer includes a first floating gate 120 and a second floating gate 121 respectively located at two sides of the word line 19, and the first floating gate 120 and the second floating gate 121 expose a portion of the semiconductor substrate 100. I.e. the portions of the control gate material layer 30 and the floating gate material layer 12 that are to be removed are defined by the patterned photoresist layer 40. In addition, when the patterned photoresist layer 140 is used as a mask, the control gate material layer 30, the isolation material layer 20, and the floating gate material layer 12 that are exposed are etched in sequence, further including: the gate oxide layer 11 is etched, i.e. after the floating gate material layer 12 is etched, the gate oxide layer 11 is etched further to expose a portion of the semiconductor substrate 100. Wherein a dry etching process is used when the exposed control gate material layer 30, the isolation material layer 20, the floating gate material layer 10, and the gate oxide layer are sequentially etched.
Then, step 6: removing the patterned photoresist layer 40 to expose the top surfaces of the first control gate 301, the second control gate 302 and the word line 19; an ashing process is preferably used to remove the patterned photoresist layer 40 to avoid residues of the patterned photoresist layer 40.
Then, step S7 is performed, referring to fig. 19, a metal silicide 303 is formed, and the metal silicide 303 covers the top surface of the control gate layer and the top surface of the word line 19. Specifically, the metal silicide 303 covers the top surface of the first control gate 301, the top surface of the second control gate 302, and the top surface of the word line 19, and because the top surfaces of the word line and the first control gate are flush with the top surface of the second control gate, compared with the prior art, when a contact structure aligned to the first control gate 301 and the second control gate 302 is formed later, a process window for photolithography and etching of the contact structure can be increased. Further, since the top surfaces of the first control gate 301 and the second control gate 302 are exposed, a metal silicide 303 can be formed on the top surfaces of both, compared with the prior art (the control gate in the prior art is usually covered with a process layer, and thus the metal silicide cannot be directly formed on the control gate), the contact resistance of the control gate can be reduced by connecting the metal silicide 303 with the subsequently formed contact structure 305, that is, the contact resistance between the contact structure 305 and the first control gate 301 or the second control gate 302 is reduced, so that the problem of larger contact resistance of the control gate in the prior art is solved.
Specifically, the method for forming the metal silicide 303 includes: a metal layer is formed, and the metal layer covers and exposes the top surface of the first control gate 301, the top surface of the second control gate 302, and the top surface of the word line 19, wherein the metal layer is made of at least one of titanium, zirconium, tantalum, tungsten, manganese, nickel, and copper. Then, the semiconductor substrate 10 is annealed to react the metal in the metal layer with silicon in the top surface of the first control gate 301, the top surface of the second control gate 302 and the top surface of the word line 19, thereby forming the metal silicide 303, and the annealing is preferably performed by using a gas containing hydrogen or nitrogen to eliminate trace oxygen in the annealing environment and prevent the metal in the metal layer from being oxidized; and performing a cleaning process to remove the unreacted metal layer on the top surfaces of the first control gate 301, the second control gate 302 and the word line 19.
Next, referring to fig. 20, a dielectric layer 304 is formed, and the dielectric layer 304 covers the metal silicide 303 and the exposed semiconductor substrate 100; the dielectric layer 304 may be silicon oxide, which may isolate the subsequently formed contact structures 305.
A plurality of contact structures 305 are formed in the dielectric layer 304, and the plurality of contact structures 305 are aligned with the first control gate 301, the second control gate 302, and the word line 19, respectively.
At least three contact structures 305, for example a first contact structure 305a, a second contact structure 305b and a third contact structure 305c, are formed in the dielectric layer 304, the first contact structure 305a being aligned with the first control gate 301 for connection of the first control gate 301 to an external circuit. The second contact structure 305b is aligned to the word line 19 for connection of the word line 301 to external circuitry. The third contact structure 305c is aligned to the second control gate 302 for connection between the second control gate 302 and an external circuit.
Further, due to the presence of the metal silicide 303 on the top surfaces of the first control gate 301 and the second control gate 302, the first control gate 301 and the second control gate 302 may be easily connected out through the contact structure 305, and the metal silicide 303 may reduce the contact resistance between the first control gate 301, the first control gate 301 or the word line 19 and the contact structure 305, thereby increasing the contact voltage.
In summary, in the method for manufacturing the split gate flash memory device provided by the present invention, the top surface of the control gate material layer is level with the top surface of the word line, then a photoresist layer is formed on the control gate material layer and the word line, and the photoresist layer is exposed and developed to form a patterned photoresist layer, so that the photoresist is prevented from remaining between the word line and the control gate material layer; sequentially etching the exposed control gate material layer and floating gate material layer by taking the patterned photoresist layer as a mask to form a control gate layer and a floating gate layer; and removing the patterned photoresist layer to expose the top surface of the control gate material layer and the top surface of the word line to form metal silicide, wherein the metal silicide covers the top surface of the control gate material layer and the top surface of the word line, so that the contact resistance of the control gate layer can be reduced due to the existence of the metal silicide.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (10)
1. A method of manufacturing a split gate flash memory device, comprising:
providing a semiconductor substrate, wherein a floating gate material layer, a mask layer, a side wall and a word line are formed on the semiconductor substrate in sequence, the word line penetrates through the floating gate material layer, and the side wall is positioned between the word line and the mask layer;
removing the mask layer to expose the floating gate material layer and the side wall of the side wall far away from the word line side;
forming a control gate material layer on the floating gate material layer, wherein the top surface of the control gate material layer is flush with the top surface of the word line;
forming a photoresist layer on the control gate material layer and the word line, and exposing and developing the photoresist layer to form a patterned photoresist layer, wherein a part of the control gate material layer is exposed out of the patterned photoresist layer;
sequentially etching the exposed control gate material layer and the exposed floating gate material layer by taking the patterned photoresist layer as a mask to form a control gate layer and a floating gate layer;
removing the patterned photoresist layer to expose the top surface of the control gate layer and the top surface of the word line; and
forming a metal silicide, wherein the metal silicide covers the top surface of the control gate layer and the top surface of the word line.
2. The method for manufacturing the split gate flash memory device according to claim 1, wherein the method for sequentially forming the floating gate material layer, the mask layer, the side wall and the word line on the semiconductor substrate comprises:
forming a floating gate material layer and a mask layer on the semiconductor substrate in sequence, wherein the floating gate material layer covers the semiconductor substrate;
forming a first opening in the mask layer, wherein the first opening exposes part of the floating gate material layer;
forming a side wall material layer through a chemical vapor deposition process, wherein the side wall material layer covers the side wall and the bottom wall of the first opening and extends to cover the top surface of the mask layer;
removing the top surface of the mask layer and the side wall material layer of the bottom wall of the first opening to form the side wall, and defining a second opening by the side wall covering the opposite side wall of the first opening;
etching the exposed floating gate material layer by taking the side wall as a mask so that the second opening extends to penetrate through the floating gate material layer;
forming a word line material layer filling the second opening and extending to cover a top surface of the mask layer;
and removing the word line material layer on the top surface of the mask layer to form word lines.
3. The method of manufacturing a split gate flash memory device of claim 2, wherein after etching the exposed floating gate material layer using the sidewall as a mask, the method of manufacturing a split gate flash memory device further comprises, prior to forming the word line: and forming a tunneling oxide layer, wherein the tunneling oxide layer covers the side wall and the bottom wall of the second opening, and the word line is positioned on the tunneling oxide layer.
4. The method of manufacturing a split gate flash memory device of claim 2, wherein a gate oxide layer is further formed between the floating gate material layer and the semiconductor substrate, and the second opening further extends through the gate oxide layer.
5. The method for manufacturing the split gate flash memory device according to claim 4, wherein when the patterned photoresist layer is used as a mask, the control gate material layer and the floating gate material layer exposed are sequentially etched, further comprising: and etching the gate oxide layer to expose a part of the semiconductor substrate.
6. The method of manufacturing a split gate flash memory device of claim 1, wherein after removing the mask layer, before forming a control gate material layer on the floating gate material layer, the method of manufacturing a flash memory device further comprises:
forming an isolation material layer, wherein the isolation material layer covers the top surface of the floating gate material layer, the top surface of the word line and the exposed side wall of the side wall; the isolation material layer comprises a first oxide layer, a nitride layer covering the first oxide layer and a second oxide layer covering the nitride layer.
7. The method of manufacturing a split gate flash memory device of claim 6, wherein the method of forming a control gate material layer on the floating gate material layer comprises:
forming a control gate material layer, wherein the control gate material layer covers the isolation material layer;
and removing the isolation material layer and the control grid material layer on the top surface of the word line so that the top surface of the control grid material layer is level with the top surface of the word line.
8. The method for manufacturing the split gate flash memory device according to claim 7, wherein when the exposed control gate material layer and the floating gate material layer are sequentially etched using the patterned photoresist layer as a mask, further comprising: and etching the isolation material layer to form an isolation layer, wherein the isolation layer comprises a first isolation layer and a second isolation layer which are respectively positioned at two sides of the word line.
9. The method of manufacturing a split gate flash memory device of claim 1, wherein the control gate layer includes a first control gate and a second control gate on both sides of the word line, respectively, and the floating gate layer includes a first floating gate and a second floating gate on both sides of the word line, respectively, the first floating gate and the second floating gate exposing a portion of the semiconductor substrate.
10. The method of manufacturing a split gate flash memory device of claim 9, wherein after forming the metal silicide, the method of manufacturing a split gate flash memory device further comprises:
forming a dielectric layer, wherein the dielectric layer covers the metal silicide and the exposed semiconductor substrate; the method comprises the steps of,
and forming a plurality of penetrating contact structures in the dielectric layer, wherein the contact structures are respectively aligned to the first control gate, the second control gate and the word line.
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