CN105140187A - Embedded flash memory structure and preparation method thereof - Google Patents
Embedded flash memory structure and preparation method thereof Download PDFInfo
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- CN105140187A CN105140187A CN201510470543.4A CN201510470543A CN105140187A CN 105140187 A CN105140187 A CN 105140187A CN 201510470543 A CN201510470543 A CN 201510470543A CN 105140187 A CN105140187 A CN 105140187A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 24
- 230000005641 tunneling Effects 0.000 claims abstract description 48
- 238000007667 floating Methods 0.000 claims abstract description 24
- 239000000463 material Substances 0.000 claims description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 25
- 229920005591 polysilicon Polymers 0.000 claims description 25
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 19
- 229910052710 silicon Inorganic materials 0.000 claims description 19
- 239000010703 silicon Substances 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 17
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 16
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 238000003701 mechanical milling Methods 0.000 claims description 3
- 238000011049 filling Methods 0.000 claims description 2
- 235000012239 silicon dioxide Nutrition 0.000 claims description 2
- 230000008878 coupling Effects 0.000 abstract description 7
- 238000010168 coupling process Methods 0.000 abstract description 7
- 238000005859 coupling reaction Methods 0.000 abstract description 7
- 238000005516 engineering process Methods 0.000 abstract description 5
- 230000009467 reduction Effects 0.000 abstract description 3
- 230000003647 oxidation Effects 0.000 abstract description 2
- 238000007254 oxidation reaction Methods 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 230000008021 deposition Effects 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 238000004064 recycling Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention relates to the technical field of semiconductor devices, in particular to an embedded flash memory structure and a preparation method thereof. According to the preparation method, reduction of the coupling ratio of an erasing gate to a floating gate is achieved by optimizing the order of a technology and improving the technology before a second tunneling oxidation layer between the erasing gate and the floating gate deposits, so that the erasing efficiency of a 55nm embedded flash memory is effectively improved.
Description
Technical field
The present invention relates to technical field of semiconductor device, particularly relate to a kind of embedded flash memory structure and preparation method thereof.
Background technology
As everyone knows, the size of the coupling ratio between the erase gate of the embedded flash memory of 55nm and floating boom directly affects the efficiency of erasing of embedded flash memory (eflash), be the side wall of deposition of silica and silicon nitride after control gate completes in current techniques, then carry out side wall etching and form side wall layer.Recycling side wall layer carries out the etching of floating boom to form the crossover region between erase gate and floating boom as autoregistration.
Employing deposits one deck second tunneling oxide layer between floating boom and erase gate makes the method for floating boom and erase gate isolation address this problem to reach, this kind of method improves the efficiency of erasing of embedded flash memory really to a certain extent, but this dependence the method making erase gate is difficult to continue to reduce to the coupling ratio of floating boom.
Therefore, how to continue to reduce erase gate and become to improve 55nm embedded flash memory efficiency of erasing a great problem that those skilled in the art face to the coupling ratio of floating boom.
Summary of the invention
In view of the above problems, the invention provides structure of a kind of embedded flash memory and preparation method thereof, be intended to the efficiency of erasing improving flash memory, by the order of Optimization Technology, improve the presedimentary technique of the second tunneling oxide layer between erase gate to floating boom, to realize the reduction of erase gate to the coupling ratio of floating boom, this technical scheme is specially:
A preparation method for embedded flash memory structure, wherein, described method comprises:
One silicon substrate is provided, and described silicon substrate is preset with the first device area and the second device area;
The first tunneling oxide layer, floating gate polysilicon layer, ONO layer, control gate polysilicon layer and silicon nitride layer is prepared successively according to order from bottom to up on described silicon substrate;
Etch described silicon nitride layer, described control gate polysilicon layer and the described ONO layer upper surface to described control gate polysilicon layer successively, to form the first opening and form the second opening on the described silicon substrate being positioned at described first device area on the described silicon substrate being positioned at described second device area;
Utilize the first open bottom described in mask etching to the upper surface of described first tunneling oxide layer, to form the first groove, and etch the upper surface of described second open bottom to described first tunneling oxide layer, to form the second groove;
Oxide layer and the second tunneling oxide layer is prepared in described first groove;
In described first opening and the first groove, prepare erase gate and prepare wordline grid in described second opening and described second groove.
The preparation method of above-mentioned embedded flash memory, wherein, the method for described first groove of described formation and described second groove also comprises:
Layer deposited isolating material makes described insolated layer materials fill full described first opening and described second opening;
Etch described side wall layer material and the described floating gate polysilicon layer upper surface to described first tunneling oxide layer successively, form the first groove with the below of described first opening and form the second groove in the below of described second opening.
The preparation method of above-mentioned embedded flash memory, wherein, the step preparing oxide layer and the second tunneling oxide layer in described method in the first groove also comprises:
Filling oxide layer material in described first groove, described first opening, described second groove and described second opening;
Utilize mechanical milling tech by the upper surface planarization of described oxide layer, the upper surface of the upper surface of described oxide layer and described silicon nitride layer is the level of state;
Etch the oxide layer retaining predetermined thickness in described oxide layer to described first groove, the second groove;
Depositing the second tunneling oxide layer material makes described second tunneling oxide layer material fill described first groove, described first opening, described second groove and described second opening;
Adopt reserve part second tunneling oxide layer and remove the oxide layer of described second bottom portion of groove and be positioned at the second tunneling oxide layer of described oxide layer in described second tunneling oxide layer to the first groove of etching.
The preparation method of above-mentioned embedded flash memory, wherein, the step forming described erase gate and described wordline grid also comprises:
In described first opening and described second opening depositing polysilicon material;
Etch the polysilicon material layer in described first opening and described second opening, in the first opening, form erase gate, in described second opening, form wordline grid.
The preparation method of above-mentioned embedded flash memory, wherein, the thickness of described oxide layer is 180 dust-220 dusts.
The preparation method of above-mentioned embedded flash memory, wherein, the material of described mask is silicon dioxide or silicon nitride.
A kind of embedded flash memory, wherein, described embedded flash memory comprises:
Silicon substrate, is provided with the first device region and the second device region; And
Above described silicon substrate, preparation has tunneling oxide layer, floating gate polysilicon layer, ONO layer, control gate polysilicon layer and silicon nitride layer successively from the bottom up;
First through hole, is arranged at the upper surface of the tunneling oxide layer of the top of described first device region;
Second through hole, is arranged at the upper surface of the tunneling oxide layer of the top of described second device region;
Erasing grid, is arranged in described first through hole;
Wordline grid, is arranged in described second through hole.
Above-mentioned embedded flash memory, wherein, be also provided with oxide layer in described first through hole, described oxide layer is between described tunneling oxide layer and described erasing grid.
Above-mentioned embedded flash memory, wherein, is provided with side wall layer between described erasing grid and described first through hole.
Above-mentioned embedded memory, wherein, is provided with side wall layer between described wordline grid and described second through hole.
Technique scheme tool has the following advantages or beneficial effect:
Adopt the technical program, effectively reduce the coupling ratio of erase gate and floating boom, thus effectively improve the efficiency of erasing of 55nm embedded flash memory.
Accompanying drawing explanation
With reference to appended accompanying drawing, to describe embodiments of the invention more fully.But, appended accompanying drawing only for illustration of and elaboration, do not form limitation of the scope of the invention.
Fig. 1 is preparation method's flow chart of embedded flash memory in example of the present invention;
Fig. 2-7 is the structural representation of embedded flash memory manufacturing process in the embodiment of the present invention;
Fig. 8 is the structural representation of embedded flash memory in the embodiment of the present invention.
Embodiment
In order to allow the personnel possessing field Conventional wisdom belonging to this invention easily implement this invention, with reference to accompanying drawing shown below, the example of this invention is described in detail.But this invention can be implemented according to different forms, is not only confined to example described herein.In order to definitely this invention is described, eliminate part irrelevant with explanation in drawing; And, in whole specification, give similar drawing symbol to similar portions.
In the whole specification of this invention, some parts and another part " connection ", not only comprise " directly connecting ", also comprise " the electrical resistance connection " that be connected by other components and parts.
In the whole specification of this invention, some parts are positioned at " top " of another parts, not only comprise the state of some parts and another parts joint, also comprise the state being also provided with another parts between two parts.
In the whole specification of this invention, certain part " comprises " certain inscape and refers to, under the prerequisite of not forbidding equipment especially, is not get rid of other inscapes, but can also comprises other inscapes.
The terms of degree " about ", " in fact " etc. that adopt in the whole specification of this invention, if prompting has manufacture and material admissible error, with regard to expression respective value or close to this numerical value; Its objective is, prevent bad personnel that the disclosure relating to exact value or absolute figure is used for improper purposes.The terms of degree that uses in the whole specification of this invention " ~ (in) stage " or " ~ stage ", be not " in order to ~ stage ".
' parts ' in this specification refer to, the unit (unit) be made up of hardware, the unit by software sharing, the unit that is made up of software and hardware.
In addition, unit can be made up of plural hardware or plural unit is made up of a hardware.In this specification, the operation implemented by terminal, device or equipment or function, a part wherein can utilize the server generation be connected with corresponding terminal, device or equipment for implementing.Equally, by operation or the function of server implementation, a part wherein also can utilize terminal, device or the equipment be connected with this server to replace implementing.Next, with reference to accompanying drawing, the example of this invention is described in detail.
With reference to structure shown in Fig. 1, for improving preparation method's flow chart of 55nm embedded flash memory in one embodiment of the invention, the embedded flash memory prepared by the method can improve the efficiency of erasing of 55nm embedded flash memory.
First, provide a silicon substrate 1, and on silicon substrate, deposit the first tunneling oxide layer 2, floating gate polysilicon layer 3, ONO layer 4, control gate polysilicon layer 5 and silicon nitride layer 6 successively, form structural representation as shown in Figure 2.
Upper surface in silicon nitride starts etching, form the first opening 7 and the second opening 8 from left to right successively, structure shown in Figure 3, wherein, this etching stopping is in the upper surface of floating gate polysilicon layer 3, and as a kind of preferred embodiment, the cross-sectional area of the first opening 7 is less than the cross-sectional area of the second opening 8, wherein, this etching adopts dry etching.
Continue precipitation mask material, make this mask material fill full described first opening 7 and described second opening 8, wherein, this mask material is silica or silicon nitride.
Respectively at the mask layer etching in described first opening 7 and described second opening 8, namely mask layer is retained, etching from the surface of the close opening of the mask layer of the mask layer of the first opening and the second opening, when being etched to open bottom, during the upper surface of i.e. floating gate polysilicon layer 3, continue to etch downwards, until the upper surface of the first tunneling oxide layer 2, namely the below respectively at the first opening 7 and the second opening 8 forms the first groove 9 and the second groove 10, forms structural representation as shown in Figure 4.
Continue deposited oxide layer material, described oxide layer materials is made to fill full first opening 7, described second opening 8, first groove 9 and the second groove 10, after layer material to be oxidized fills full first opening 7 and the second opening 8, adopt mechanical milling tech, make the upper surface of the oxide layer in the first opening 7 and the second opening 8 be in same level with the upper surface without the silicon nitride etched, form structural representation as described in Figure 5.
Mask layer in the first opening 7 and the second opening 8 starts etching, i.e. removal part is positioned at the portion of oxide layer of original first opening and the second opening, the gross thickness of the oxide layer in the first groove and the oxide layer in the first opening is made to be 180 dust-220 dust (180 dusts, 190 dusts, 200 dusts, 220 dusts), as a preferred embodiment of the invention, after etching, remaining first groove is interior is 200 dusts with the gross thickness of the first opening inner groovy, wherein, this process adopts wet etching, forms structural representation as shown in Figure 6.
Continue at deposition the second tunneling oxide layer material in the first opening and the second opening, deposit rear part second tunneling oxide layer adopting the mode of etching to remove deposition, it should be noted that, the sidewall of the first opening retains certain thickness second tunneling oxide layer, form the sidewall 11 and 12 of the first opening, the sidewall of the second opening retains certain thickness second tunneling oxide layer, form the sidewall 13 and 14 of the second opening, simultaneously, the upper surface of the first opening internal oxidation layer retains the second tunneling oxide layer of certain depth, as one preferred embodiment, the thickness of the second tunneling oxide layer of the first opening sidewalls is identical with the thickness of the second more than oxide layer upper surface tunneling oxide layer, meanwhile, adopt the second tunneling oxide layer that the method for etching is removed the oxide layer bottom the second groove 10 and is positioned in oxide layer, the mode that this process mainly adopts dry etching and wet etching to combine, forms structural representation shown in Figure 7.
Continue at deposit spathic silicon in the first opening 7 and the second opening 8 and the first groove 9 and the second groove 10, simultaneously in the first opening and the second opening etching, preferably, this etching according to the first opening with the surface of the close opening of the second tunneling oxide layer of the second opening, etch the polysilicon of certain depth in reservation first opening and the second opening, form erase gate 15 and wordline grid 16, form structural representation shown in Figure 8.
Structure shown in Figure 8, the present invention also provides a kind of embedded flash memory, and wherein, this embedded flash memory comprises:
Silicon substrate 1, is provided with the first device region and the second device region; And
Above described silicon substrate, preparation has the first tunneling oxide layer 2, floating gate polysilicon layer 3, ONO layer 4, control gate polysilicon layer 5 and silicon nitride layer 6 successively from the bottom up.Wherein, the upper surface of the first tunneling oxide layer of the top of the first device region is provided with the first through hole, and wherein the first through hole is made up of the first groove and the first opening, and the second through hole is made up of the second groove and the second opening.Erasing grid 15 is set in the first through hole, wordline grid 16 are set in the second through hole.
As a preferred embodiment of the invention, be also provided with oxide layer in the first through hole, this oxide layer is between the first tunneling oxide layer 2 and described erasing grid 15.
As a preferred embodiment of the invention, between erasing grid and described first through hole, be provided with side wall layer 11 and side wall layer 12.
As a preferred embodiment of the invention, between wordline grid 16 and the second through hole, be provided with side wall layer 13 and side wall layer 14.
In sum, the present invention, by the order of Optimization Technology, improves the presedimentary technique of the second tunneling oxide layer between erase gate to floating boom, to realize the reduction of erase gate to the coupling ratio of floating boom, thus effectively improves the efficiency of erasing of 55nm embedded flash memory.
Foregoing this invention related description is only limited to some examples; As long as possess the Conventional wisdom of this invention art, without the need to changing the technical thought of this invention or necessary feature, just this invention can be changed to other forms.Therefore, foregoing example contains any one example of this invention, is not limited only to the form in this specification.Such as, each inscape being defined as single type dispersibles enforcement; Equally, be defined as the inscape of dispersion, also can implement with combining form.
The category of this invention is not limited to above-mentioned detailed description, patent claim described after can containing; All changes of deriving from the definition of patent claim, scope and equivalent conception or change form and include in the category of this invention.
Claims (10)
1. a preparation method for embedded flash memory structure, is characterized in that, described method comprises:
One silicon substrate is provided, and described silicon substrate is preset with the first device area and the second device area;
The first tunneling oxide layer, floating gate polysilicon layer, ONO layer, control gate polysilicon layer and silicon nitride layer is prepared successively according to order from bottom to up on described silicon substrate;
Etch described silicon nitride layer, described control gate polysilicon layer and the described ONO layer upper surface to described control gate polysilicon layer successively, to form the first opening and form the second opening on the described silicon substrate being positioned at described first device area on the described silicon substrate being positioned at described second device area;
Utilize the first open bottom described in mask etching to the upper surface of described first tunneling oxide layer, to form the first groove, and etch the upper surface of described second open bottom to described first tunneling oxide layer, to form the second groove;
Oxide layer and the second tunneling oxide layer is prepared in described first groove;
In described first opening and the first groove, prepare erase gate and prepare wordline grid in described second opening and described second groove.
2. the preparation method of embedded flash memory as claimed in claim 1, it is characterized in that, the step forming described first groove and described second groove in described method also comprises:
Layer deposited isolating material makes described insolated layer materials fill full described first opening and described second opening;
Etch described side wall layer material and the described floating gate polysilicon layer upper surface to described first tunneling oxide layer successively, form the first groove with the below of described first opening and form the second groove in the below of described second opening.
3. the preparation method of embedded flash memory as claimed in claim 1, it is characterized in that, the step preparing oxide layer and the second tunneling oxide layer in described method in the first groove also comprises:
Filling oxide layer material in described first groove, described first opening, described second groove and described second opening;
Utilize mechanical milling tech by the upper surface planarization of described oxide layer, the upper surface of the upper surface of described oxide layer and described silicon nitride layer is the level of state;
Etch the oxide layer retaining predetermined thickness in described oxide layer to described first groove, the second groove;
Depositing the second tunneling oxide layer material makes described second tunneling oxide layer material fill described first groove, described first opening, described second groove and described second opening;
Adopt reserve part second tunneling oxide layer and remove the oxide layer of described second bottom portion of groove and be positioned at the second tunneling oxide layer of described oxide layer in described second tunneling oxide layer to the first groove of etching.
4. the preparation method of embedded flash memory as claimed in claim 1, it is characterized in that, the step forming erase gate and described wordline grid in described method also comprises:
In described first opening and described second opening depositing polysilicon material;
Etch the polysilicon material layer in described first opening and described second opening, in the first opening, form erase gate, in described second opening, form wordline grid.
5. the preparation method of embedded flash memory as claimed in claim 1, it is characterized in that, the thickness of described oxide layer is 180 dust-220 dusts.
6. the preparation method of embedded flash memory as claimed in claim 1, it is characterized in that, the material of described mask is silicon dioxide or silicon nitride.
7. an embedded flash memory, is characterized in that, based on the preparation method as the embedded flash memory in claim 1 ~ 6 as described in any one, described embedded flash memory comprises:
Silicon substrate, is provided with the first device region and the second device region; And
Above described silicon substrate, preparation has tunneling oxide layer, floating gate polysilicon layer, ONO layer, control gate polysilicon layer and silicon nitride layer successively from the bottom up;
First through hole, is arranged at the upper surface of the tunneling oxide layer of the top of described first device region;
Second through hole, is arranged at the upper surface of the tunneling oxide layer of the top of described second device region;
Erasing grid, is arranged in described first through hole;
Wordline grid, is arranged in described second through hole.
8. embedded flash memory as claimed in claim 7, it is characterized in that, be also provided with oxide layer in described first through hole, described oxide layer is between described tunneling oxide layer and described erasing grid.
9. embedded flash memory as claimed in claim 7, is characterized in that, be provided with side wall layer between described erasing grid and described first through hole.
10. embedded memory as claimed in claim 7, is characterized in that, be provided with side wall layer between described wordline grid and described second through hole.
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| CN201510470543.4A CN105140187A (en) | 2015-08-04 | 2015-08-04 | Embedded flash memory structure and preparation method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106449389A (en) * | 2016-10-21 | 2017-02-22 | 武汉新芯集成电路制造有限公司 | Embedded flash memory structure and manufacturing method thereof |
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| TW200802816A (en) * | 2006-06-27 | 2008-01-01 | Powerchip Semiconductor Corp | Non-volatile memory and manufacturing method thereof |
| US20080248620A1 (en) * | 2007-04-09 | 2008-10-09 | Shih-Chang Liu | Gated semiconductor device and method of fabricating same |
| CN102543885A (en) * | 2010-12-31 | 2012-07-04 | 中芯国际集成电路制造(上海)有限公司 | Split-gate memory device and forming method thereof |
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- 2015-08-04 CN CN201510470543.4A patent/CN105140187A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200802816A (en) * | 2006-06-27 | 2008-01-01 | Powerchip Semiconductor Corp | Non-volatile memory and manufacturing method thereof |
| US20080248620A1 (en) * | 2007-04-09 | 2008-10-09 | Shih-Chang Liu | Gated semiconductor device and method of fabricating same |
| CN102543885A (en) * | 2010-12-31 | 2012-07-04 | 中芯国际集成电路制造(上海)有限公司 | Split-gate memory device and forming method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106449389A (en) * | 2016-10-21 | 2017-02-22 | 武汉新芯集成电路制造有限公司 | Embedded flash memory structure and manufacturing method thereof |
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Application publication date: 20151209 |