CN109065547B - Method for manufacturing three-dimensional memory - Google Patents
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- CN109065547B CN109065547B CN201811109480.XA CN201811109480A CN109065547B CN 109065547 B CN109065547 B CN 109065547B CN 201811109480 A CN201811109480 A CN 201811109480A CN 109065547 B CN109065547 B CN 109065547B
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- 238000000034 method Methods 0.000 title claims abstract description 48
- 230000015654 memory Effects 0.000 title claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 239000000463 material Substances 0.000 claims abstract description 60
- 238000005530 etching Methods 0.000 claims abstract description 31
- 239000004065 semiconductor Substances 0.000 claims abstract description 29
- 239000010410 layer Substances 0.000 claims description 320
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 229910017052 cobalt Inorganic materials 0.000 claims description 7
- 239000010941 cobalt Substances 0.000 claims description 7
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 7
- 238000005240 physical vapour deposition Methods 0.000 claims description 7
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 7
- 229910052721 tungsten Inorganic materials 0.000 claims description 7
- 239000010937 tungsten Substances 0.000 claims description 7
- 238000001883 metal evaporation Methods 0.000 claims description 6
- 238000004544 sputter deposition Methods 0.000 claims description 6
- 239000011241 protective layer Substances 0.000 claims description 5
- 238000004140 cleaning Methods 0.000 description 6
- 239000011810 insulating material Substances 0.000 description 6
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 239000006117 anti-reflective coating Substances 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 230000000149 penetrating effect Effects 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000012876 topography Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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Abstract
The invention provides a method for manufacturing a three-dimensional memory, which comprises the following steps: providing a semiconductor structure, wherein the semiconductor structure comprises a stacked structure, the stacked structure comprises a first material layer and a second material layer which are alternately stacked, and a step structure is formed at the edge of the stacked structure, the step structure is provided with a plurality of steps, and the edge of at least part of the first material layer forms the top surface of the step; forming a conductive layer covering a top surface of the step and an insulating layer covering the conductive layer; forming a contact structure through the insulating layer and connected to the conductive layer. Compared with the prior art, the conducting layer covers the grid layer, so that the thickness of the grid layer is thicker and the grid layer is not easy to etch through, and the risk of etching through is greatly reduced.
Description
Technical Field
The invention mainly relates to the field of semiconductor manufacturing, in particular to a manufacturing method of a three-dimensional memory.
Background
To overcome the limitations of the two-dimensional memory device, the industry has developed a memory device having a three-dimensional (3D) structure to increase integration density by arranging memory cells three-dimensionally over a substrate.
In a three-dimensional memory device such as a 3D NAND flash memory, a memory array may include a core (core) region and a staircase region. The step region is used for leading out a contact part of a gate layer in each layer of the memory array. These gate layers are used as word lines of the memory array to perform programming, erasing, reading, etc.
In the manufacturing process of the 3D NAND flash memory, contact holes are formed on all levels of stepped structures in a stepped area in an etching mode, and then the contact holes are filled, so that electric signals of a grid layer are led out. In the actual production process, because the number of the 3D-NAND flash memory ladder layers is large, in the step of etching the contact hole, in order to ensure that the lower ladder layer can be smoothly led out, the upper ladder layer is easily etched by over etching (OverEtch), and etching Through holes (Punch Through) occur, so that the grid metal layers are mutually short-circuited, and the product yield is reduced.
In order to solve the above problem, it is often necessary to perform light irradiation and etching a plurality of times, thereby reducing the depth difference at each etching.
Disclosure of Invention
The invention aims to solve the technical problem of a manufacturing method of a three-dimensional memory, which can overcome the problems of etching defects of word line connecting areas and the like and does not need to carry out multiple times of illumination and etching.
In order to solve the technical problem, the invention provides a method for manufacturing a three-dimensional memory, which comprises the following steps: providing a semiconductor structure, wherein the semiconductor structure comprises a stacked structure, the stacked structure comprises a first material layer and a second material layer which are alternately stacked, and a step structure is formed at the edge of the stacked structure, the step structure is provided with a plurality of steps, and the edge of at least part of the first material layer forms the top surface of the step; forming a conductive layer covering a top surface of the step and an insulating layer covering the conductive layer; forming a contact structure through the insulating layer and connected to the conductive layer.
In an embodiment of the invention, the first material layer is a dummy gate layer, the second material layer is a dielectric layer, and the dummy gate layer is removed to form a gap between the dielectric layers and a gate layer is formed in the gap.
In an embodiment of the invention, a method of forming the conductive layer covering the top surface of the step is physical vapor deposition, metal sputtering or metal evaporation.
In an embodiment of the invention, projections of the conductive layers of adjacent steps on the bottom surface of the stacked structure are end-to-end.
In an embodiment of the invention, the conductive layer and the first material layer are both made of tungsten or cobalt.
In an embodiment of the invention, the thickness of the conductive layer is 10-100 nm.
In an embodiment of the present invention, before forming the step structure at the edge of the stacked structure, the method further includes: a virtual channel hole is formed on the stacked structure.
In an embodiment of the invention, before forming the conductive layer covering the top surface of the step, the method further includes: and back-etching to remove at least one part of at least one second material layer, so that the side surface of at least one second material layer is recessed relative to the first material layer on the second material layer, thereby avoiding short circuit connection between the conductive layers.
In an embodiment of the invention, the insulating layer covering the conductive layer includes planarizing the insulating layer.
In an embodiment of the invention, a passivation layer covers the insulating layer when the insulating layer is planarized.
In an embodiment of the present invention, the step of forming a contact structure passing through the insulating layer and connected to the conductive layer includes: and etching the insulating layer on the stepped structure to form a plurality of contact holes exposing the first material layer on the top surface of each step of the stepped structure.
Compared with the prior art, the invention has the following advantages: the invention provides a manufacturing method of a three-dimensional memory, wherein a semiconductor device of the three-dimensional memory comprises a core area and a step area, the step area is provided with a step structure, the step structure is provided with a plurality of steps, each step comprises at least one gate layer and at least one dielectric layer which are alternately stacked from top to bottom, the edge of at least one gate layer forms the top surface of the step, a conductive layer is formed on the top surface of the step, and a contact part is connected onto the conductive layer. It can be seen that, since the gate layer is covered with the conductive layer, the thickness of the gate layer is thicker and is not easily etched through, so that the risk of etching through is greatly reduced.
Drawings
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below, wherein:
FIGS. 1A-1F are flow diagrams of a method of fabricating a three-dimensional memory.
Fig. 2A-2B are schematic structural diagrams of a three-dimensional memory.
Fig. 3 is a flowchart of a method for fabricating a three-dimensional memory according to an embodiment of the invention.
Fig. 4A-4E are cross-sectional views illustrating exemplary processes of a method for fabricating a three-dimensional memory according to an embodiment of the invention.
Fig. 5A-5D are exemplary processes for planarizing an insulating layer, in accordance with an embodiment of the present invention.
Fig. 6 is a schematic structural diagram of a three-dimensional memory according to an embodiment of the invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.
As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements.
In describing the embodiments of the present invention in detail, the cross-sectional views illustrating the structure of the device are not enlarged partially in a general scale for convenience of illustration, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary words "below" and "beneath" can encompass both an orientation of up and down. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein should be interpreted accordingly. Further, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
As introduced in the background, in a three-dimensional memory device such as a 3D NAND flash memory, a memory array may include a core (core) region and a staircase region. The step region is used for leading out a contact part of a gate layer in each layer of the memory array. These gate layers are used as word lines of the memory array to perform programming, erasing, reading, etc.
In the manufacturing process of the 3D NAND flash memory, contact holes are formed on all levels of stepped structures in a stepped area in an etching mode, and then the contact holes are filled, so that electric signals of a grid layer are led out. In the actual production process, because the number of the 3D-NAND flash memory ladder layers is large, in the step of etching the contact hole, in order to ensure that the lower ladder layer can be smoothly led out, the upper ladder layer is easily etched by over etching (OverEtch), and etching Through holes (Punch Through) occur, so that the grid metal layers are mutually short-circuited, and the product yield is reduced.
FIGS. 1A-1F are flow diagrams of a method of fabricating a three-dimensional memory. The manufacturing method mainly comprises the step of etching and forming a contact hole on each step. The process of forming the contact hole includes forming a stacked structure 110 having dummy gate layers 101 and dielectric layers 102 stacked alternately as shown in fig. 1A, forming a stepped structure at the edge of the stacked structure 110 as shown in fig. 1B, covering an insulating layer 103 on the stacked structure 110 as shown in fig. 1C, and replacing the dummy gate layer 101 with a gate layer 104 as shown in fig. 1D, and finally forming a contact hole 106 through an etch mask 105 and filling the contact hole 106 to form a contact portion 107 as shown in fig. 1E and 1F, respectively.
As shown in fig. 1D, the step-region gate layer 104 is thin and is easily over-etched in this method. As shown in fig. 2A, when the contact hole 106 is etched, due to the large depth difference, when the deepest contact hole is etched to a right position, the shallowest contact hole may be etched through to cause a short circuit. In order to avoid over-etching of the shallowest contact hole, the vertical through holes corresponding to the metal gate layers in different regions are usually etched in a segmented manner, as shown in fig. 2B, the method needs to perform multiple steps of photoetching and etching, the cost and the time cost are high, the mass production rate is seriously influenced, and the more the number of stacked layers of the memory cells is, the more the photoetching and etching processes need to be performed.
Fig. 3 is a flowchart of a method for fabricating a three-dimensional memory according to an embodiment of the invention. Fig. 4A-4E are cross-sectional views illustrating exemplary processes of a method for fabricating a three-dimensional memory according to an embodiment of the invention. A method of fabricating a three-dimensional memory according to the present embodiment will be described with reference to fig. 3 to 4E.
In step 302, a semiconductor structure is provided.
The semiconductor structure is at least a portion of a structure that will be used in subsequent processing to ultimately form a three-dimensional memory device. The semiconductor structure may include an array region (array), which may include a core region (core) and a step region (SS). The core region is a region including memory cells, and the staircase region is a region including word line connection circuits. The stepped region may be located on at least one side of the core region. The array region may have a substrate and a stacked structure, a channel hole array may be formed on the stacked structure of the core region, and a dummy channel hole array may be formed on the stacked structure of the stepped region, the stacked structure including first material layers and second material layers alternately stacked, and a stepped structure formed at an edge, the stepped structure having a plurality of steps, and an edge of at least a portion of the first material layers constituting a top surface of the step. The first material layer may be a dummy gate layer or a gate layer. The second material layer may be a dielectric layer. For simplicity, the first material layer is a dummy gate layer, and the second material layer is a dielectric layer.
In the cross-sectional view of the semiconductor structure 400a illustrated in fig. 4A, the semiconductor structure 400a may include a stacked structure 410, and the stacked structure 410 may include a dummy gate layer 410a and a dielectric layer 410b that are alternately stacked. The stacked structure 410 is formed with a stepped structure at the edge. The staircase structure may include several steps depending on the number of layers (e.g., 32 or 64 layers) of the three-dimensional memory device being fabricated. In fig. 4A, 3 steps 411, 412 and 413 are exemplarily shown. Each step comprises one or more dielectric layers and one or more dummy gate layers which are alternately stacked from top to bottom, namely the dummy gate layers and the dielectric layers are alternately stacked, and the edge of at least one dummy gate layer forms the top surface of the step. Taking the step 412 as an example, it includes dummy gate layers 412a, dielectric layers 412b stacked alternately from top to bottom, and the edge of the dummy gate layer 412a constitutes the top surface of the step. It is understood that the steps 412 are not limited to the 2 layers illustrated herein, but may have other numbers, such as 4 layers, 6 layers, or more.
In an embodiment of the present invention, the semiconductor structure 400a may further include a virtual channel hole 420. The virtual channel hole 420 may be formed at the stepped region and/or the core region. The dummy channel hole 420 vertically penetrates the stacked structure of the semiconductor structure 400a, and is filled with, for example, an insulating material to provide support for the stacked structure. As an exemplary process of forming the virtual channel hole 420, a hard mask, an anti-reflective coating, and a photoresist may be sequentially coated on the stack structure; then photoetching and etching are carried out to form a virtual channel hole; carrying out wet cleaning on the virtual channel hole; the dummy channel hole is filled with an insulating material, such as silicon oxide. The step of forming the virtual channel hole 420 on the stacked structure may be performed before the step structure is formed at the edge of the stacked structure. It is understood that the dummy channel hole 420 does not completely block the dummy gate layer. The dummy channel hole 420 is only a hole structure penetrating a partial cross-sectional area of the dummy gate layer, and after the dummy gate layer is replaced with the gate layer, the control signal may still be transmitted to the core region through the gate layer.
In an embodiment of the present invention, the material of the dummy gate layer 412b may be silicon nitride. The material of the dielectric layer 412a is, for example, silicon oxide.
Although exemplary configurations of the initial semiconductor structure are described herein, it will be appreciated that one or more features may be omitted, substituted, or added to the semiconductor structure. In addition, the materials of the illustrated layers are merely exemplary, and other materials that are available in charge storage (CTF) three-dimensional NAND memories may be selected for the dummy gate layer 412b and the dielectric layer 412 a. For example, dummy gate layer 412b and dielectric layer 412a may also be a combination of silicon oxide and (undoped) polysilicon or amorphous silicon, a combination of silicon oxide or silicon nitride and amorphous carbon, and the like. For example, the step of forming the dummy channel hole 420 on the stacked structure may be omitted.
At step 304, at least a portion of at least one of the dielectric layers is etched back.
In this step, in order to avoid short-circuit connection between the conductive layers, at least a portion of at least one of the dielectric layers is removed, and the side surface of at least one of the dielectric layers is recessed relative to the dummy gate layer thereon. The method of etching back to remove at least a portion of at least one of the dielectric layers may include wet etching, for example, etching at least a portion of at least one of the dielectric layers using phosphoric acid as an etchant. The thickness of the etched dielectric layer may be the thickness of the dielectric layer in the stacked structure. The depth of the etch may be half the width of the dummy trench hole or less. In some embodiments of the present invention, the step of removing at least a portion of at least one of the dielectric layers may be omitted and the conductive layer may be directly covered on the top surface of the step.
In the cross-sectional view of semiconductor structure 400B illustrated in fig. 4B, a portion of dielectric layer 412B is removed such that the sides of dielectric layer 412B are recessed relative to dummy gate layer 412a thereon. The thickness of the etched dielectric layer 412b (in the vertical direction in the figure) is the thickness of the dielectric layer in the stacked structure. The depth of the etch (horizontal in the figure) is half the width of the dummy trench hole 420. It is understood that the depth of the etch may be other values, such as greater than or less than half the width of the virtual channel hole 420.
At step 306, a conductive layer covering the top surface of the step and an insulating layer covering the conductive layer are formed.
In this step, a conductive layer covering the top surface of the step and an insulating layer covering the conductive layer are formed. A conductive layer covers a top surface of the step and contacts the dummy gate layer of the step structure in the step region. The material of the conductive layer can be various conductive materials. In some embodiments of the invention, the material of the conductive layer is a metallic material. Preferably, the material of the conductive layer may be the same as that of the gate layer, for example, the material of the conductive layer and the material of the gate layer are both tungsten or cobalt. Methods of forming the conductive layer covering the top surface of the step may be Physical Vapor Deposition (PVD), Metal Sputtering, Metal Evaporation, and the like. The thickness and the appearance of the conducting layer need to ensure that the two dielectric layers above and below the conducting layer are not adhered. The projections of the conductive layers of adjacent steps on the bottom surface of the stacked structure are connected end to end, i.e. the conductive layers are formed only on the horizontal plane, the conductive layers are not formed on the side surfaces, and the adjacent conductive layers are still insulated. The thickness of the conductive layer may be 10-100 nm. The topography of the conductive layer may be flat. The width of the conductive layer may be approximately equal to the width of each step. In some embodiments of the present invention, after forming the conductive layer covering the top surface of the step, wet cleaning, wafer backside and dielectric layer side cleaning, etc. may be further included to remove a small amount of metal that may be contaminated, thereby facilitating subsequent processes. After forming a conductive layer covering the top surface of the step, an insulating layer covering the conductive layer is formed on the conductive layer. The insulating layer covering the conductive layer includes a planarization insulating layer.
In the cross-section of the semiconductor structure 400C shown in fig. 4C, the conductive layer 430 covers the top surface of the step and contacts the dummy gate layer of the step structure in the step region. The material of the conductive layer 430 may be various conductive materials. In some embodiments of the present invention, the material of the conductive layer 430 is a metal material. Preferably, the material of the conductive layer 430 may be the same as that of the gate layer, for example, the material of the conductive layer 430 and the material of the gate layer are both tungsten or cobalt. Methods of forming the conductive layer covering the top surface of the step may be Physical Vapor Deposition (PVD), Metal sputtering (Metal sputtering), Metal Evaporation (Metal Evaporation), and the like. The projections of the conductive layers 430 of adjacent steps on the bottom surface of the stacked structure 410 are end-to-end, i.e., the conductive layers 430 are formed only on the horizontal plane, the conductive layers 430 are not formed on the side surfaces, and the adjacent conductive layers 430 are still insulated. The thickness and morphology of the conductive layer 430 are required to ensure that the two dielectric layers above and below the conductive layer do not adhere. The thickness of the conductive layer 430 may be 50-200 nm. The topography of the conductive layer may be flat. The width of conductive layer 430 is approximately equal to the width of each step. After forming the conductive layer 430 covering the top surface of the step, wet cleaning, wafer backside and dielectric layer side cleaning, etc. may be further included to remove a small amount of metal that may be contaminated for subsequent processes.
In the cross section of the semiconductor structure 400D shown in fig. 4D, after the conductive layer 430 covering the top surface of the step is formed, an insulating layer 440 covering the conductive layer 430 is formed on the conductive layer 430. The insulating layer 440 covering the conductive layer 430 includes a planarization insulating layer 440.
In step 308, a contact structure is formed through the insulating layer and connected to the conductive layer.
In this step, a contact structure is formed through the insulating layer and connected to the conductive layer. The step of forming a contact structure through the insulating layer and connected to the conductive layer includes etching the insulating layer on the stepped structure to form contact holes exposing the gate layer at a top surface of each step of the stepped structure at one time, and filling the contact holes to form the contact structure. The step structure may be covered with an insulating material, and then a contact hole vertically penetrating the step region may be formed by one-time etching in a conventional manner. Contact holes extend vertically through the insulating material from the top surface to the first material layer at the top of each step structure.
The contact hole is formed by, for example, etching or other known methods, and is not limited herein.
The first material layer may be a dummy gate layer or a gate layer and the second material layer may be a dielectric layer. If the first material layer is a gate layer, a contact structure can be directly formed; if the first material layer is a dummy gate layer, the dummy gate layer is required to replace the gate layer. The method for replacing the dummy gate layer with the gate layer comprises removing the dummy gate layer to form a gap between the dielectric layers, and forming the gate layer in the gap. The method for removing the dummy gate layer comprises wet etching. The etching liquid for wet etching may be phosphoric acid. After the dummy gate is removed, a gap is formed between the dielectric layers. The gap is filled with a gate layer material to form a gate layer in the gap. The material of the gate layer includes, but is not limited to, tungsten and cobalt. The method may further include forming a Channel Hole (CH) in the core region before the step of removing the dummy gate layer to form a gap between the dielectric layers and forming the gate layer in the gap. Methods of forming channel holes in the core region are well known in the art and will not be described further herein.
In the cross-sectional view of the semiconductor structure 400E illustrated in fig. 4E, each step structure is covered with an insulating material 440, and contact holes are formed through the insulating material 440 to the gate layer of each step structure, respectively. Thereafter, a contact structure 470 may be formed by filling the contact hole with a metal material to provide a conductive path for the gate layer of each step structure. The material of the contact structure 470 may be tungsten or cobalt. It can be seen that, since the gate layer is covered with the conductive layer, the thickness of the gate layer is thicker and is not easily etched through, so that the risk of etching through is greatly reduced.
Flow charts are used herein to illustrate operations performed by methods according to embodiments of the present application. It should be understood that the preceding operations are not necessarily performed in the exact order in which they are performed. Rather, various steps may be processed in reverse order or simultaneously. Meanwhile, other operations are added to or removed from these processes. For example, step 304 may be omitted and after providing the semiconductor structure, a conductive layer covering the top surface of the step and an insulating layer covering the conductive layer may be formed directly.
The semiconductor structure formed by the above embodiments may be processed by the following conventional steps to obtain a three-dimensional memory device. A three-dimensional memory according to an embodiment of the invention is described herein with reference to the semiconductor structure formed in this embodiment.
Fig. 5A-5D illustrate an exemplary process for planarizing an insulating layer, in accordance with an embodiment of the present invention.
In the cross-section of the semiconductor structure 500a shown in fig. 5A, the step region is filled with the insulating layer material 540, and the core region is also filled with the insulating layer material 540, so that the core region is entirely higher, forming a raised mesa protruding from the center.
In the cross-section of the semiconductor structure 500B shown in fig. 5B, a protective layer 550 may be covered on the surface of the insulating layer 540 before Chemical Mechanical Polishing (CMP) is performed. The material of the protection layer 550 may be silicon nitride. It is understood that the protective layer 550 may not be needed if the cmp process is well controlled enough. The stepped surface of the core region is also covered with a conductive layer 530, which may act as a barrier layer for the core region.
In the cross-section of the semiconductor structure 500C shown in fig. 5C, the insulating layer 540 of the core region is dry etched. As an example, the dry etching may be to cover the insulating layer with a hard mask layer, an anti-reflective coating layer and a photoresist in sequence, and then expose and open the hard mask layer, remove most of the insulating layer in the core region, and stay on the conductive layer 530 as a barrier layer in the core region. In some embodiments of the present invention, the antireflective coating material may be silicon oxynitride. In some embodiments of the present invention, the dry etching of the insulating layer 540 of the core region may be further followed by a wet cleaning to facilitate subsequent processes.
In the cross-section of the semiconductor structure 500D shown in fig. 5D, the mechanochemical planarization is performed such that the core region rests on the conductive layer 430 and the step region rests on the protective layer 450. Wet etching is then performed to remove the protective layer 450 on the surface of the step region and the conductive layer 430 on the surface of the core region.
To this end, a planarized surface of the insulating layer is formed, and the planarized surface stays above the dummy gate layer in the core region.
Fig. 6 illustrates a partial structure of a three-dimensional memory 600 according to an embodiment of the invention. As shown in fig. 6, three-dimensional memory 600 includes a core region and a staircase region. The step region has a step structure having a plurality of steps, each step (e.g., 611) includes at least one gate layer (e.g., 611a) and at least one dielectric layer (e.g., 611b) stacked alternately from top to bottom, an edge of at least one of the gate layers forms a top surface of the step, a conductive layer (e.g., 611c) is formed on the top surface of the step, and a contact (e.g., 620) is connected to the conductive layer.
In one embodiment of the invention, the projections of the conductive layers (e.g., 611c) of adjacent steps on the bottom surface of the stacked structure are end-to-end. In an embodiment of the invention, the conductive layer (e.g., 611c) and the gate layer (e.g., 611a) are made of the same material. In an embodiment of the present invention, the conductive layer (e.g., 611c) and the gate layer (e.g., 611a) are made of tungsten or cobalt. In one embodiment of the present invention, the thickness of the conductive layer (e.g., 611c) is 10-100 nm. In an embodiment of the present invention, the method of forming the conductive layer (e.g. 611c) on the top surface of the step is physical vapor deposition, metal sputtering or metal evaporation. In an embodiment of the present invention, the step structure further includes a dummy trench hole 640 penetrating through the step structure. In one embodiment of the present invention, a method of connecting contacts (e.g., 620) on a conductive layer (e.g., 611c) includes: an insulating layer 630 is formed over the step structure, and the insulating layer 630 is etched to form contact holes (not shown) exposing the gate layer (e.g., 611a) on the top surface of each step of the step structure. In an embodiment of the present invention, covering the insulating layer 630 on the step structure further includes planarizing the insulating layer 630. In an embodiment of the present invention, a peripheral circuit device (not shown) is further included below the step structure.
For further details of the present embodiment, reference is made to the above-mentioned manufacturing method, which is not further expanded herein.
This embodiment of the present invention provides a semiconductor structure including a core region and a terrace region, the terrace region having a terrace structure with a plurality of terraces, each terrace including at least one gate layer and at least one dielectric layer alternately stacked from top to bottom, an edge of at least one of the gate layers constituting a top surface of the terrace, a conductive layer formed on the top surface of the terrace, and a contact connected to the conductive layer. It can be seen that, since the gate layer is covered with the conductive layer, the thickness of the gate layer is thicker and is not easily etched through, so that the risk of etching through is greatly reduced.
Although the present invention has been described with reference to the present specific embodiments, it will be appreciated by those skilled in the art that the above embodiments are merely illustrative of the present invention, and various equivalent changes and substitutions may be made without departing from the spirit of the invention, and therefore, it is intended that all changes and modifications to the above embodiments within the spirit and scope of the present invention be covered by the appended claims.
Claims (10)
1. A method for manufacturing a three-dimensional memory comprises the following steps:
providing a semiconductor structure, wherein the semiconductor structure comprises a stacked structure, the stacked structure comprises a first material layer and a second material layer which are alternately stacked, and a step structure is formed at the edge, the step structure is provided with a plurality of layers of steps, the edge of at least part of the first material layer forms the top surface of the step, and the first material layer is a dummy gate layer or a gate layer;
forming a discontinuous conductive layer covering the top surface of each step;
forming an insulating layer covering the conductive layer after forming the conductive layer;
forming a contact structure through the insulating layer and connected to the conductive layer;
wherein before the step structure is formed at the edge of the stacked structure, the method further comprises: a virtual channel hole is formed on the stacked structure.
2. The method of claim 1, wherein prior to the forming of the insulating layer overlying the conductive layer, when the first material layer is a dummy gate layer and the second material layer is a dielectric layer, removing the dummy gate layer to form a gap between the dielectric layers and forming a gate layer in the gap.
3. The method of claim 1, wherein the conductive layer covering the top surface of the step is formed by physical vapor deposition, metal sputtering, or metal evaporation.
4. The method of claim 1, wherein projections of the conductive layers of adjacent steps on the bottom surface of the stacked structure are end-to-end.
5. The method of claim 1, wherein the conductive layer and the first material layer are both tungsten or cobalt.
6. The method according to any one of claims 1 to 5, wherein the thickness of the conductive layer is 10 to 100 nm.
7. The method of claim 1, wherein forming the conductive layer overlying the top surface of the step further comprises: and back-etching to remove at least one part of at least one second material layer, so that the side surface of at least one second material layer is recessed relative to the first material layer on the second material layer, thereby avoiding short circuit connection between the conductive layers.
8. The method of claim 1, wherein forming an insulating layer overlying the conductive layer comprises planarizing the insulating layer.
9. The method of claim 8, wherein planarizing the insulating layer is performed with a protective layer over the insulating layer.
10. The method of claim 1, wherein forming a contact structure through the insulating layer and connected to the conductive layer comprises: and etching the insulating layer on the stepped structure to form a plurality of contact holes exposing the first material layer on the top surface of each step of the stepped structure.
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| CN113130449B (en) * | 2019-12-30 | 2022-12-23 | 中芯国际集成电路制造(北京)有限公司 | Method for forming semiconductor structure |
| JP7297923B2 (en) * | 2020-05-27 | 2023-06-26 | 長江存儲科技有限責任公司 | Three-dimensional memory device and method |
| CN112038349A (en) * | 2020-09-08 | 2020-12-04 | 长江存储科技有限责任公司 | Method for forming channel hole of three-dimensional memory device and three-dimensional memory device |
| CN114188330A (en) * | 2020-09-28 | 2022-03-15 | 长江存储科技有限责任公司 | Three-dimensional memory |
| CN112331661B (en) * | 2020-11-03 | 2021-10-26 | 长江存储科技有限责任公司 | Semiconductor device and method for manufacturing the same |
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| CN104900648A (en) * | 2014-03-07 | 2015-09-09 | 三星电子株式会社 | Three-dimensional (3D) semiconductor devices |
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| CN104900648A (en) * | 2014-03-07 | 2015-09-09 | 三星电子株式会社 | Three-dimensional (3D) semiconductor devices |
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