CN109887915B - Flash memory device and method of manufacturing the same - Google Patents
Flash memory device and method of manufacturing the same Download PDFInfo
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- CN109887915B CN109887915B CN201910172992.9A CN201910172992A CN109887915B CN 109887915 B CN109887915 B CN 109887915B CN 201910172992 A CN201910172992 A CN 201910172992A CN 109887915 B CN109887915 B CN 109887915B
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Abstract
The invention provides a flash memory device and a manufacturing method thereof, wherein the manufacturing method of the flash memory device comprises the following steps: providing a substrate, and forming a plurality of shallow trench isolation structures on the substrate; etching back the side wall of the shallow trench isolation structure to form a first trench on the substrate between the adjacent shallow trench isolation structures, wherein the width of the top of the first trench is larger than that of the bottom of the first trench; forming a floating gate in the first trench; etching back the top of the shallow trench isolation structure to form a second trench exposing the side wall of the floating gate, wherein the width of the bottom of the second trench is larger than that of the top of the second trench; and forming a filling layer in the second groove, wherein a cavity is formed between the side wall of the filling layer and the side wall of the bottom of the floating gate. According to the technical scheme, the width of the floating gate is increased, and meanwhile, the crosstalk between the floating gates can be reduced, so that the reliability of the flash memory device is improved.
Description
Technical Field
The present invention relates to the field of integrated circuit manufacturing, and more particularly, to a flash memory device and a method for manufacturing the same.
Background
Flash memory (Flash) is an electrically reprogrammable read-only memory that has been the mainstay of the memory market due to its rapid growth. Compared with the traditional electrical reprogrammable read-only memory, the flash memory does not need to add extra external high voltage in the system in the engineering of electrical erasing and reprogramming, and has the characteristics of high memory cell density, high integration level and low cost. At present, flash memory is widely used in high and new technology industries such as mobile communication, data processing, intelligent terminals, embedded systems, and the like, such as personal computers and external devices thereof, automotive electronics, network switches, internet devices and instruments and meters, and also includes novel digital cameras, personal digital assistants, smart phones, tablet computers, and the like, due to its excellent performance. As these electronic products are accepted and used by more and more people, higher requirements are put on the functions, capacity, power consumption, volume, and the like of the flash memory. Especially, the flash memory with small volume and high performance has become the mainstream of the market nowadays, which requires the line width of the manufacturing process to be smaller and smaller, from 0.13 μm, 90nm, 65nm to 50nm, 40nm, 20nm and even smaller, and as the line width is reduced, the smaller and smaller size effect is more obvious.
For a flash memory having a Floating Gate (FG) structure, particularly, a floating gate is added to a Field Effect Transistor (FET), and information of one Bit (Bit), i.e., "0" or "1", is stored by a state of electrons in the floating gate. Such a floating gate is typically located between a Control Gate (CG) and a Tunnel oxide (Tunnel oxide), wherein the control gate and the floating gate are separated by an intergate dielectric layer. To ensure that the floating gate can store enough electrons and to ensure the erase and write speed of the flash memory device, the size of the floating gate cannot be made too small.
A method of manufacturing a flash memory device having a floating gate structure generally includes the steps of:
first, a sacrificial oxide layer 111 and a sacrificial nitride layer 112 are sequentially formed on a substrate 10, as shown in fig. 1 a;
then, the sacrificial nitride layer 112, the sacrificial oxide layer 111 and the substrate 10 are sequentially etched to form a first trench 121, and the first trench 121 is filled to form a shallow trench isolation structure 122(STI), referring to fig. 1b and 1 c;
then, removing the sacrificial nitride layer 112 and the sacrificial oxide layer 111, performing back etching on the sidewall of the shallow trench isolation structure 122 to form a second trench 131 on the substrate 10, and then performing ion implantation into the substrate 10 to form a well region 132, as shown in fig. 1 d;
then, a tunnel oxide layer 141 and a floating gate 142 are sequentially formed in the second trench 131 from bottom to top, as shown in fig. 1 e;
then, the shallow trench isolation structure 122 is etched back, so that the top surface of the shallow trench isolation structure 122 is lower than the top surface of the floating gate 142 and higher than the top surface of the tunnel oxide layer 141, as shown in fig. 1 f;
then, an intergate dielectric layer 151 and a control gate 152 are sequentially formed on top of the floating gate 142, see fig. 1 g.
It can be seen from the above manufacturing steps of the flash memory device with the floating gate structure that, in order to increase the size of the floating gate, it may be considered to increase the thickness or width of the floating gate, but if the thickness of the floating gate is too large, an abnormal process (for example, a void may be generated) may occur in the subsequent process of filling the dielectric layer, and then a large leakage occurs between Bit and Bit, and therefore, only the lateral width of the floating gate may be selectively increased. However, if the lateral width of the floating gates is increased, the lateral distance between adjacent floating gates is decreased, which results in an increase in the mutual coupling effect (i.e., crosstalk between adjacent floating gates) between adjacent bits, thereby affecting the programming and erasing states of the flash memory device, and reducing the reliability of the flash memory device.
Therefore, how to improve the manufacturing process of the existing flash memory device with the floating gate structure, so that the width of the floating gate is increased, and the crosstalk between the floating gates can be reduced, thereby improving the reliability of the flash memory device is a problem to be solved at present.
Disclosure of Invention
The invention aims to provide a flash memory device and a manufacturing method thereof, which can reduce crosstalk between floating gates while increasing the width of the floating gates, thereby improving the reliability of the flash memory device.
To achieve the above object, the present invention provides a method of manufacturing a flash memory device, comprising:
providing a substrate, and forming a plurality of shallow trench isolation structures on the substrate, wherein the top surfaces of the shallow trench isolation structures are higher than the top surface of the substrate;
etching back the side wall of the shallow trench isolation structure to form a first trench on the substrate between the adjacent shallow trench isolation structures, wherein the width of the top of the first trench is larger than that of the bottom of the first trench;
forming a floating gate in the first trench, wherein the width of the top of the floating gate is larger than that of the bottom of the floating gate;
etching back the top of the shallow trench isolation structure to form a second trench exposing the side wall of the floating gate, wherein the width of the bottom of the second trench is larger than that of the top of the second trench; and the number of the first and second groups,
and forming a filling layer in the second groove, wherein a cavity is formed between the side wall of the filling layer and the side wall of the bottom of the floating gate.
Optionally, the step of forming the shallow trench isolation structure on the substrate includes:
forming a sacrificial layer on the substrate;
sequentially etching the sacrificial layer and the substrate to form a third groove;
filling an isolation oxide layer in the third trench, wherein the isolation oxide layer fills the third trench and buries the sacrificial layer in the third trench;
grinding the isolation oxide layer by adopting a chemical mechanical grinding process, and stopping on the top surface of the sacrificial layer; and the number of the first and second groups,
and removing the sacrificial layer.
Optionally, the step of forming the sacrificial layer includes: and sequentially forming a sacrificial oxide layer and a sacrificial nitride layer on the substrate.
Optionally, the side wall of the shallow trench isolation structure is etched back for multiple times, so that the side wall of the first trench includes at least one step.
Optionally, before forming the floating gate in the first trench, a tunnel oxide layer is formed at the bottom of the first trench.
Optionally, after the first trench is formed and before the tunnel oxide layer is formed, ion implantation is performed on the substrate to form a well region in the substrate.
Optionally, the step of forming the filling layer in the second trench includes:
depositing a filling layer in the second trench, wherein a cavity is formed between the side wall of the filling layer and the side wall of the bottom of the floating gate close to the top surface of the shallow trench isolation structure, and the floating gate is buried in the filling layer;
grinding the filling layer by adopting a chemical mechanical grinding process and stopping on the top surface of the floating gate; and the number of the first and second groups,
removing a portion of the thickness of the fill layer such that a top surface of the fill layer is below a top surface of the floating gate and above the void.
Optionally, the material of the filling layer includes silicon oxide, silicon nitride, or silicon oxide-silicon nitride-silicon oxide.
Optionally, after the filling layer is formed in the second trench, an inter-gate dielectric layer and a control gate are sequentially formed on the floating gate.
The present invention also provides a flash memory device, comprising:
a substrate with shallow trench isolation structure;
the floating gate is positioned on the substrate between the adjacent shallow trench isolation structures, and the width of the top of the floating gate is larger than that of the bottom of the floating gate; and the number of the first and second groups,
and a cavity is formed between the side wall of the filling layer and the side wall of the bottom of the floating gate.
Optionally, the flash memory device further includes a tunneling oxide layer located between the floating gate and the substrate.
Optionally, the substrate includes a well region therein.
Optionally, the void is located between a sidewall of the filling layer and a sidewall of the bottom of the floating gate near the top surface of the shallow trench isolation structure, and the top surface of the filling layer is lower than the top surface of the floating gate and higher than the void.
Optionally, the material of the filling layer includes silicon oxide, silicon nitride, or silicon oxide-silicon nitride-silicon oxide.
Optionally, the flash memory device further includes an inter-gate dielectric layer and a control gate on the floating gate.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
1. according to the manufacturing method of the flash memory device, the side wall of the shallow trench isolation structure is etched back to form the first trench with the top width larger than the bottom width, the floating gate is formed in the first trench, the top of the shallow trench isolation structure is etched back to form the second trench exposing the side wall of the floating gate, the filling layer is formed in the second trench, and a cavity is formed between the side wall of the filling layer and the side wall of the bottom of the floating gate, so that the width of the floating gate is increased, the crosstalk between the floating gates can be reduced, and the reliability of the flash memory device is improved.
2. According to the flash memory device, the cavity is formed between the filling layer on the shallow trench isolation structure between the adjacent floating gates and the side wall of the bottom of the floating gate, so that the width of the floating gate is increased, the crosstalk between the floating gates can be reduced, and the reliability of the flash memory device is improved.
Drawings
FIGS. 1a to 1g are schematic views of a conventional flash memory device in a method of manufacturing the flash memory device;
fig. 2 is a flowchart of a method of manufacturing a flash memory device according to an embodiment of the present invention;
fig. 3a to 3j are device diagrams in the method of manufacturing the flash memory device shown in fig. 2.
Wherein the reference numerals of figures 1a to 3j are as follows:
10-a substrate; 111-sacrificial oxide layer; 112-sacrificial nitride layer; 121-a first trench; 122-shallow trench isolation structures; 131-a second trench; 132-a well region; 141-tunneling oxide layer; 142-a floating gate; 151-inter-gate dielectric layer; 152-a control gate; 20-a substrate; 21-a sacrificial layer; 211-sacrificial oxide layer; 212-sacrificial nitride layer; 22-shallow trench isolation structures; 221-a third trench; 222-isolation oxide layer; 231 — a first trench; 2311-first part; 2312-second part; 232-well region; 241-tunneling oxide layer; 242-floating gate; 243-a second groove; 244-a void; 25-a filler layer; 261-an inter-gate dielectric layer; 262-control gate.
Detailed Description
To make the objects, advantages and features of the present invention more apparent, a flash memory device and a method for manufacturing the same according to the present invention will be described in detail with reference to fig. 1a to 3 j. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
An embodiment of the present invention provides a method for manufacturing a flash memory device, and referring to fig. 2, fig. 2 is a flowchart of a method for manufacturing a flash memory device according to an embodiment of the present invention, where the method for manufacturing a flash memory device includes:
step S1, providing a substrate, and forming a plurality of shallow trench isolation structures on the substrate, wherein the top surfaces of the shallow trench isolation structures are higher than the top surface of the substrate;
step S2, etching back the side wall of the shallow trench isolation structure to form a first trench on the substrate between the adjacent shallow trench isolation structures, wherein the width of the top of the first trench is larger than that of the bottom of the first trench;
step S3, forming a floating gate in the first trench, wherein the width of the top of the floating gate is greater than that of the bottom of the floating gate;
step S4, etching back the top of the shallow trench isolation structure to form a second trench exposing the side wall of the floating gate, wherein the width of the bottom of the second trench is larger than that of the top of the second trench;
step S5, forming a filling layer in the second trench, and forming a cavity between a sidewall of the filling layer and a sidewall of the bottom of the floating gate.
The method for manufacturing the flash memory device according to the present embodiment will be described in more detail with reference to fig. 3a to 3j, and fig. 3a to 3j are device diagrams in the method for manufacturing the flash memory device shown in fig. 2.
First, referring to fig. 3a to 3d, according to step S1, a substrate 20 is provided, and a plurality of shallow trench isolation structures 22 are formed on the substrate 20, wherein top surfaces of the shallow trench isolation structures 22 are higher than top surfaces of the substrate 20.
Wherein the step of forming the shallow trench isolation structure 22 on the substrate 20 comprises: first, a sacrificial layer 21 is formed on the substrate 20, as shown in fig. 3 a; then, sequentially etching the sacrificial layer 21 and the substrate 20 to form a third trench 221, as shown in fig. 3 b; then, filling an isolation oxide layer 222 in the third trench 221, wherein the isolation oxide layer 222 fills the third trench 221 and buries the sacrificial layer 21 therein; then, the isolation oxide layer 222 is polished by a chemical mechanical polishing process and stops on the top surface of the sacrificial layer 21, as shown in fig. 3 c; then, the sacrificial layer 21 is removed so that the top surface of the shallow trench isolation structure 22 is formed higher than the top surface of the substrate 20, as shown in fig. 3 d. As can be seen from fig. 3a, the step of forming the sacrificial layer 21 may include: a sacrificial oxide layer 211 and a sacrificial nitride layer 212 are sequentially formed on the substrate 20. The isolation oxide layer 222 and the sacrificial oxide layer 211 may be made of silicon oxide, and the sacrificial nitride layer 212 may be made of silicon nitride. The method for forming the sacrificial layer 21 and filling the isolation oxide layer 222 may include chemical vapor deposition, physical vapor deposition, and the like, and the method for etching the sacrificial layer 21 and the substrate 20 and removing the sacrificial layer 21 may be dry etching or wet etching.
Then, referring to fig. 3e, in step S2, the sidewalls of the shallow trench isolation structures 22 are etched back to form a first trench 231 on the substrate 20 between adjacent shallow trench isolation structures 22, wherein the width of the top of the first trench 231 is greater than the width of the bottom thereof. In this embodiment, the sidewall of the shallow trench isolation structure 22 may be etched back for multiple times, so that the sidewall of the first trench 231 includes at least one step, and further the width of the top of the first trench 231 is greater than the width of the bottom of the first trench. As can be seen from fig. 3e, the sidewall of the first trench 231 includes a step, so that the first trench 231 is composed of a first portion 2311 and a second portion 2312, the width of the cross section of the first portion 2311 of the first trench 231, which is perpendicular to the surface of the substrate 20, is greater than the width of the cross section of the second portion 2312, which is perpendicular to the surface of the substrate 20, a mask plate with a relatively smaller opening pattern size may be first used for exposure to obtain a mask layer with a smaller opening size, then the sidewall of the shallow trench isolation structure 22 is etched back by using the mask layer as a mask, and then another mask plate with a relatively larger opening pattern size is used for exposure to obtain a mask layer with a larger opening size, and then the sidewall of the shallow trench isolation structure 22 is etched back by using the mask layer as a mask to obtain the first portion 2311 and the second portion 2312 of the first trench 231. When the sidewall of the first trench 231 includes two steps, the sidewall of the shallow trench isolation structure 22 may be etched back three times, and the detailed process is not repeated. In other embodiments, the sidewall of the first trench 231 may not be step-shaped, and the width of the first trench 231 may gradually increase from bottom to top (that is, the longitudinal cross-sectional shape of the first trench 231 is an inverted trapezoid), that is, the sidewall of the first trench 231 is inclined toward the shallow trench isolation structure 22, so that the width of the top of the first trench 231 is greater than the width of the bottom thereof.
Then, referring to fig. 3f, a floating gate 242 is formed in the first trench 231 according to step S3, wherein the width of the top of the floating gate 242 is greater than that of the bottom thereof. In this embodiment, when the sidewall of the first trench 231 proposed in step S2 includes a step, as shown in fig. 3f, the floating gate 242 has a T-shaped longitudinal cross section. In other embodiments, namely, the width of the first trench 231 provided in step S2 gradually increases from bottom to top, the longitudinal section of the floating gate 242 has an inverted trapezoid structure. Before forming the floating gate 242 in the first trench 231, a tunnel oxide layer 241 is formed at the bottom of the first trench 231. After the first trench 231 is formed and before the tunnel oxide layer 241 is formed, ion implantation may be performed on the substrate 20 to form a well region 232 in the substrate 20. The well region 232 may contain P-type or N-type ions. The method for forming the tunnel oxide layer 241 and the floating gate 242 may include chemical vapor deposition, physical vapor deposition, and the like, the tunnel oxide layer 241 may be made of silicon oxide, and the floating gate 242 may be made of polysilicon.
Then, referring to fig. 3g, in step S4, the top of the shallow trench isolation structure 22 is etched back to form a second trench 243 exposing the sidewalls of the floating gate 242, and the width of the bottom of the second trench 243 is greater than that of the top of the second trench. After etching back the top of the shallow trench isolation structure 22, the bottom wall of the second trench 243 may be flush with the top surface of the tunneling oxide layer 241; alternatively, the bottom wall of the second trench 243 is slightly lower than the top surface of the tunneling oxide layer 241, for example, flush with the top surface of the substrate 20; still alternatively, the bottom wall of the second trench 243 is slightly higher than the top surface of the tunnel oxide layer 241, but the height of the bottom wall of the second trench 243 does not affect the formation of the void 244 between the sidewall of the subsequently formed filling layer 25 and the sidewall of the bottom of the floating gate 242. The method for forming the second trench 243 may include wet etching, dry etching, or a combination of wet etching and dry etching.
Finally, referring to fig. 3h to 3j, in step S5, a filling layer 25 is formed in the second trench 243, and a void 244 is formed between a sidewall of the filling layer 25 and a sidewall of the bottom of the floating gate 242. The step of forming the filling layer 25 in the second trench 243 includes: depositing a filling layer 25 in the second trench 243, forming a void 244 between a sidewall of the filling layer 25 and a sidewall of the bottom of the floating gate 242 near the top surface of the shallow trench isolation structure 22, and burying the floating gate 242 therein by the filling layer 25; then, the filling layer 25 is polished by a chemical mechanical polishing process and stops on the top surface of the floating gate 242, as shown in fig. 3 h; then, a portion of the thickness of the fill layer 25 is removed so that the top surface of the fill layer 25 is below the top surface of the floating gates 242 and above the voids 244, as shown in FIG. 3 i. The top surface of the fill layer 25 is lower than the top surface of the floating gate 242 so that the coupling ratio between the floating gate 242 and a later formed control gate 262 is increased, thereby improving the programming and erase rates of the flash memory device. The shape of the longitudinal cross section of the void 244 may be a single square, a combination of squares, or a triangle, and the like, and the shape of the longitudinal cross section of the void 244 is mainly determined by the number of times the sidewalls of the shallow trench isolation structure 22 are etched back and the process parameters in step S2. For example, when the shape of the longitudinal cross section of the void 244 is a single square, the sidewall of the shallow trench isolation structure 22 is etched back twice in the step S2; when the shape of the longitudinal section of the void 244 is a plurality of square combinations, the sidewall of the shallow trench isolation structure 22 is etched back at least three times in the step S2. Of course, the shape of the longitudinal section of the void 244 may also be affected by the process of forming the filling layer 25 in the second trench 243.
In addition, in the process of depositing and forming the filling layer 25 in the second trench 243, by controlling process parameters such as the deposition speed of the deposition process, plasma defects on the filling layer 25 are reduced, so that the surface of the formed filling layer 25 is smoother and has uniform interface charges, thereby improving the uniformity and reliability of the flash memory device. Moreover, the flowability of the material of the filling layer 25 is poor, so that the void 244 is more easily formed between the sidewall of the filling layer 25 and the sidewall of the bottom of the floating gate 242; meanwhile, the filling layer 25 has a better interface state due to poor fluidity of the material of the filling layer 25, so that the uniformity and reliability of the flash memory device are improved. The material of the filling layer 25 may include silicon oxide, silicon nitride, or silicon oxide-silicon nitride-silicon oxide (ONO). In addition, due to the existence of the void 244 between the sidewall of the filling layer 25 and the sidewall of the bottom of the floating gate 242, the lateral distance between adjacent floating gates 242 can be increased while the width of the floating gates 242 is increased to meet the process requirement, so as to reduce the crosstalk between adjacent floating gates 242; moreover, the voids 244 are filled with air, and the dielectric constant of air is low, so that the crosstalk between adjacent floating gates 242 is further reduced, and the reliability of the flash memory device is further improved.
In addition, as can be seen from fig. 3j, after the filling layer 25 is formed in the second trench 243, an inter-gate dielectric layer 261 and a control gate 262 are sequentially formed on the floating gate 242. The materials of the inter-gate dielectric layer 261 and the control gate 262 may be sequentially deposited on the floating gate 242 and the filling layer 25, and then the materials on the filling layer 25 are removed by etching, so as to form the inter-gate dielectric layer 261 and the control gate 262 on the floating gate 242. The material of the inter-gate dielectric layer 261 may include silicon oxide, silicon nitride, or silicon oxide-silicon nitride-silicon oxide (ONO), and the material of the control gate 262 may be polysilicon.
In addition, the method for manufacturing the flash memory device in the steps S1 to S5 is particularly suitable for manufacturing the flash memory device with the node of 55nm or less, and the manufacturing process is simple and easy to implement.
In summary, the method for manufacturing a flash memory device provided by the present invention includes: providing a substrate, and forming a plurality of shallow trench isolation structures on the substrate, wherein the top surfaces of the shallow trench isolation structures are higher than the top surface of the substrate; etching back the side wall of the shallow trench isolation structure to form a first trench on the substrate between the adjacent shallow trench isolation structures, wherein the width of the top of the first trench is larger than that of the bottom of the first trench; forming a floating gate in the first trench, wherein the width of the top of the floating gate is larger than that of the bottom of the floating gate; etching back the top of the shallow trench isolation structure to form a second trench exposing the side wall of the floating gate, wherein the width of the bottom of the second trench is larger than that of the top of the second trench; and forming a filling layer in the second groove, wherein a cavity is formed between the side wall of the filling layer and the side wall of the bottom of the floating gate. By the technical scheme of the invention, the width of the floating gate is increased, and the crosstalk between the floating gates can be reduced, so that the reliability of the flash memory device is improved.
An embodiment of the present invention provides a flash memory device, as can be seen in fig. 3j, the semiconductor device includes a substrate 20, a floating gate 242, and a filling layer 25, the substrate 20 having a shallow trench isolation structure 22; the floating gates 242 are located on the substrate 20 between adjacent shallow trench isolation structures 22, and the width of the top of the floating gates 242 is larger than that of the bottom thereof; and the filling layer 25 is located on the shallow trench isolation structure 22 between the adjacent floating gates 242, and a void 244 is formed between the sidewall of the filling layer 25 and the sidewall of the bottom of the floating gate 242.
The flash memory device provided in the present embodiment is described in detail below with reference to fig. 3 j:
the substrate 20 has a shallow trench isolation structure 22, a top surface of the shallow trench isolation structure 22 being flush with a top surface of the substrate 20; alternatively, the top surface of the shallow trench isolation structure 22 is higher than the top surface of the substrate 20, but the height of the top surface of the shallow trench isolation structure 22 does not affect the formation of the void 244 between the sidewall of the filling layer 25 and the sidewall of the bottom of the floating gate 242, for example, the top surface of the shallow trench isolation structure 22 may be flush with the top surface of the tunnel oxide 241 formed later. The substrate 20 may include a well region 232 therein, and the well region 232 may include P-type or N-type ions therein.
The floating gates 242 are located on the substrate 20 between adjacent shallow trench isolation structures 22, and the width of the top of the floating gates 242 is larger than that of the bottom thereof. A tunnel oxide layer 241 may also be included between the floating gate 242 and the substrate 20. The floating gate 242 may have a T-shaped cross-section such that a void 244 is formed below both lateral ends of the T-shaped structure; alternatively, the floating gates 242 have an inverted trapezoidal structure in longitudinal section, so that voids 244 are formed between the sidewalls of the bottom portions of the floating gates 242 and the sidewalls of the filling layer 25. The shape of the longitudinal section of the hollow 244 may be a single square, a combination of squares, or a triangle, etc. The tunneling oxide layer 241 may be made of silicon oxide, and the floating gate 242 may be made of polysilicon.
The filling layer 25 is located on the shallow trench isolation structure 22 between adjacent floating gates 242, and the void 244 is located between the sidewall of the filling layer 25 and the sidewall of the bottom of the floating gate 242 near the top surface of the shallow trench isolation structure 22. The top surface of the fill layer 25 is below the top surface of the floating gates 242 and above the voids 244. The top surface of the fill layer 25 is lower than the top surface of the floating gate 242 so that the coupling ratio between the floating gate 242 and a later formed control gate 262 is increased, thereby improving the programming and erase rates of the flash memory device. The material of the filling layer 25 may include silicon oxide, silicon nitride, or silicon oxide-silicon nitride-silicon oxide (ONO). In addition, as the plasma defects on the filling layer 25 are reduced, the surface of the formed filling layer 25 is smoother and has uniform interface charges, and further, the uniformity and the reliability of the flash memory device are improved. Moreover, the flowability of the material of the filling layer 25 is poor, so that the void 244 is more easily formed between the sidewall of the filling layer 25 and the sidewall of the bottom of the floating gate 242; meanwhile, the filling layer 25 has a better interface state due to poor fluidity of the material of the filling layer 25, so that the uniformity and reliability of the flash memory device are improved. In addition, due to the existence of the void 244 between the sidewall of the filling layer 25 and the sidewall of the bottom of the floating gate 242, the lateral distance between adjacent floating gates 242 can be increased while the width of the floating gates 242 is increased to meet the process requirement, so as to reduce the crosstalk between adjacent floating gates 242; moreover, the voids 244 are filled with air, and the dielectric constant of air is low, so that the crosstalk between adjacent floating gates 242 is further reduced, and the reliability of the flash memory device is further improved.
In addition, an inter-gate dielectric layer 261 and a control gate 262 are further included on the floating gate 242. The material of the inter-gate dielectric layer 261 may include silicon oxide, silicon nitride, or silicon oxide-silicon nitride-silicon oxide (ONO), and the material of the control gate 262 may be polysilicon.
In summary, the flash memory device provided by the present invention includes: a substrate with shallow trench isolation structure; the floating gate is positioned on the substrate between the adjacent shallow trench isolation structures, and the width of the top of the floating gate is larger than that of the bottom of the floating gate; and the filling layer is positioned on the shallow trench isolation structure between the adjacent floating gates, and a cavity is formed between the side wall of the filling layer and the side wall of the bottom of the floating gate. The flash memory device provided by the invention can reduce the crosstalk between the floating gates while increasing the width of the floating gates, thereby improving the reliability of the flash memory device.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (15)
1. A method of manufacturing a flash memory device, comprising:
providing a substrate, and forming a plurality of shallow trench isolation structures on the substrate, wherein the top surfaces of the shallow trench isolation structures are higher than the top surface of the substrate;
etching back the side wall of the shallow trench isolation structure to form a first trench on the substrate between the adjacent shallow trench isolation structures, wherein the width of the top of the first trench is larger than that of the bottom of the first trench;
forming a floating gate in the first trench, wherein the width of the top of the floating gate is larger than that of the bottom of the floating gate;
etching back the top of the shallow trench isolation structure to form a second trench exposing the side wall of the floating gate, wherein the width of the bottom of the second trench is larger than that of the top of the second trench; and the number of the first and second groups,
and forming a filling layer in the second groove, wherein a cavity is formed between the side wall of the filling layer and the side wall of the bottom of the floating gate.
2. The method of manufacturing a flash memory device of claim 1, wherein the step of forming a shallow trench isolation structure on the substrate comprises:
forming a sacrificial layer on the substrate;
sequentially etching the sacrificial layer and the substrate to form a third groove;
filling an isolation oxide layer in the third trench, wherein the isolation oxide layer fills the third trench and buries the sacrificial layer in the third trench;
grinding the isolation oxide layer by adopting a chemical mechanical grinding process, and stopping on the top surface of the sacrificial layer; and the number of the first and second groups,
and removing the sacrificial layer.
3. The method of manufacturing a flash memory device according to claim 2, wherein the step of forming the sacrificial layer comprises: and sequentially forming a sacrificial oxide layer and a sacrificial nitride layer on the substrate.
4. The method of manufacturing a flash memory device of claim 1, wherein the sidewalls of the shallow trench isolation structure are etched back a plurality of times so that the sidewalls of the first trench comprise at least one step.
5. The method of any of claims 1-4, wherein a tunnel oxide layer is formed at a bottom of the first trench prior to forming the floating gate in the first trench.
6. The method of manufacturing a flash memory device according to claim 5, wherein after forming the first trench and before forming the tunnel oxide layer, the substrate is ion-implanted to form a well region in the substrate.
7. The method of manufacturing a flash memory device according to any one of claims 1 to 4, wherein the step of forming the filling layer in the second trench comprises:
depositing a filling layer in the second trench, wherein a cavity is formed between the side wall of the filling layer and the side wall of the bottom of the floating gate close to the top surface of the shallow trench isolation structure, and the floating gate is buried in the filling layer;
grinding the filling layer by adopting a chemical mechanical grinding process and stopping on the top surface of the floating gate; and the number of the first and second groups,
removing a portion of the thickness of the fill layer such that a top surface of the fill layer is below a top surface of the floating gate and above the void.
8. The method of manufacturing a flash memory device according to any one of claims 1 to 4, wherein a material of the filling layer includes silicon oxide, silicon nitride, or silicon oxide-silicon nitride-silicon oxide.
9. The method of manufacturing a flash memory device according to any one of claims 1 to 4, wherein after the filling layer is formed in the second trench, an intergate dielectric layer and a control gate are sequentially formed on the floating gate.
10. A flash memory device, comprising:
a substrate with shallow trench isolation structure;
the floating gate is positioned on the substrate between the adjacent shallow trench isolation structures, and the width of the top of the floating gate is larger than that of the bottom of the floating gate; and the number of the first and second groups,
and a filling layer is positioned on the shallow trench isolation structure between the adjacent floating gates, and a cavity is formed between the side wall of the filling layer and the side wall of the bottom of the floating gate.
11. The flash memory device of claim 10, further comprising a tunnel oxide layer between the floating gate and the substrate.
12. The flash memory device of claim 10 wherein said substrate includes a well region therein.
13. The flash memory device of any one of claims 10 to 12, wherein the void is located between a sidewall of the fill layer and a sidewall of the bottom of the floating gate proximate to a top surface of the shallow trench isolation structure, the top surface of the fill layer being lower than the top surface of the floating gate and higher than the void.
14. The flash memory device according to any of claims 10 to 12, wherein the material of the filling layer comprises silicon oxide, silicon nitride or silicon oxide-silicon nitride-silicon oxide.
15. The flash memory device of any of claims 10 to 12, further comprising an intergate dielectric layer and a control gate over the floating gate.
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