CN115472623A

CN115472623A - Semiconductor device, manufacturing method thereof, memory and storage system

Info

Publication number: CN115472623A
Application number: CN202211124454.0A
Authority: CN
Inventors: 吴林春; 李思晢; 孔翠翠; 张坤
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2022-09-15
Filing date: 2022-09-15
Publication date: 2022-12-13

Abstract

The invention discloses a semiconductor device and a preparation method thereof, a memory and a storage system, which comprise a substrate with a transverse surface, wherein a stack layer is formed on one side of the substrate in the longitudinal direction opposite to the transverse surface, the stack layer comprises a first stack structure formed by alternately stacking sacrificial layers and interlayer insulating layers and a bottom stack structure formed by alternately stacking stop layers and spacing layers, the stack layer comprises a core region and a step region, the stop layer comprises a first stop layer and a second stop layer, the second stop layer is positioned on the first stop layer, a longitudinally extending channel hole is formed in the core region of the stack layer, and the first stop layer and the second stop layer are subjected to oxidation treatment in the side wall of the channel hole, wherein the oxidation rate of the first stop layer subjected to oxidation treatment is greater than that of the second stop layer.

Description

Semiconductor device, manufacturing method thereof, memory and storage system

Technical Field

The invention relates to the technical field of electronic devices, in particular to a semiconductor device, a manufacturing method of the semiconductor device, a memory and a storage system.

Background

3D NAND (3D NAND FLASH MEMORY) is an emerging type of FLASH MEMORY that addresses the limitations imposed by 2D or planar NAND FLASH memories by stacking MEMORY grains together.

In 3D NAND, a mode of vertically stacking a plurality of layers of data storage units is adopted to realize a stacked memory structure. As the number of stacked layers increases, the control of etching the trench hole profile becomes more and more difficult.

In the prior art, the etching control precision of the channel hole profile is improved mainly through an etching process. However, due to the low selection of SiN (silicon nitride), OX (oxide) and Poly (polysilicon) in the etching process, the uniformity of the gouges formed on the substrate of the memory structure is poor, thereby affecting the related preparation process of the subsequent backside extraction structure.

Disclosure of Invention

The invention aims to provide a semiconductor device, a manufacturing method thereof, a memory and a storage system, and aims to solve the problem that the uniformity of a punched hole formed on a substrate is poor due to an etching process.

In a first aspect, to achieve the above object, the present disclosure provides a method for manufacturing a semiconductor device, including:

providing a substrate having a lateral surface;

forming a stack layer on one side of the substrate in a longitudinal direction opposite to the lateral surface, the stack layer including a first stack structure alternately stacked by a sacrificial layer and an interlayer insulating layer, and a bottom stack structure alternately stacked by a stop layer and a spacer layer, the stack layer including a core region and a step region, the stop layer including a first stop layer and a second stop layer, the second stop layer being located on the first stop layer;

forming a longitudinally extending channel hole in the core region of the stacked layers;

and performing oxidation treatment on the first stop layer and the second stop layer in the side wall of the channel hole, wherein the oxidation rate of the oxidation treatment on the first stop layer is greater than that of the oxidation treatment on the second stop layer.

In some embodiments, the step of oxidizing the first stop layer and the second stop layer within the sidewalls of the channel hole further comprises:

and respectively forming a first protruding structure and a second protruding structure in the side wall of the channel hole at a first position and a second position corresponding to the first stop layer and the second stop layer, wherein the length of the second protruding structure in the transverse direction is smaller than that of the first protruding structure in the transverse direction.

In some embodiments, the step of forming stacked layers on the substrate side in a longitudinal direction opposite the lateral surface further comprises:

carrying out phosphorus doping on the first stop layer;

and carrying out carbon doping on the second stop layer.

and performing surface treatment on the second stop layer by adopting ammonia gas.

In some embodiments, the first protruding structure forms a gap in the longitudinal direction at a protruding portion within the channel hole, and the method for manufacturing a semiconductor device further includes:

forming a storage function layer in the channel hole, wherein the storage function layer is attached to the whole inner wall of the channel hole and completely fills the gap;

and sequentially forming a channel layer and an insulating layer in the channel hole above the first protruding structure.

In some embodiments, the first protruding structure does not have a gap formed in the longitudinal direction at the protruding portion in the trench hole, and the method for manufacturing a semiconductor device further includes:

and sequentially forming a storage function layer, a channel layer and an insulating layer in the channel hole above the first bulge structure.

In some embodiments, the method for manufacturing a semiconductor device further includes:

forming a dummy channel hole longitudinally penetrating the stacked layers in the step area;

oxidizing the first stop layer in the side wall of the pseudo channel hole, and forming a third bump structure on the side wall of the bottom of the pseudo channel hole and the part corresponding to the first stop layer;

and filling the dummy channel hole with the third bump structure to form a dummy channel structure.

In some embodiments, the protruding portion of the third protruding structure within the dummy channel hole is not formed with a slit in the longitudinal direction.

forming a grid line isolation structure longitudinally penetrating through the stacked layers;

forming a contact structure longitudinally through the bottom stack structure at the stepped region;

removing the substrate and the bottom stack structure between the substrate and the second stop layer and exposing the bottom surface of the channel layer;

and forming a source region on the bottom surface of the channel layer and the second stop layer.

In some embodiments, after the step of forming a source region on the bottom surface of the channel layer and the second stop layer, the method of manufacturing a semiconductor device further includes:

and forming an insulation structure on the bottom surface of the source region, and forming a conductive structure which is respectively connected with the contact structure and the source region on the bottom surface of the insulation structure.

In some embodiments, the step of forming a contact structure in the stepped region that extends longitudinally through the bottom stack structure comprises:

forming a dielectric layer covering the stacked layers in the step area;

forming a contact hole which longitudinally penetrates through the dielectric layer and extends to the second stop layer in the step area;

and depositing a conductive material in the contact hole to form a contact structure.

In a second aspect, to solve the same technical problem, the present disclosure provides a semiconductor device comprising:

a stack structure including a first stack structure in which gate layers and interlayer insulating layers are alternately stacked in a longitudinal direction and a bottom stack structure having a stopper layer, the stack structure including a core region and a terrace region in a lateral direction, the stack structure in the core region being formed with a longitudinally extending channel hole;

a source region located at the bottom of the stack structure and in contact with the stop layer of the bottom stack structure; and

a channel structure located in the channel hole and including a memory functional layer, a channel layer, and an insulating layer formed along the channel hole inner wall;

and a raised structure is formed in the side wall of the channel hole corresponding to the stop layer, so that the inner diameter of the channel structure at the position is smaller than that of other positions, and the channel layer has a bottom surface extending into the source region.

In some embodiments, the semiconductor device further comprises:

the conductive structure is positioned at the bottom of the source region and is electrically connected with the source region;

and the insulation structure is positioned between the source region and the conductive structure and is provided with a through hole for connecting the conductive structure with the source region.

In some embodiments, the semiconductor device further comprises:

the semiconductor device further includes:

and the grid line isolation structure longitudinally penetrates through the stack structure of the core region and extends into the source region.

In some embodiments, the semiconductor device further comprises:

the dielectric layer covers the stack structure of the step area; and

and the contact structure longitudinally penetrates through the dielectric layer, extends to a position corresponding to the transverse surface of the stop layer and is connected with the conductive structure.

In some embodiments, the semiconductor device further comprises:

and the pseudo channel structure longitudinally penetrates through the stack structure of the step region and is provided with a pseudo channel structure bottom surface which is in contact with the source region at a position corresponding to the transverse surface of the stop layer.

In some embodiments, the bottom stack structure corresponds to the step region of the contact structure in the longitudinal direction, and further includes a first stop layer, and the stop layer serves as a second stop layer, and an oxidation rate of the first stop layer is greater than that of the second stop layer.

In some embodiments, the first and second stop layers and the source region longitudinally corresponding to the contact structure are provided with a through silicon via, and the contact structure is connected with the conductive structure through the through silicon via.

In a third aspect, the present disclosure provides a memory comprising:

a semiconductor device manufactured by the method for manufacturing a semiconductor device according to any one of the above embodiments, and a peripheral circuit electrically connected to the semiconductor device.

In a fourth aspect, the present disclosure provides a memory system comprising:

the memory of the third aspect, and a controller electrically connected to the memory for controlling the memory to store data.

The utility model provides a semiconductor device and preparation method, memory and storage system thereof, through carrying out oxidation treatment to first stop layer and second stop layer in the lateral wall of trench hole, wherein, the oxidation rate of carrying out oxidation treatment to first stop layer is greater than the oxidation rate of carrying out oxidation treatment to second stop layer, thereby can realize that the trench hole forms protruding structure in the position department that corresponds with first stop layer in order to reduce the degree of depth of trench hole when carrying out oxidation treatment to trench hole bottom, avoid producing the influence to the homogeneity of trench hole deep punchhole when the trench hole bottom is etched, and then increased the technology window of trench hole bottom sculpture.

Drawings

Fig. 1 is a schematic flow diagram of a method of fabricating a semiconductor device provided by the present disclosure;

FIGS. 2a-2f are schematic structural diagrams of a semiconductor device provided by the present disclosure during fabrication;

fig. 3 is a schematic structural diagram of a semiconductor device provided by the present disclosure;

FIG. 4 is a schematic structural diagram of a memory provided by the present disclosure;

fig. 5 is a schematic structural diagram of a storage system provided by the present disclosure.

Detailed Description

The technical solutions in the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the present disclosure. It should be apparent that the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It will be understood that, although the terms first, second, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present invention.

It will be understood that when an element is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element or intervening elements may also be present. Other words used to describe the relationship between components should be interpreted in a similar manner.

As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. The layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far from the substrate. The layer may extend over the entire underlying or overlying structure, or may have an extent less than the extent of the underlying or overlying structure. Furthermore, the layer may be a region of uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. The layers may extend horizontally, vertically and/or along a tapered surface. The substrate may be a layer, which may include one or more layers, and/or may have one or more layers above, and/or below it. The layer may comprise a plurality of layers. For example, the interconnect layers may include one or more conductive layers and contact layers (in which contacts, interconnect lines, and one or more dielectric layers are formed).

The cross-section of the semiconductor device in various directions is represented herein by a cartesian coordinate system (denoted X, Y and Z), wherein the directions of the XY plane are parallel to the substrate and the Z direction is perpendicular to the substrate.

It should be noted that the drawings provided in the present disclosure are only for illustrating the basic idea of the present invention, and although the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, the type, quantity and proportion of each component in actual implementation can be changed freely, and the layout of the components may be more complicated.

The semiconductor device in the present disclosure may be applied to a wafer or a three-dimensional memory. The three-dimensional memory can be applied to communication products, consumer electronics products, automobile products, aerospace products, artificial intelligence products, big data and the like. Among them, the consumer electronics products include, but are not limited to, mobile phones, computers, tablets, cameras, smart glasses, or game products.

In the related art, as the number of layers of the 3D NAND increases, the etching control of the channel hole profile becomes more difficult. In order to improve the accuracy of etching control of the profile of the channel hole, in the related art, a low-temperature etching process is used to etch the memory structure. However, due to the low selection ratio of SiN (silicon nitride), OX (oxide) and Poly (polysilicon) in the low-temperature etching process, the uniformity of the gouges formed on the substrate of the 3D NAND is poor, thereby affecting the related preparation process of the subsequent back extraction structure.

In order to solve the problem that the uniformity of the via holes formed on the 3D NAND substrate is poor due to the low-temperature etching process, please refer to fig. 1 and fig. 2a-2f, where fig. 1 is a schematic flow diagram of a manufacturing method of the semiconductor device provided by the present disclosure, and fig. 2a-2f are schematic structural diagrams of the semiconductor device provided by the present disclosure in a manufacturing process. It should be noted that fig. 2a-2f only show exemplary structures of the present disclosure, and the semiconductor device provided by the present disclosure may further include other components and/or structures for realizing the complete functions of the device.

Specifically, the method for manufacturing a semiconductor device according to an embodiment of the present disclosure includes steps 101 to 104.

Please refer to step 101 in fig. 1 and fig. 2a.

Step 101, providing a substrate 11 having a lateral surface.

In one embodiment of the present disclosure, the substrate 11 may be a semiconductor substrate, and for example, may be a Silicon (Si), germanium (Ge), siGe substrate, silicon On Insulator (SOI), germanium On Insulator (GOI), or the like. The substrate 11 may be a substrate including other element semiconductors or compound semiconductors, or may have a stacked-layer structure such as Si/SiGe or the like.

As shown in fig. 2a, the Y direction is a lateral direction of the substrate 11, and a plane formed by the X direction and the Y direction is a lateral surface of the substrate 11.

Please refer to step 102 in fig. 1 and fig. 2b.

Step 102 of forming a stacked layer 12 on the substrate 11 side in a longitudinal direction opposite to the lateral surface, the stacked layer 12 including a first stacked structure 121 alternately stacked by a sacrificial layer and an interlayer insulating layer, and a bottom stacked structure 122 alternately stacked by a stop layer and a spacer layer, the stacked layer 12 including a core region M1 and a step region M2, the stop layer including a first stop layer 1221 and a second stop layer 1222, the second stop layer 1222 being located on the first stop layer 1221.

Wherein the stacked layer 12 includes, in a longitudinal direction, i.e., a Z direction, a first stacked structure 121 alternately stacked by sacrificial layers and interlayer insulating layers, and a bottom stacked structure 122 alternately stacked by stop layers and spacer layers. The stacked layer 12 includes a core region M1 and a step region M2 in order in the lateral direction, i.e., the X direction. In the present disclosure, the process for preparing the stacked layer 12 of the semiconductor device provided by the present disclosure is: first, a stacked layer 12 including alternately stacked sacrificial layers and interlayer insulating layers, the number of which is controllable, may be formed on a substrate 11 through a deposition process, such as forming a desired number of sacrificial layers and interlayer insulating layers by adjusting parameters of the deposition process. Among them, an interlayer insulating layer is used to separate a plurality of sacrificial layers, and the material of the interlayer insulating layer may be composed of an oxide such as silicon oxide (SiO 2), and the material of the sacrificial layer may be composed of a nitride such as silicon nitride (SiN). Since the material of the sacrificial layer is mostly nitride, it is advantageous to simultaneously form the stacked layers 12 of a plurality of sacrificial layers and a plurality of interlayer insulating layers, which are alternately stacked, and thus, the stacked layers 12 including the sacrificial layers and the interlayer insulating layers, which are alternately stacked in a direction perpendicular to the lateral surface of the substrate 11, may be formed through a deposition process.

It should be noted that, the stacked layer 12 may be etched, so that the etched stacked layer 12 may include the core region M1 and the step region M2. The length of each step along the direction parallel to the lateral surface of the substrate 11 decreases in order from the direction close to the substrate 11 toward the direction away from the substrate 11. The step region M2 may be located around the core region M1, or may be located in the middle of the core region M1. The step region M2 provided in this embodiment generally refers to the core region M1, and includes a region where a step structure (not shown) is formed and a region where no step structure is formed, where the region where no step structure is formed includes a non-step structure space surrounded by the step structure in the step region M2 and a non-step structure space outside the step structure.

In order to better explain the specific manufacturing method of the semiconductor device provided in this embodiment, the drawings on the left part of fig. 2 b-2 f are shown in the YZ direction, and the drawings on the right part are shown in the XZ direction in this embodiment.

Please refer to step 103 in fig. 1 and fig. 2b.

Step 103, forming a longitudinally extending channel hole 123 in the core region M1 of the stacked layer 12.

In this embodiment, a trench hole 123 is formed in the stack layer 12 by an etching process, such as dry etching, and extends through the stack layer 12 and into the substrate 11.

Please refer to step 104 in fig. 1 and fig. 2c.

In step 104, the first stopper layer 1221 and the second stopper layer 1222 are oxidized in the sidewall of the channel hole 123, wherein an oxidation rate of the first stopper layer 1221 is higher than an oxidation rate of the second stopper layer 1222.

In this embodiment, by making the oxidation rate of the first stopper layer 1221 by the oxidation treatment larger than the oxidation rate of the second stopper layer 1222 by the oxidation treatment, the entire first stopper layer 1221 can be oxidized when the oxidation treatment is performed.

As an alternative embodiment, the step of performing the oxidation treatment on the first stop layer 1221 and the second stop layer 1222 within the sidewall of the channel hole 123 further includes: first and second protruding structures 1221 'and 1222' are formed in the sidewalls of the channel hole 123 at first and second locations corresponding to the first and second stop layers 1221 and 1222, respectively, and the length of the second protruding structure 1222 'in the lateral direction is smaller than the length of the first protruding structure 1221' in the lateral direction.

Alternatively, the present embodiment may control parameters of the oxidation reaction, such as the reaction time, to form the protruding structures with controllable thickness and length, so that the length of the second protruding structures 1222 ' in the lateral direction is smaller than the length of the first protruding structures 1221 ' in the lateral direction, thereby achieving that the second protruding structures 1222 ' will not be blocked by the second protruding structures 1222 ' of the second stop layer 1222 and will smoothly stay at the positions of the first protruding structures 1221 ' when the channel hole 123 is filled, such as polysilicon filling.

As an alternative embodiment, the step of forming the stacked layer 12 on the substrate 11 side in the longitudinal direction opposite to the lateral surface specifically further includes: phosphorus doping the first stop layer 1221; the second stop layer 1222 is carbon doped. By the difference in doping pattern between the first stopper layer 1221 and the second stopper layer 1222, the oxidation rate of the first stopper layer 1221 subjected to oxidation treatment can be made larger than the oxidation rate of the second stopper layer 1222 subjected to oxidation treatment.

Further, the step of forming the stacked layer 12 on the substrate 11 side in the longitudinal direction opposite to the lateral surface specifically includes: the second stopper layer 1222 is surface-treated with ammonia gas. In this embodiment, by performing the surface treatment of the second stopper 1222 using ammonia gas, without performing the surface treatment of the first stopper 1221, the oxidation reaction of the surface of the second stopper 1222 is suppressed when performing the oxidation treatment, and it is possible to ensure that at least when the first stopper 1221 is completely oxidized, a part of the second stopper 1222 is not oxidized. By performing the surface treatment of the second stopper layer 1222 using ammonia gas in this manner, the oxidation rate of the first stopper layer 1221 during the oxidation treatment can be further increased than the oxidation rate of the second stopper layer 1222 during the oxidation treatment, and the purpose of oxidizing the entire first stopper layer 1221 during the oxidation treatment of the first stopper layer 1221 can be achieved.

In one case, the second stopper layer 1222 may be surface-treated with ammonia gas after the second stopper layer 1222 is carbon-doped. In other cases, the second stop layer 1222 may be surface-treated with ammonia gas before the second stop layer 1222 is carbon-doped. The specific treatment method is not particularly limited, and may be any treatment method as long as the oxidation rate of the first stopper layer 1221 in the oxidation treatment is higher than the oxidation rate of the second stopper layer 1222 in the oxidation treatment.

In one embodiment, with continued reference to fig. 2d, the protruding portion of the first protruding structure 1221' in the channel hole 123 forms a gap (not shown) in the longitudinal direction, and the method for manufacturing a semiconductor device further includes: forming a memory function layer 12311 in the channel hole 123, wherein the memory function layer 12311 is attached to the entire inner wall of the channel hole 123 and completely fills the gap; a channel layer 12312 and an insulating layer 12313 are sequentially formed in the channel hole 123 above the first bump structure 1221'.

In another embodiment, the protruding portion of the first protruding structure 1221' in the channel hole 123 is not formed with a gap (not shown) in the longitudinal direction, and the method for manufacturing a semiconductor device specifically includes: a memory function layer 12311, a channel layer 12312, and an insulating layer 12313 are sequentially formed in the channel hole 123 above the first protrusion structure 1221'.

The inner wall of the trench hole 123 may be sequentially filled with one or more filling materials through a deposition process, so as to form the trench structure 1231, where the filling material may be an insulating material or a conductive material.

By directly and sequentially forming the storage function layer 12311, the channel layer 12312, and the insulating layer 12313 in the channel hole 123 above the first bump structure 1221', the formation of the storage function layer 12311 in the channel hole 123 below the first stopper layer 1221 can be avoided, thereby reducing the material required for depositing the storage function layer 12311 below the first stopper layer 1221, reducing the time required for forming the channel structure 1231, simplifying the process flow, and greatly reducing the production cost.

As an optional embodiment, the method for manufacturing a semiconductor device further includes: forming a dummy channel hole 124 longitudinally penetrating the stacked layer 12 in the step region M2; performing oxidation treatment on the first stop layer 1221 in the sidewall of the dummy channel hole 124, and forming a third protrusion 1223' on the sidewall of the bottom of the dummy channel hole 124 corresponding to the first stop layer 1221; the dummy channel hole 124 formed with the third protrusion structure 1223' is filled to form a dummy channel structure. It should be noted that, between the step region M2 and the core region M1, a transition region is also generally provided, and for convenience of description herein, the step region M2 is set to include the transition region.

As shown in fig. 2d, the third protrusion structure 1223' is formed at the position where the sidewall of the bottom of the dummy trench 124 corresponds to the first stop layer 1221, so as to reduce the filling inlet of the oxide filling material, and when the dummy trench 124 is oxide-filled, the filling material required at the bottom of the dummy trench 124 can be effectively reduced, thereby avoiding forming a gap when the bottom of the dummy trench 124 is oxide-filled, and facilitating the formation of a process window when the semiconductor device is subjected to a back side removal process.

Specifically, the protruding structure of the third protruding structure 1223' in the dummy trench hole 124 provided in this embodiment may also have no gap formed in the longitudinal direction, so as to close the filling inlet of the oxide filling material, thereby avoiding the oxide filling material from depositing at the bottom of the dummy trench hole 124 when performing oxide filling on the bottom of the dummy trench hole 124, reducing the material and time required for forming the dummy trench hole structure, simplifying the process flow, and reducing the production cost. Meanwhile, by closing the filling inlet of the oxide filling material, it is also possible to prevent the etching liquid from damaging the internal structure of the dummy channel hole 124 through the gap (filling inlet of the oxide filling material) formed by the protruding structure of the third protruding structure 1223' when performing a back removal process on the semiconductor device, thereby improving the yield of the semiconductor device.

In some embodiments, as shown in fig. 2d, the method for manufacturing a semiconductor device further includes: a gate line isolation structure 125 is formed longitudinally through the stacked layers 12.

Before the gate line isolation structure 125 is formed, the stacked layer 12 needs to be etched to form a gate line isolation trench (not shown in the figure) which penetrates through the stacked layer 12 and extends into the substrate 11, because the number of stacked layers 12 is very large, a deposition process needs to be adopted to form sacrificial layers and interlayer insulating layers which are alternately stacked at one time, then the sacrificial layers are removed through a wet etching process, and finally, a gate layer is formed at the position of the original sacrificial layer, so that the stacked layer 12 including the gate layer and the interlayer insulating layers which are alternately stacked is formed. The gate line isolation groove is filled after the replacement process, so that the gate line isolation structure 125 can be obtained.

It should be noted that, because the oxidation treatment of the first stop layer 1221 is performed through the inner wall of the channel hole 123, and the oxidation treatment of a part of the first stop layer 1221 can cause the edge of the first stop layer 1221 close to the side of the channel hole 123 to generate a swelling phenomenon, when the oxidation treatment is performed on the first stop layer 1221 through the inner wall of the channel hole 123, the edge of the first stop layer 1221 corresponding to the inner wall of the channel hole 123 close to the side of the channel hole 123 is caused to generate a swelling phenomenon when the oxidation reaction is performed on the first stop layer 1221 through the inner wall of the channel hole 123, so that the oxide corresponding to the first stop layer 1221 part close to the gate line isolation groove is obviously thickened, and the tilting problem is caused. Therefore, in this embodiment, the oxidation rate of the first stop layer 1221 during the oxidation process is greater than the oxidation rate of the second stop layer 1222 during the oxidation process, so that when the first stop layer 1221 is oxidized by the inner wall of the channel hole 123, the purpose of oxidizing the first stop layer 1221 completely can be achieved, and the warpage problem can be effectively avoided.

In other embodiments, as shown in fig. 2d, the method for manufacturing a semiconductor device further includes: a contact structure 126 is formed in the step region M2 to longitudinally penetrate through the bottom stacked structure 122.

Specifically, the step of forming the contact structure 126 longitudinally penetrating through the bottom stack structure 122 in the step area M2 includes: forming a dielectric layer 1211 covering the stacked layers in the step area M2; forming a contact hole (not shown) longitudinally penetrating through the dielectric layer 1211 and extending to the second stop layer 1222 in the step region M2; a conductive material is deposited in the contact holes to form contact structures 126. The dielectric layer 1211 may include an insulating material such as silicon oxide.

Referring to fig. 2e and 2f in fig. 1, the method for manufacturing a semiconductor device according to the present embodiment further includes: removing the substrate 11 and the bottom stack structure 122 between the substrate 11 and the second stop layer 1222 and exposing a bottom surface of the channel layer 12312; a source region 13 is formed on the bottom surface 12314 of the channel layer 12312 and the second stop layer 1222.

Specifically, the substrate 11 may be removed by wet etching or dry etching, for example, by using a chemical solution with a certain selection ratio, the etching rate of the chemical solution to the substrate 11 is high, and the etching rate to other film layers is low, so that when the substrate 11 is removed, the other film layers are not substantially damaged, and thus the substrate 11 is removed. Subsequently, a portion of the memory function layer 12311 at the bottom of the channel structure 1231 may be removed by wet etching to expose the channel layer 12312 at the end of the channel structure 1231, especially including the bottom surface 12314 of the channel layer 12312 and the side surface of the end adjacent to the bottom surface 12314.

Specifically, the source region 13 may be formed by depositing one or more polysilicon layers on the bottom of the stack layer 12, i.e., on the original substrate 11, and then performing ion implantation on the polysilicon layers. The source region 13 is used to provide carriers, which may be electrons or holes, to the semiconductor device. The channel layer 12312 is used to provide a path for movement of carriers between the source region 13 and the storage function layer 12311, and thus, the material of the channel layer 12312 needs to be a conductive material, such as polysilicon. Among them, the storage function layer 12311 generally includes a tunneling layer (tunneling layer), a charge trap layer (charge trap layer), and a blocking layer (blocking layer). By removing the substrate 11, a portion of the memory function layer 12311 at the end of the channel structure 1231 is removed to expose the channel layer 12312 at the end of the channel structure 1231, and the source region 13 covers the channel structure 1231 and the bottom of the gate line isolation structure 125, so that the source region 13 is directly in contact with the channel layer 12312 of the channel structure 1231, thereby realizing that carriers in the source region 13 can move freely in the channel layer 12312.

As shown in fig. 2f, after the step of forming the source region 13 on the bottom surface 12314 of the channel layer 12312 and the second stop layer 1222, the method for manufacturing a semiconductor device specifically includes: an insulating structure 14 is formed on the bottom surface of the source region 13, and a conductive structure 15 (PAD) connected to the contact structure 126 and the source region 13 is formed on the bottom surface of the insulating structure 14.

In particular, the insulating structure 14 is located between the source region 13 and the conductive structure 15, and is provided with a via (not shown in the figure) for connecting the conductive structure 15 and the source region 13.

In this embodiment, after forming source region 13, a deposition process is performed on the bottom of source region 13, specifically, by depositing an insulating material such as silicon oxide to form a bottom insulating layer (not shown) on the bottom of source region 13, and then by etching the bottom insulating layer to form a via that is longitudinally open to the bottom of contact structure 126 and source region 13, so that insulating structure 14 as shown in fig. 2f can be obtained. Then, a conductive material is deposited on the bottom of the insulating structure 14, so as to form a conductive structure 15 connected to the bottom of the contact structure 126 and the source region 13 through the via hole.

Referring to fig. 3, fig. 3 is a schematic structural diagram of a semiconductor device provided in the present disclosure, and as shown in fig. 3, the semiconductor device provided in the present disclosure includes: stack structure 22, source region 23, channel structure 2231.

In some embodiments, the stack structure 22 includes a first stack structure 221 in which gate layers and interlayer insulating layers are alternately stacked in a longitudinal direction, and a bottom stack structure 222 having a stop layer 2222, the stack structure 22 includes a core region M1 and a step region M2 in a lateral direction, and the stack structure 22 in the core region M1 is formed with a longitudinally extending channel hole 223. The source region 23 is located at the bottom of the stack structure 22 and contacts the stop layer of the bottom stack structure. The channel structure 2231 is located in the channel hole 223 and includes a storage function layer 22311, a channel layer 22312, and an insulating layer 22313 formed along an inner wall of the channel hole 223.

In which a protruding structure 2222' is formed in a portion of a sidewall of the channel hole 223 corresponding to the stop layer 2222, so that the inner diameter of the channel structure 2231 at the portion is smaller than that of the other portions, and the channel layer 22312 has a bottom surface 22314 extending into the source region 23.

It should be noted that, a portion of the bump structure 2222 ' forming the stop layer 2222 corresponds to the second portion in the foregoing method embodiment, and the formed bump structure 2222 ' also corresponds to the second bump structure 1222 ' in the foregoing method embodiment, and the forming method thereof is the same as that in the foregoing method embodiment, and is not repeated herein.

In this embodiment, the channel layer 22312 extends into the bottom surface 22314 of the source region 23, so that the source region 23 is in direct contact with the channel layer 22312 of the channel structure 2231, thereby allowing carriers in the source region 23 to move freely in the channel layer 22312.

With continued reference to fig. 3, the semiconductor device provided in the embodiment of the present invention further includes: conductive structure 25, insulating structure 24, gate line isolation structure 225, dielectric layer 2211, contact structure 226, and dummy channel structure.

Specifically, the conductive structure 25 is located at the bottom of the source region 23 and is electrically connected to the source region 23. The insulating structure 24 is located between the source region 23 and the conducting structure 25, and is provided with a via (not shown in the figure) for connecting the conducting structure 25 with the source region 23. The gate line isolation structure 225 longitudinally penetrates the stack structure 22 of the core region M1 and extends into the source region 23. The dielectric layer 2211 covers the stack structure 22 of the step area M2. The contact structure 226 longitudinally penetrates through the dielectric layer 2211, extends to a position corresponding to the transverse surface of the stop layer 2222, and is connected to the conductive structure 25. The dummy channel structure (formed after the dummy channel hole 224 filling process) longitudinally penetrates the stack structure 22 of the step region M2, and has a dummy channel structure bottom surface (not shown) contacting the source region 23 at a position corresponding to the lateral surface of the stop layer 2222.

The bottom stacked structure 222 corresponds to the step region M2 of the contact structure 226 in the longitudinal direction, and further includes a first stop layer 2221, and the stop layer 2222 serves as a second stop layer 2222, where an oxidation rate of the first stop layer 2221 is greater than an oxidation rate of the second stop layer 2222.

In this embodiment, the first stop layer (not shown in the figure) near the Gate line isolation structure 225 can be completely oxidized just by making the oxidation rate of the first stop layer 2221 during the oxidation process greater than that of the second stop layer 2222 during the oxidation process, so that the first stop layer near the Gate line isolation structure 225 is oxidized during the oxidation process performed during the formation of the Gate line isolation structure 225, and the Bottom Select Gate (Bottom Select Gate) is obviously thickened, so that a gap is formed during the subsequent tungsten filling, and further, the risk of F attach exists.

Specifically, the first stop layer 2221, the second stop layer 2222, and the source region 23 longitudinally corresponding to the contact structure 226 are provided with a through silicon via (not shown), and the contact structure 226 is connected to the conductive structure 25 through the through silicon via.

In this embodiment, an etching process is performed on the source region 23 to form a through-silicon via on the source region 23, which longitudinally corresponds to the contact structure 226 and the source region 23, so that when the insulating structure 24 is formed later, a through-hole for connecting the conductive structure 25 with the contact structure 226 and the source region 23 can be formed according to the through-silicon via.

Referring to fig. 4, fig. 4 is a schematic structural diagram of a memory according to the present disclosure. The memory 200 may be a three-dimensional memory, such as a 3D NAND, 3D NOR memory.

The memory 200 includes a semiconductor device 201 and a peripheral circuit 202, the semiconductor device 201 may be a semiconductor device manufactured by the manufacturing method of any one of the semiconductor devices in the above embodiments, and the peripheral circuit 202 may be cmos (complementary metal oxide semiconductor). The semiconductor device 201 may be stacked with the peripheral circuit 202, or may be staggered with the peripheral circuit 202, which is not limited in this application. The peripheral circuit 202 is electrically connected to the semiconductor device 201 to transmit signals with the semiconductor device 201. The peripheral circuit 202 may be used for logic operation and controlling and detecting the switching state of each memory cell in the semiconductor device 201 through a metal wire, so as to implement data storage and data reading.

The semiconductor device 201 comprises a stack structure, wherein the stack structure comprises a first stack structure formed by alternately stacking a gate layer and an interlayer insulating layer in the longitudinal direction and a bottom stack structure with a stop layer, the stack structure comprises a core region and a step region in the transverse direction, and a longitudinally extending channel hole is formed in the stack structure positioned in the core region; the source region is positioned at the bottom of the stack structure; and a channel structure located in the channel hole and including a memory functional layer, a channel layer and an insulating layer formed along the channel hole inner wall; and a raised structure is formed in the side wall of the channel hole corresponding to the stop layer, so that the inner diameter of the channel structure at the position is smaller than that of other positions, and the channel layer has a bottom surface extending into the source region.

Referring to fig. 5, fig. 5 is a schematic structural diagram of a memory system provided in the present disclosure. The memory system 300 includes a memory 301 and a controller 302, the memory 301 may be the memory in any of the embodiments, the memory 301 may include any of the semiconductor devices in the embodiments, the controller 302 is electrically connected to the memory 301 and is configured to control the memory 301 to store data, and the memory 301 may perform an operation of storing data based on the control of the controller 302.

In some embodiments, the storage system may be implemented as a memory device such as a Universal Flash Storage (UFS) device, a Solid State Disk (SSD), a multi-media card in the form of an MMC, eMMC, RS-MMC, and micro-MMC, a secure digital card in the form of an SD, mini-SD, and micro-SD, a Personal Computer Memory Card International Association (PCMCIA) card type memory device, a Peripheral Component Interconnect (PCI) type memory device, a PCI express (PCI-E) type memory device, a Compact Flash (CF) card, a smart media card, or a memory stick, and so forth.

The semiconductor device in the memory 301 includes a stack structure including a first stack structure in which gate layers and interlayer insulating layers are alternately stacked in a longitudinal direction, and a bottom stack structure having a stopper layer, the stack structure including a core region and a step region in a lateral direction, and the stack structure in the core region being formed with a longitudinally extending channel hole; the source region is positioned at the bottom of the stack structure; and a channel structure located in the channel hole and including a memory functional layer, a channel layer and an insulating layer formed along the channel hole inner wall; wherein, a raised structure is formed in the side wall of the channel hole corresponding to the stop layer, so that the inner diameter of the channel structure at the position is smaller than that of other parts, and the channel layer has a bottom surface extending into the source region.

The above description of the embodiments is only for helping understanding the technical solution of the present invention and its core idea; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing a semiconductor device, comprising:

providing a substrate having a lateral surface;

2. The method for manufacturing a semiconductor device according to claim 1, wherein the step of subjecting the first stop layer and the second stop layer to oxidation treatment within the sidewall of the channel hole further comprises:

forming a first protrusion structure and a second protrusion structure in a sidewall of the channel hole at a first portion and a second portion corresponding to the first stop layer and the second stop layer, respectively, the second protrusion structure having a length in the lateral direction smaller than a length of the first protrusion structure in the lateral direction.

3. The method for manufacturing a semiconductor device according to claim 2, wherein the step of forming a stack of layers on the substrate side in a longitudinal direction opposite to the lateral surface further comprises:

carrying out phosphorus doping on the first stop layer;

and doping the second stop layer with carbon.

4. A method for manufacturing a semiconductor device according to claim 3, wherein the step of forming a stack of layers on the substrate side in a longitudinal direction opposite to the lateral surface further comprises:

5. The method for manufacturing a semiconductor device according to claim 2, wherein a convex portion of the first convex structure in the channel hole forms a slit in the longitudinal direction, the method for manufacturing a semiconductor device further comprising:

6. The method for manufacturing a semiconductor device according to claim 2, wherein a protruding portion of the first protruding structure in the channel hole is not formed with a slit in the longitudinal direction, the method for manufacturing a semiconductor device further comprising:

and sequentially forming a storage function layer, a channel layer and an insulating layer in the channel hole above the first protruding structure.

7. The method for manufacturing a semiconductor device according to claim 1, further comprising:

forming a dummy channel hole longitudinally penetrating through the stacked layers in the step area;

8. The manufacturing method of a semiconductor device according to claim 7, wherein a convex portion of the third convex structure in the dummy channel hole is not formed with a slit in the longitudinal direction.

9. The method for manufacturing a semiconductor device according to claim 5 or 6, further comprising:

10. The method for manufacturing a semiconductor device according to claim 9, wherein after the step of forming a source region on the bottom surface of the channel layer and the second stop layer, the method for manufacturing a semiconductor device further comprises:

11. The method of manufacturing a semiconductor device according to claim 9, wherein the step of forming a contact structure in the step area longitudinally penetrating through the bottom stack structure comprises:

forming a dielectric layer covering the stacked layers in the step area;

12. A semiconductor device, characterized in that the semiconductor device comprises:

a stack structure including a first stack structure alternately stacked by gate layers and interlayer insulating layers in a longitudinal direction, and a bottom stack structure having a stopper layer, the stack structure including a core region and a terrace region in a lateral direction, and the stack structure located in the core region being formed with a longitudinally extending channel hole;

13. The semiconductor device according to claim 12, further comprising:

14. The semiconductor device according to claim 12, further comprising:

15. The semiconductor device according to claim 13, further comprising:

the dielectric layer covers the stack structure of the step area; and

16. The semiconductor device according to claim 12, further comprising:

and the dummy channel structure longitudinally penetrates through the stack structure of the step region and is provided with a dummy channel structure bottom surface which is contacted with the source region at a position corresponding to the transverse surface of the stop layer.

17. The semiconductor device of claim 15, wherein the bottom stack structure corresponds to a step region of the contact structure in a longitudinal direction, further comprising a first stop layer, and the stop layer functions as a second stop layer, an oxidation rate of the first stop layer being greater than an oxidation rate of the second stop layer.

18. The semiconductor device of claim 17, wherein the first and second stop layers, and the source region longitudinally corresponding to the contact structure, are provided with a through-silicon via through which the contact structure is connected to the conductive structure.

19. A memory, comprising: a semiconductor device produced by the method for producing a semiconductor device according to any one of claims 1 to 11, and a peripheral circuit electrically connected to the semiconductor device.

20. A storage system, comprising:

the memory of claim 19, and

the controller is electrically connected with the memory and is used for controlling the memory to store data.