CN114551332A - Semiconductor device, manufacturing method thereof, memory, storage system and electronic equipment - Google Patents

Semiconductor device, manufacturing method thereof, memory, storage system and electronic equipment Download PDF

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Publication number
CN114551332A
CN114551332A CN202210167810.0A CN202210167810A CN114551332A CN 114551332 A CN114551332 A CN 114551332A CN 202210167810 A CN202210167810 A CN 202210167810A CN 114551332 A CN114551332 A CN 114551332A
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Prior art keywords
filling
layer
trench
filling layer
substrate
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Chinese (zh)
Inventor
李刚
郭申
桑瑞
张志雄
张�成
陈成
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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Priority to CN202210167810.0A priority Critical patent/CN114551332A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Element Separation (AREA)

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof, a memory, a storage system and an electronic device, comprising: forming a substrate; forming a groove on a substrate; filling along the side wall and the bottom surface of the groove to form a first filling layer, wherein the first filling layer fills part of the space in the groove; removing a part of the first filling layer far away from the side wall and the bottom surface to form a trimming filling layer; the second filling layer is formed by filling the trimming filling layer in the groove, so that the problem that the large-angle groove is difficult to be completely filled by filling materials can be solved, and when the manufacturing method of the semiconductor device is applied to forming the shallow groove isolation structure in the IC device, the seam or the gap in the shallow groove isolation structure can be reduced, so that the breakdown resistance of the shallow groove isolation structure is improved, the electrical isolation effect of the shallow groove isolation structure can be improved, and the product quality is favorably improved.

Description

Semiconductor device, manufacturing method thereof, memory, storage system and electronic equipment
[ technical field ] A method for producing a semiconductor device
The invention relates to the technical field of semiconductor devices, in particular to a semiconductor device and a manufacturing method thereof, a memory, a storage system and electronic equipment.
[ background of the invention ]
In a semiconductor device, as the requirement for the depth of a trench is deeper and deeper, the angle of the trench (i.e., the acute angle between the sidewall and the bottom plane of the trench) is closer and closer to a right angle, and how to fill the large-angle trench with a material becomes a big problem, and a solution is needed.
[ summary of the invention ]
The embodiment of the invention provides a semiconductor device, a manufacturing method thereof, a memory, a storage system and electronic equipment, and aims to solve the problem that a large-angle groove is difficult to be completely filled with a filling material, so that the performance of the filling material in the large-angle groove is improved.
In order to at least partially solve the above problem, an embodiment of the present invention provides a method for manufacturing a semiconductor device, where the method for manufacturing a semiconductor device includes: forming a substrate; forming a groove on a substrate; filling along the side wall and the bottom surface of the groove to form a first filling layer, wherein the first filling layer fills part of the space in the groove; removing a part of the first filling layer far away from the side wall and the bottom surface to form a trimming filling layer; and filling the trimming filling layer in the groove to form a second filling layer.
The step of filling along the sidewall and the bottom surface of the trench to form a first filling layer specifically includes: a first deposition of a fill material is performed to deposit a first fill layer on the sidewalls and bottom surface of the trench.
Filling the trimmed filling layer in the groove to form a second filling layer, wherein the step of forming the second filling layer specifically comprises the following steps: a second deposition of fill material is performed to deposit a second fill layer over the trim fill layer in the trench.
Wherein, the first deposition is completed by adopting a chemical vapor deposition process, and the second deposition is completed by adopting an atomic layer deposition process.
The step of removing a portion of the first filling layer away from the sidewall and the bottom surface to form a trimmed filling layer specifically includes: the first filling layer is etched along the direction towards the bottom surface so as to remove the part of the first filling layer far away from the side wall and the bottom surface, thereby forming a trimming filling layer.
The step of forming the substrate specifically includes: providing a substrate; forming a first insulating layer over a substrate; forming a second insulating layer on the first insulating layer, wherein the trench penetrates through the second insulating layer and the first insulating layer and extends into the substrate; and the manufacturing method of the semiconductor device further comprises the following steps: and filling the trimming filling layer in the groove, and removing the second insulating layer after the step of forming the second filling layer.
After the second filling layer is formed, the obtained filler filled in the trench is a shallow trench isolation structure, the substrate comprises a plurality of well regions, and two adjacent well regions are separated by the shallow trench isolation structure.
The well region comprises a source region, a channel region and a drain region which are connected in sequence, and after the step of removing the second insulating layer, the manufacturing method of the semiconductor device further comprises the following steps: forming a gate insulating layer on the channel region; a gate electrode layer is formed on the gate insulating layer.
The acute included angle between the side wall and the surface of the substrate with the groove is not smaller than a preset angle, and the value range of the preset angle is 80-90 degrees.
Wherein the volume ratio of the partial space to the whole space in the groove is 0.7-0.8.
In order to at least partially solve the above problem, an embodiment of the present invention also provides a semiconductor device including: a substrate, wherein a groove is arranged on the substrate; a filler filling the trench and including a trim fill layer and a second fill layer; wherein the trimming filling layer is positioned on the side wall and the bottom surface of the groove, fills partial space in the groove, and is separated by the second filling layer between the opposite surfaces of the trimming filling layer facing away from the side wall.
One end of the filler is filled in the groove, and the other end of the filler extends to the upper part of the substrate.
Wherein, the filler is a shallow trench isolation structure.
The substrate comprises a plurality of well regions, and two adjacent well regions are separated by a shallow trench isolation structure.
Wherein, well region includes source region, channel region and the drain region that connects gradually, and semiconductor device still includes: a gate insulating layer on the channel region; and a gate electrode layer on the gate insulating layer.
The acute included angle between the side wall and the surface of the substrate provided with the groove is not smaller than a preset angle, and the value range of the preset angle is 80-90 degrees.
In order to at least partially solve the above problem, an embodiment of the present invention further provides a memory including a memory array and a peripheral device electrically connected, the peripheral device being the semiconductor device of any one of the above.
In order to at least partially solve the above problem, an embodiment of the present invention further provides a storage system, which includes a controller and the memory of any one of the above, wherein the controller is coupled to the memory and is used for controlling the memory to store data.
In order to solve the above problem, an embodiment of the present invention further provides an electronic device, which includes the storage system in any one of the above.
The embodiment of the invention has the beneficial effects that: the semiconductor device, the manufacturing method thereof, the memory, the storage system and the electronic device provided by the embodiment of the invention form the substrate, form the groove on the substrate, then fill along the side wall and the bottom surface of the groove to form the first filling layer, the first filling layer fills part of the space in the groove, then remove part of the first filling layer far away from the side wall and the bottom surface in the first filling layer to form the trimming filling layer, and then fill the trimming filling layer in the groove to form the second filling layer, thereby solving the problem that the large holes exist in the filler in the large-angle groove and further influence the performance of the semiconductor device due to the fact that the large-angle groove is difficult to be completely filled by the filling material, and reducing the gaps or gaps in the shallow groove isolation structure when the manufacturing method of the semiconductor device is applied to form the shallow groove isolation structure in the IC device, the breakdown resistance of the shallow trench isolation structure is improved, so that the electrical isolation effect of the shallow trench isolation structure can be improved, and the product quality is improved.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 2 is a schematic cross-sectional view of the completed step S11 according to the embodiment of the present invention;
FIG. 3 is a schematic top view of a substrate according to an embodiment of the present invention;
fig. 4 is a schematic cross-sectional view of the completed step S12 according to the embodiment of the present invention;
fig. 5 is a schematic cross-sectional view of the completed step S13 according to the embodiment of the present invention;
fig. 6 is a schematic cross-sectional view of the completed step S14 according to the embodiment of the present invention;
FIG. 7 is a cross-sectional view of another embodiment of a fill material filling a trench;
FIG. 8 is a schematic cross-sectional view of the completed step S13 according to the present invention;
fig. 9 is a schematic cross-sectional view of the completed step S14 according to the present invention;
FIG. 10 is a schematic cross-sectional view of the completed step S15 according to the present invention;
FIG. 11 is a schematic cross-sectional view of a completed step S16 according to an embodiment of the present invention;
FIG. 12 is a schematic cross-sectional view of the modified filling layer and the second filling layer outside the trench according to the embodiment of the invention;
fig. 13 is a schematic cross-sectional view of the completed step S17 according to the embodiment of the present invention;
fig. 14 is a schematic cross-sectional view of the completed step S18 according to the embodiment of the present invention;
FIG. 15 is a diagram illustrating a memory structure according to an embodiment of the present invention;
FIG. 16 is a schematic structural diagram of a storage system according to an embodiment of the present invention;
fig. 17 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
[ detailed description ] embodiments
The embodiments of the present invention will be described in further detail with reference to the drawings and the embodiments. It is to be noted that the following examples are only illustrative of the present invention, and do not limit the scope of the present invention. Similarly, the following examples are only some examples but not all examples of the embodiments of the present invention, and all other examples obtained by those skilled in the art without any inventive work are within the scope of the embodiments of the present invention.
In addition, directional terms used in the embodiments of the present invention, such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], etc., refer to directions of the attached drawings only. Accordingly, the directional terms used are used for describing and understanding the embodiments of the present invention, and are not used for limiting the embodiments of the present invention. In the various figures, elements of similar structure are identified by the same reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. Moreover, some well-known elements may not be shown in the figures.
Embodiments of the invention may be presented in various forms, some examples of which are described below.
Referring to fig. 1, fig. 1 is a schematic flow chart of a manufacturing method of a semiconductor device according to an embodiment of the present invention, and the specific flow of the manufacturing method of the semiconductor device may be as follows:
step S11: a substrate is formed.
Fig. 2 shows a schematic cross-sectional structure of the completed step S11.
The material of the substrate 21 may include a semiconductor material such as Silicon, germanium, or Silicon-On-Insulator (SOI). In one embodiment, the base 21 may be embodied as a substrate 211.
In another embodiment, as shown in fig. 2, the base 21 may further specifically include a substrate 211, and a first insulating layer 212 and a second insulating layer 213 sequentially disposed on the substrate 211. Accordingly, the step S11 may specifically include:
step S111: a substrate 211 is provided.
The substrate 211 may be a semiconductor substrate, such as a Silicon (Si) substrate, a Germanium (Ge) substrate, a SiGe substrate, a Silicon On Insulator (SOI) substrate, or a Germanium On Insulator (GOI) substrate.
In one embodiment, as shown in FIG. 3, the substrate 211 may include a plurality of isolation regions 211A/211B, such as a first isolation region 211A and a second isolation region 211B. Also, different isolation regions 211A/211B may be used to isolate different regions in the substrate 211. Also, in some embodiments, the isolation regions 211A/211B may be integrally connected.
Specifically, as shown in fig. 3, the substrate 211 may further include a plurality of well regions 211C/211D, such as a first well region 211C and a second well region 211D. Also, two adjacent well regions 211C/211D may be separated by the isolation regions 211A/211B described above. For example, the first isolation region 211A may be located around the first well region 211C to isolate the first well region 211C from other regions (e.g., other well regions) around the first well region 211C, thereby facilitating independent control of the transistors formed based on the first well region 211C. The second isolation region 211B may be located around the second well region 211D to isolate the second well region 211D from other regions (e.g., other well regions) around the second well region 211D, so as to facilitate independent control of the transistors formed based on the second well region 211D.
In addition, in a specific implementation, ions may be doped on the upper surface of the substrate 211 (i.e., the surface facing the first insulating layer 212 and the second insulating layer 213 in a subsequent process) to form the plurality of well regions 211C/211D disposed at intervals.
The well regions 211C/211D can be P-type well regions or N-type well regions. Specifically, the P-type well region may be formed by P-type heavy doping, and the N-type well region may be formed by N-type heavy doping. Taking the substrate 211 as a silicon substrate as an example, the substrate 211 may be doped with a group v element, such as nitrogen, phosphorus, arsenic, etc., to form the N-type well region, and the substrate 211 may be doped with a group iii element, such as boron, aluminum, etc., to form the P-type well region.
It should be noted that, in the embodiment, the substrate 211 shown in fig. 3 includes a plurality of isolation regions 211A/211B and a plurality of well regions 211C/211D, and when the substrate 211 in fig. 2 and fig. 4 to 14 described below includes a plurality of isolation regions 211A/211B and a plurality of well regions 211C/211D, the substrate 211 in fig. 2 and fig. 4 to 14 described below may be a partial cross-sectional view of the substrate 211 shown in fig. 3 taken along the line E-E'.
Step S112: a first insulating layer 212 is formed over the substrate 211.
Specifically, the exposed surface of the substrate 211 may be oxidized by a thermal oxidation process to form the first insulating layer 212. The material of the first insulating layer 212 may be, but is not limited to, silicon oxide, and the first insulating layer 212 can reduce stress applied to the substrate 211 in subsequent process steps, thereby preventing the substrate 211 from cracking, and improving product reliability of a semiconductor device manufactured subsequently.
Step S113: a second insulating layer 213 is formed on the first insulating layer 212.
Specifically, a thin film deposition process (e.g., a chemical vapor deposition process) may be used to form the second insulating layer 213 on the first insulating layer 212, wherein the material of the second insulating layer 213 may be, but is not limited to, silicon nitride.
Step S12: a trench is formed in a substrate.
Fig. 4 shows a schematic cross-sectional structure diagram after step S12 is completed.
Specifically, the trench 22 may penetrate the second insulating layer 213 and the first insulating layer 212 and extend into the substrate 211 to form a shallow trench 221 on the substrate 211. In a specific implementation, an anisotropic etching process (e.g., a dry etching process) may be used to sequentially etch the second insulating layer 213, the first insulating layer 212, and the substrate 211 from top to bottom, so as to form the trench 22 vertically penetrating through the second insulating layer 213, the first insulating layer 212, and a portion of the substrate 211 from top to bottom.
In an embodiment, the number of the trenches 22 may be multiple, and the multiple trenches 22 are spaced apart from each other and may correspond to the multiple isolation regions 211A/211B one by one. That is, one trench 22 may be formed on each isolation region 211A/211B. Specifically, the trenches 22 may surround the well regions 211C/211D for one circle to separate adjacent well regions 211C/211D. In a specific implementation, an anisotropic etching process (e.g., a dry etching process) may be used to sequentially etch the second insulating layer 213 and the first insulating layer 212 on the isolation regions 211A/211B and a portion of the substrate 211 in the isolation regions 211A/211B from top to bottom, so as to form the trenches 22.
Step S13: and filling along the side wall and the bottom surface of the groove to form a first filling layer, wherein the first filling layer fills part of the space in the groove.
Fig. 5 shows a schematic cross-sectional structure diagram after step S13 is completed.
In the present embodiment, the material of the first filling layer 231 may include, but is not limited to, an insulating material such as silicon oxide. Specifically, a volume ratio of a portion of the trench 22 filled by the first filling layer 231 to a total space in the trench 22 may be in a range of 0.7 to 0.8, and for example, a volume ratio of a portion of the trench 22 filled by the first filling layer 231 to a total space in the trench 22 may be 0.7, 0.75, or 0.8. Moreover, compared with a scheme that the trench needs to be filled in one time, the present embodiment can fill the trench 22 in multiple times, which is beneficial to reducing the difficulty of the filling process.
In a specific embodiment, the step S13 may specifically include: a first deposition of a filling material is performed to deposit and form the first filling layer 231 on the sidewalls 22A and the bottom surface 22B of the trench 22.
The first Deposition may be performed by an Atomic Layer Deposition process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Flow Chemical Vapor Deposition (FCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition (LPCVD), High Density Plasma Chemical Vapor Deposition (HDPCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD), Metal-organic Chemical Vapor Deposition (MOCVD), Deposition (Atomic Layer Deposition, etc.
Moreover, it can be understood that, since the first deposition does not need to fill the trench 22 and only needs to deposit and form the first filling layer 231 with a certain thickness on the sidewall 22A and the bottom surface 22B of the trench 22, the requirement of the first deposition on the deposition process is not high, and the requirement of the first deposition on the deposition process can be well satisfied by the conventional chemical vapor deposition. Therefore, in practical implementation, a conventional chemical vapor deposition process may be used to perform a first deposition of the filling material to form the first filling layer 231 on the sidewall 22A and the bottom surface 22B of the trench 22. Compared with other thin film deposition processes, the conventional chemical vapor deposition process has cheaper materials and equipment, and is more favorable for reducing the production cost.
In some embodiments, as shown in fig. 5, the trench 22 may be specifically formed on the upper surface of the substrate 21, and the first filling layer 231 may cover the upper surface of the substrate 21 in addition to filling a part of the space in the trench 22.
Specifically, the first filling layer 231 may conform to the upper surface of the substrate 21, so that the trench 22 located on the upper surface of the substrate 21 can be copied onto a surface (i.e., an upper surface) of the first filling layer 231 facing away from the substrate 21, so as to obtain the first recess 24 located on the upper surface of the first filling layer 231.
Thus, the mask required by the process of forming the first filling layer 231 can be saved, and the first groove 24 on the upper surface of the first filling layer 231 can also be used as an alignment mark in the process of forming the trimmed filling layer in the subsequent process, so as to achieve self-alignment, and further save the mask required by the process of trimming the filling layer in the subsequent process.
Step S14: and removing the part of the first filling layer far away from the side wall and the bottom surface to form a trimming filling layer.
Fig. 6 shows a schematic cross-sectional structure diagram after step S14 is completed.
Specifically, the inventors found that after filling the trench 22 with a filling material to form the first filling layer 231 on the sidewall 22A and the bottom surface 22B of the trench 22, interconnection between opposite surfaces of the first filling layer 231 away from the sidewall 22A, which fill the inner space of the trench 22, is very likely to occur, so that the trench 22 may be sealed in advance, and further, the trench 22 may not be completely filled in a subsequent filling process and larger voids may exist therein, and the existence of these voids may affect the performance of the finally formed filler in the trench 22.
For example, as shown in fig. 5, after the first filling-up layer 231 is formed, the spacing distance between the opposite surfaces of the first filling-up layer 231 facing away from the side wall 22A, which are filled in the inner space of the trench 22, may be very small at the local position R of the trench 22. Next, as shown in fig. 7, if the filling material is continuously filled into the trench 22 so that the thickness of the first filling layer 231 is increased to fill the entire space in the trench 22, the trench 22 is sealed in advance, and cannot be completely filled with the filling material, and a large cavity 22C is formed therein.
For another example, as shown in fig. 8, after the first filling layer 231 is formed, an interconnection may occur between opposite surfaces of the first filling layer 231, which are away from the sidewall 22A, of the partial space in the trench 22, so that the trench 22 is sealed in advance, and the trench 22 cannot be completely filled in a subsequent filling process, and a large void 22C exists therein.
Moreover, it can be understood that, by removing a portion of the first filling layer 231 that is far away from the sidewall 22A and the bottom surface 22B of the trench 22, the spacing distance between the opposite surfaces of the first filling layer 231 that are away from the sidewall 22A and fill the partial space in the trench 22 can be increased, and the opposite surfaces of the first filling layer 231 that are away from the sidewall 22A and fill the partial space in the trench 22 can be changed from interconnection to mutual disconnection to leave a gap therebetween, so that the remaining space in the trench 22 can be more easily and completely filled with the filling material in the subsequent filling process, thereby facilitating to eliminate or reduce the gap or void inside the filling material filled in the trench 22.
In an embodiment, as shown in fig. 9, the step S14 may specifically include: the trim filling layer 230 is formed by etching the first filling layer 231 in a direction toward the bottom surface 22B of the trench 22, for example, in a direction perpendicular to the bottom surface 22B of the trench 22 (i.e., a Z direction in fig. 9), so as to remove a portion of the first filling layer 231 away from the sidewall 22A and the bottom surface 22B of the trench 22. Wherein the etching depth may be less than the thickness of the first filling layer 231.
Specifically, as shown in fig. 5, the first filling layer 231 may be conformally covered on the surface of the substrate 21 on which the trench 22 is formed. Also, as shown in fig. 9, in the process of etching the first filling layer 231 in the direction perpendicular to the bottom surface 22B of the trench 22, the etchant may have the same etching rate for each region of the first filling layer 231 in the direction perpendicular to the bottom surface 22B of the trench 22. Therefore, a mask is not needed in the etching process for forming the trim filling layer 230, that is, the mask used in the etching process for forming the trim filling layer 230 can be saved, and the production cost is reduced.
It is understood that, in the present embodiment, by controlling the etching depth to be smaller than the thickness of the first filling layer 231, it is ensured that the surface of the substrate 21 or the second insulating layer 213 is always covered by the first filling layer 231 during the process of etching the first filling layer 231 to form the trim filling layer 230, so that the substrate 21 or the second insulating layer 213 is prevented from being damaged by the etchant.
Furthermore, by controlling the etching depth to be smaller than the thickness of the first filling layer 231, it is also possible to ensure that the sidewall 22A and the bottom surface 22B of the trench 22 are always covered by the first filling layer 231 during the process of etching the first filling layer 231 to form the trim filling layer 230.
It should be noted that the specific value of the etching depth can be obtained through multiple tests. And, the etch depth may be a minimum value that satisfies a preset condition, in particular. The preset condition may specifically be: after the etching process is performed to remove a portion of the first filling layer 231 away from the sidewall 22A and the bottom surface 22B of the trench 22, the spacing distance between the opposite surfaces of the first filling layer 231 away from the sidewall 22A, which are filled in the internal space of the trench 22, can be increased, and the opposite surfaces of the first filling layer 231 away from the sidewall 22A, which are filled in the internal space of the trench 22, are not connected to each other by interconnection.
In one embodiment, the thickness of the first filling-up layer 231 may be 50 nm, and the etching depth may be 30 nm.
Step S15: and filling the trimming filling layer in the groove to form a second filling layer.
Fig. 10 illustrates a schematic cross-sectional structure diagram after step S15 is completed.
In the present embodiment, the material of the second filling-up layer 232 may include, but is not limited to, an insulating material such as silicon oxide. Specifically, after forming the second filling layer 232 to complete the filling of the trench 22, the resulting filler 23 filled in the trench 22 may include the trim filling layer 230 filled in the trench 22 and the second filling layer 232 filled in the trench 22.
In one embodiment, a second deposition of the fill material may be performed to deposit a second fill layer 232 over the trim fill layer 230 in the trench 22.
The second deposition may be performed by a thin film deposition process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Flow Chemical Vapor Deposition (FCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition (LPCVD), High Density Plasma Chemical Vapor Deposition (HDPCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD), Metal Organic Chemical Vapor Deposition (MOCVD), Atomic Layer Deposition (ALD), and the like.
The first deposition and the second deposition may be performed by the same thin film deposition process, or may be performed by different thin film deposition processes.
In one possible application scenario, the first deposition and the second deposition may be performed by a low-cost chemical vapor deposition process. Thus, compared with the scheme of forming the filler in the trench by one chemical vapor deposition, which may cause a problem of a large seam or void inside the filler, in the present embodiment, by two chemical vapor depositions, and before performing the second chemical vapor deposition, the first filling layer 231 formed by the first chemical vapor deposition is trimmed to open the sealed region in the trench 22 and the region with the sealing tendency in the trench 22, so that the remaining space in the trench 22 is more easily and completely filled by the second filling layer 232 formed by the second chemical vapor deposition, thereby being beneficial to eliminating or reducing the seam or void inside the filler 23 filled in the trench 22.
In another possible application scenario, the first deposition may be performed by a chemical vapor deposition process, and the second deposition may be performed by an atomic layer deposition process. Compared with the chemical vapor deposition process, the atomic layer deposition process has the advantages of uniform film thickness, layer-by-layer deposition, good bonding strength, good component uniformity and the like, and therefore, the atomic layer deposition process is adopted for the second deposition, which is more beneficial to completely filling the residual space in the trench 22 formed with the trimming filling layer 230 by the second filling layer 232.
In some alternative embodiments, the second deposition may be performed by other thin film deposition processes (e.g., flow cvd) with better film quality than conventional cvd processes. Moreover, it can be understood that, compared to performing a single deposition to fill the trench 22 by using another film deposition process with a film quality better than that of the conventional chemical vapor deposition process, in the present embodiment, a conventional chemical vapor deposition process with a low cost is first performed to perform a first deposition to form a first filling layer 231 filling most of the space (for example, 70% to 80% of the space) in the trench 22, and after the first filling layer 231 is properly trimmed, a film deposition process with a high cost but a better film quality is then performed to perform a second deposition to form a second filling layer 232 filling the remaining space in the trench 22, so that the process cost for filling the trench 22 can be reduced and the holes or gaps inside the filler 23 filled in the trench 22 can be reduced.
In some embodiments, as shown in fig. 4, an acute included angle θ between the sidewall 22A of the trench 22 and the surface of the substrate 21 on which the trench 22 is formed (i.e., the upper surface of the substrate 21) may be not smaller than a predetermined angle, that is, the angle of the trench 22 is not smaller than the predetermined angle, wherein the predetermined angle may range from 80 degrees to 90 degrees, and for example, the predetermined angle may be 90 degrees, 86 degrees, or 85 degrees. In addition, in the embodiment, the scheme of sequentially performing the preamble step S12, the step S13, and the step S14 to form the filler 23 in the trench 22 can well satisfy the requirement of the large-angle trench 22 on the step coverage capability, so as to solve the problem that the conventional chemical vapor deposition process has a limited filling capability and is difficult to fill the large-angle trench, and further can be used as a substitute scheme for filling the trench 22 with the filler by performing one-step deposition of the filler material by using a high-cost thin film deposition process (e.g., flow chemical vapor deposition), which is beneficial to reducing the process cost.
In the above embodiments, the filler 23 may be specifically a shallow trench isolation structure 23 (in this case, the shallow trench isolation structure and the filler are denoted by the same reference numerals), and the material of the shallow trench isolation structure 23 may be, but is not limited to, silicon oxide. Specifically, two adjacent well regions 211C/211D in the substrate 211 can be separated by the shallow trench isolation structure 23 to achieve electrical isolation.
Moreover, compared to the scheme of filling the trench 22 with a filling material once to obtain the sti structure, which is prone to cause a problem of a large void inside the sti structure, in the present embodiment, there may be no hole or gap or only a small hole or gap inside the sti structure 23 formed by sequentially performing the steps S12, S13, and S14. Because the dielectric constant of air is low, holes or gaps inside the shallow trench isolation structure 23 are reduced or decreased, the electrical breakdown resistance of the shallow trench isolation structure 23 can be enhanced, and the electrical isolation effect of the shallow trench isolation structure 23 on each discrete component in a semiconductor device (e.g., an IC device) can be further improved.
In some embodiments, after the step S15, the method for manufacturing a semiconductor device may further include:
step S16: and removing the second insulating layer.
Fig. 11 shows a schematic cross-sectional structure of the completed step S16.
Specifically, as shown in fig. 12, before removing the second insulating layer 213, the method for manufacturing the semiconductor device may further include: the second insulating layer 213 is used as a polishing stop layer to polish the trim filling layer 230 and the second filling layer 232 outside the trench 22 until the second insulating layer 213 is exposed, and the filler 23 may be composed of the remaining trim filling layer 230 and the remaining second filling layer 232. Next, as shown in fig. 11, the second insulating layer 213 may be selectively etched and removed with respect to the first insulating layer 212, the trim fill layer 230, and the second fill layer 232 by using a selective etchant, so as to expose an end portion of the filler 23 extending to a side of the first insulating layer 212 facing away from the substrate 211.
In some embodiments, after step S16, the method for manufacturing a semiconductor device may further include:
step S17: a gate insulating layer is formed on the channel region.
Fig. 13 shows a schematic cross-sectional structure diagram after step S17 is completed.
Specifically, as shown in FIG. 3, the well region 211C/211D may include a source region 211C-1/211D-1, a channel region 211C-2/211D-2, and a drain region 211C-3/211D-3 connected in sequence. The gate insulating layers 24A/24B may be used to provide gate insulating layers for transistors subsequently formed based on the well regions 211C/211D, among other things. Also, the gate insulating layers 24A/24B located on different channel regions 211C-2/211D-2 may have different thicknesses, e.g., the thickness of the gate insulating layer 24A located on the first channel region 211C-2 may be greater than the thickness of the gate insulating layer 24B located on the second channel region 211D-2.
In some embodiments, the first insulating layer 212 may be removed before the gate insulating layer 24A/24B is formed on the channel regions 211C-2/211D-2, so as to re-expose the surface of the substrate 211.
Step S18: a gate electrode layer is formed on the gate insulating layer.
Fig. 14 shows a schematic cross-sectional structure of the completed step S18.
In particular, gate layers 25A/25B may be used to provide gates for transistors subsequently formed based on well regions 211C/211D. And, the material of the gate layer may include polysilicon.
In one possible application scenario, the semiconductor device may include a plurality of transistors, and the plurality of transistors may be divided into at least one transistor type (e.g., a high-voltage transistor type, a low-voltage transistor type, an ultra low-voltage transistor type, etc.) according to an operating voltage (i.e., a gate turn-on voltage), wherein the gate turn-on voltage of the high-voltage transistor type transistor is higher than the gate turn-on voltage of the low-voltage transistor type transistor, and the gate turn-on voltage of the low-voltage transistor type transistor is higher than the gate turn-on voltage of the ultra low-voltage transistor type transistor.
Specifically, the first well region 211C may be used to form a transistor of one transistor type (for example, a transistor of a high-voltage transistor type), and the second well region 211D may be used to form a transistor of another transistor type (for example, a transistor of a low-voltage transistor type).
It is understood that, for a transistor with a higher operating voltage (i.e., a higher gate-on voltage), the thicker the gate insulating layer 24A/24B is, the better the electrical characteristics parameters of the transistor device, such as saturation current, leakage current, etc., are improved, and thus the performance of the transistor is improved. Moreover, in the above embodiment, the smaller the gaps or pores existing inside the shallow trench isolation structure 23 for isolating the well region 211C/211D used by each transistor from the other well regions 211C/211D, the more beneficial the performance of each transistor in the above semiconductor device is.
The method for manufacturing a semiconductor device according to this embodiment forms a substrate, forms a trench on the substrate, fills the trench along the sidewall and the bottom surface of the trench to form a first filling layer, fills a part of the space in the trench with the first filling layer, removes a part of the first filling layer away from the sidewall and the bottom surface of the first filling layer to form a trimmed filling layer, fills the trimmed filling layer in the trench to form a second filling layer, and fills the trench, thereby solving the problem that the large trench is difficult to be completely filled with a filling material, which causes a large void inside the filler in the large trench, and further affects the performance of the semiconductor device, and reduces seams or voids inside the shallow trench isolation structure when the method for manufacturing a semiconductor device is applied to form a shallow trench isolation structure in an IC device, the breakdown resistance of the shallow trench isolation structure is improved, so that the electrical isolation effect of the shallow trench isolation structure can be improved, and the product quality is improved.
The semiconductor device manufactured according to the above method embodiment of the present invention may be as shown in fig. 12 or fig. 14, and the semiconductor device may include a substrate (i.e., the base 21 or the substrate 211 in the above method embodiment), and a filler 23 including a trim filling layer 230 and a second filling layer 232, wherein a trench (i.e., the trench 22 or the shallow trench 221 in the above method embodiment) is provided on the substrate, and the filler 23 fills the trench. In particular, the trim fill layer 230 may be located on the sidewalls and bottom surface of the trench, filling a portion of the space within the trench, with the opposing surfaces of the trim fill layer 230 facing away from the sidewalls of the trench being separated by a second fill layer 232.
In one embodiment, as shown in fig. 14, the substrate may be embodied as the substrate 211 in the method embodiment, the trench may be embodied as the shallow trench 221 in the method embodiment, and one end of the filler 23 may be filled in the trench and the other end may extend above the substrate.
In one embodiment, the filler 23 may be a shallow trench isolation structure 23. Specifically, as shown in fig. 14, the substrate may be the substrate 211 in the method embodiment, and, as shown in fig. 3, the substrate may include a plurality of well regions 211C/211D, and two adjacent well regions 211C/211D may be separated by the shallow trench isolation structure 23 to achieve electrical isolation.
In one embodiment, as shown in FIG. 3, the well region 211C/211D may include a source region 211C-1/211D-1, a channel region 211C-2/211D-2, and a drain region 211C-3/211D-3 connected in sequence. Also, as shown in fig. 14, the above-described semiconductor device may further include a gate insulating layer 24A/24B on the channel regions 211C-2/211D-2, and a gate layer 25A/25B on the gate insulating layer 24A/24B.
In the above embodiment, an acute included angle between the sidewall of the trench and a surface of the substrate having the trench (i.e., an upper surface of the substrate) is not smaller than a predetermined angle, that is, the angle of the trench is greater than or equal to the predetermined angle, wherein the predetermined angle ranges from 80 degrees to 90 degrees.
It should be noted that, in the present embodiment, reference may be made to the specific implementation described in the above method embodiments for each structure of the semiconductor device, and therefore, details are not described here again.
The semiconductor device provided by the embodiment is filled for multiple times, and before the next filling, a film layer formed by the previous filling is trimmed to open a sealed area and an area with a sealing trend in a groove, so that the residual space in the groove is easier to be completely filled by a filling material filled subsequently, and therefore, the gap or the gap inside a filling material filled in the groove is favorably eliminated or reduced.
Referring to fig. 15, fig. 15 is a schematic structural diagram of a memory according to an embodiment of the invention. As shown in fig. 15, the memory may include a memory array 100 and a peripheral device 200 electrically connected, wherein the peripheral device 200 may include the semiconductor device in any of the embodiments described above.
Specifically, the peripheral device 200 may include a substrate and a filler including a trim filling layer and a second filling layer, wherein a trench is disposed on the substrate, and the filler fills the trench. Specifically, the trim fill layer is located on the sidewalls and bottom surface of the trench, fills a portion of the space within the trench, and is separated by a second fill layer between opposing surfaces of the trim fill layer facing away from the sidewalls of the trench.
It should be noted that, in this embodiment, reference may be made to the specific implementation manner described in the foregoing semiconductor device embodiment for each structure of the peripheral device 200, and therefore, details are not described here again.
In the above embodiment, the memory array 100 may include: a plurality of memory cell strings 101 and a stacked structure 102 on the peripheral device 200, wherein each memory cell string 101 includes a channel layer and a memory function layer penetrating the stacked structure 102, and the memory function layer is located between the channel layer and the stacked structure. The stacked structure 102 may include a plurality of gate layers 1021 and electrically insulating layers 1022 alternately stacked in the longitudinal direction Z.
In some embodiments, the memory array 100 may further include an interconnect layer 104 disposed on a side of the stacked structure 102 facing the peripheral device 200, wherein the memory cell string 101 is electrically connected to the interconnect layer 104, and the interconnect layer 104 may be electrically connected to a gate layer of the peripheral device 200.
Specifically, the memory array 100 may further include an interlayer dielectric layer disposed between the stacked structure 102 and the interconnect layer 104, and a plurality of conductive contacts 103 formed in the interlayer dielectric layer. The plurality of conductive contacts 103 may include bit line contacts, which may extend in the longitudinal direction Z and have one end electrically connected to the memory cell strings 101 and the other end electrically connected to the interconnect layer 104.
It is understood that, in the present embodiment, reference may be made to the specific implementation of the memory array 100 in the prior art, and thus, the detailed description is omitted here.
In addition, although the example of the memory in this embodiment is a Wafer bonding (Wafer bonding) architecture in which the peripheral device and the memory array are bonded, in other embodiments, the memory may be a NAND architecture, for example, a peripheral circuit under array (PUC) architecture, a peripheral circuit near array (PNC) architecture, and the like, which is not specifically limited in this embodiment of the present invention.
Different from the prior art, the memory provided in this embodiment is configured to perform multiple filling, and before performing the next filling, trim the film layer formed by the previous filling to open the sealed region and the region with the sealing tendency in the trench, so that the remaining space in the trench is more easily filled completely by the subsequently filled filling material, thereby facilitating elimination or reduction of the gap or space inside the filling material filled in the trench, and when the filling material is used as a shallow trench isolation structure in an IC device, the electrical breakdown resistance of the shallow trench isolation structure can be enhanced, and further the electrical isolation effect of the shallow trench isolation structure on each discrete component in the IC device can be improved.
Accordingly, as shown in fig. 16, an embodiment of the present invention further provides a storage system 40, where the storage system 40 includes a controller 41 and a memory 42, and the controller 41 is coupled to the memory 42 and is configured to control the memory 42 to store data.
The memory 42 may be the same as the memory described in any of the above embodiments, and therefore, the description thereof is omitted here. The controller 41 may control the memory 42 through the channel CH, and the memory 42 may perform an operation based on the control of the controller 41 in response to a request from the host 50. The memory 42 may receive a command CMD and an address ADDR from the controller 41 through a channel CH and access a region selected from the memory cell array in response to the address. In other words, the memory 42 may perform an internal operation corresponding to the command on the area selected by the address.
In some embodiments, the storage system 40 may be implemented as a memory device such as a Universal Flash Storage (UFS) device, a Solid State Disk (SSD), a multi-media card in the form of an MMC, eMMC, RS-MMC, and micro-MMC, a secure digital card in the form of an SD, mini-SD, and micro-SD, a Personal Computer Memory Card International Association (PCMCIA) card type memory device, a Peripheral Component Interconnect (PCI) type memory device, a PCI express (PCI-E) type memory device, a Compact Flash (CF) card, a smart media card, or a memory stick, and so forth.
In particular, the storage system 40 may be used in a computer, a television, a set-top box, a vehicle, or other terminal product.
Different from the prior art, the storage system provided by this embodiment forms the filler in the trench by filling for multiple times and trimming the film layer formed by the previous filling between two adjacent fillings, so as to reduce the holes or gaps inside the filler, and when the filler is used as a shallow trench isolation structure in an IC device, the electrical breakdown resistance of the shallow trench isolation structure can be enhanced, and thus the electrical isolation effect of the shallow trench isolation structure on each discrete component in the IC device can be improved.
Accordingly, as shown in fig. 17, an embodiment of the present invention further provides an electronic device 60, where the electronic device 60 includes the storage system 61 provided in the embodiment of the present invention, and specifically, the electronic device 60 may be any device that can store data, such as a mobile phone, a desktop computer, a tablet computer, a notebook computer, a server, an in-vehicle device, a wearable device, and a mobile power supply.
The electronic device provided by the embodiment of the invention has the same beneficial effects as the storage system due to the arrangement of the storage system provided by the embodiment of the invention.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the present invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims (19)

1. A method for manufacturing a semiconductor device, comprising:
forming a substrate;
forming a trench on the substrate;
filling along the side wall and the bottom surface of the groove to form a first filling layer, wherein the first filling layer fills part of the space in the groove;
removing a portion of the first filling layer away from the sidewalls and the bottom surface to form a trimmed filling layer;
and filling the trimming filling layer in the groove to form a second filling layer.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the step of filling along the sidewall and the bottom surface of the trench to form the first filling layer specifically comprises:
a first deposition of a fill material is performed to deposit a first fill layer on the sidewalls and bottom surface of the trench.
3. The method for manufacturing a semiconductor device according to claim 2, wherein the step of filling the trimmed filling layer in the trench to form a second filling layer specifically comprises:
and performing second deposition of the filling material to deposit and form a second filling layer on the trimming filling layer in the groove.
4. A method for fabricating a semiconductor device according to claim 3, wherein the first deposition is performed by a chemical vapor deposition process and the second deposition is performed by an atomic layer deposition process.
5. The method for manufacturing the semiconductor device according to claim 1, wherein the step of removing the portion of the first filling layer away from the sidewalls and the bottom surface to form a trimmed filling layer comprises:
and etching the first filling layer along the direction towards the bottom surface to remove the part of the first filling layer far away from the side wall and the bottom surface to form a trimming filling layer.
6. The method for manufacturing a semiconductor device according to claim 1, wherein the step of forming the substrate specifically comprises:
providing a substrate;
forming a first insulating layer on the substrate;
forming a second insulating layer on the first insulating layer, wherein the trench penetrates through the second insulating layer and the first insulating layer and extends into the substrate;
the manufacturing method of the semiconductor device further comprises the following steps: and filling the trimming filling layer in the groove, and removing the second insulating layer after the step of forming a second filling layer.
7. The method as claimed in claim 6, wherein after the second filling layer is formed, the obtained filling material filled in the trench is a shallow trench isolation structure, the substrate includes a plurality of well regions, and two adjacent well regions are separated by the shallow trench isolation structure.
8. The method according to claim 7, wherein the well region comprises a source region, a channel region and a drain region connected in sequence, and after the step of removing the second insulating layer, the method further comprises:
forming a gate insulating layer on the channel region;
a gate electrode layer is formed on the gate insulating layer.
9. The method of manufacturing a semiconductor device according to claim 1, wherein an acute included angle between the side wall and the surface of the substrate on which the trench is formed is not smaller than a predetermined angle, and the predetermined angle ranges from 80 degrees to 90 degrees.
10. The method for manufacturing a semiconductor device according to claim 1, wherein a volume ratio of the partial space to the entire space in the trench is in a range of 0.7 to 0.8.
11. A semiconductor device, comprising:
the device comprises a substrate, a first electrode and a second electrode, wherein a groove is formed in the substrate;
a filler filling the trench and including a trim fill layer and a second fill layer;
wherein the trimming filling layer is positioned on the side wall and the bottom surface of the groove, fills part of the space in the groove, and the opposite surface of the trimming filling layer facing away from the side wall is separated by the second filling layer.
12. The semiconductor device of claim 11, wherein one end of the filler is filled in the trench and the other end extends above the substrate.
13. The semiconductor device of claim 12, wherein the filler is a shallow trench isolation structure.
14. The semiconductor device of claim 13, wherein the substrate comprises a plurality of well regions, and two adjacent well regions are separated by the shallow trench isolation structure.
15. The semiconductor device of claim 14, wherein the well region comprises a source region, a channel region, and a drain region connected in sequence, and the semiconductor device further comprises:
a gate insulating layer on the channel region;
and a gate electrode layer on the gate insulating layer.
16. The semiconductor device according to claim 11, wherein an acute included angle between the side wall and a surface of the substrate where the trench is provided is not smaller than a preset angle, and a value of the preset angle ranges from 80 degrees to 90 degrees.
17. A memory comprising a memory array and a peripheral device electrically connected, the peripheral device comprising the semiconductor device of any one of claims 11 to 16.
18. A memory system comprising the memory of claim 17 and a controller coupled to the memory and configured to control the memory to store data.
19. An electronic device characterized by comprising the storage system of claim 18.
CN202210167810.0A 2022-02-23 2022-02-23 Semiconductor device, manufacturing method thereof, memory, storage system and electronic equipment Pending CN114551332A (en)

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