CN115472621A

CN115472621A - Semiconductor device, manufacturing method thereof, memory and storage system

Info

Publication number: CN115472621A
Application number: CN202211124065.8A
Authority: CN
Inventors: 吴林春; 周文犀; 吴双双; 韩玉辉
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2022-09-15
Filing date: 2022-09-15
Publication date: 2022-12-13

Abstract

The invention discloses a semiconductor device and a preparation method thereof, a memory and a storage system, wherein the method comprises the steps of providing a substrate, forming a stacking layer on one side of the substrate in the longitudinal direction opposite to the transverse surface, wherein the stacking layer comprises a spacing lamination layer, the spacing lamination layer comprises a first stop layer and a second stop layer, the first stop layer comprises a first stop layer easy-oxidation area positioned in a first area and a first stop layer non-doping area positioned in a second area, and the first stop layer easy-oxidation area and the second stop layer are subjected to oxidation treatment in the side wall of a channel hole formed in the stacking layer of the first area, wherein the oxidation rate of the first stop layer easy-oxidation area is greater than that of the second stop layer, so that a protruding structure is formed in the position of the channel hole corresponding to the first stop layer when the bottom of the channel hole is subjected to oxidation treatment, the depth of the channel hole is reduced, the influence on the uniformity of the depth of the channel hole during etching of the bottom of the channel hole is avoided, and the process window of etching of the bottom of the channel hole is increased.

Description

Semiconductor device, manufacturing method thereof, memory and storage system

Technical Field

The present disclosure relates to the field of electronic device technologies, and in particular, to a semiconductor device, a method for manufacturing the semiconductor device, a memory, and a storage system.

Background

3D NAND (3D NAND FLASH MEMORY) is an emerging type of FLASH MEMORY that addresses the limitations imposed by 2D or planar NAND FLASH memories by stacking MEMORY grains together.

In the 3D NAND, a stacked memory structure is realized by vertically stacking a plurality of layers of data storage units. As the number of stacked layers increases, the control of etching the trench hole profile becomes more and more difficult.

In the prior art, the etching control precision of the channel hole profile is improved mainly through an etching process. However, since the selection of SiN (silicon nitride), OX (oxide) and Poly (polysilicon) is low, the uniformity of the via formed on the substrate of the memory structure is poor, and the related preparation process of the subsequent back side extraction structure is affected.

Disclosure of Invention

The invention aims to provide a semiconductor device, a manufacturing method thereof, a memory and a storage system, and aims to solve the problem that the uniformity of a punched hole formed on a substrate is poor due to an etching process.

In a first aspect, to achieve the above object, the present disclosure provides a method for manufacturing a semiconductor device, including:

providing a substrate having a lateral surface, the substrate comprising in the lateral direction portions located in a first region and a second region;

forming a stacking layer on one side of the substrate in a longitudinal direction opposite to the transverse surface, wherein the stacking layer comprises a spacing stacking layer and a first stacking structure, the spacing stacking layer comprises a first stopping layer and a second stopping layer, and the first stopping layer comprises a first stopping layer easy-oxidation area positioned in the first area and a first stopping layer non-doping area positioned in the second area;

forming a channel hole in the stack of layers in the first region that extends into the spacer stack;

and performing oxidation treatment on the first stop layer easy oxidation area and the second stop layer in the side wall of the channel hole, wherein the oxidation rate of the oxidation treatment on the first stop layer easy oxidation area is greater than that of the oxidation treatment on the second stop layer.

In some embodiments, the method for manufacturing a semiconductor device further includes:

forming a channel structure in the channel hole, and forming at least one of a dummy channel structure and a gate line isolation structure in the stacked layer in the second region; the channel structure comprises a channel layer, the channel layer is provided with a transverse bottom surface, and a second protruding structure is formed at the position where the second stopping layer and the channel structure meet, so that the inner diameter of the channel structure at the position corresponding to the second protruding structure is smaller than that of other positions;

removing the substrate and layers in the first region between the substrate and the second stop layer and in the second region between the substrate and the first stop layer undoped region and exposing the bottom surface of the channel layer, the second stop layer in the first region and the first stop layer undoped region in the second region;

forming a source region covering the bottom surface of the channel layer, the second stop layer in the first region, and the first stop layer non-doped region.

In some embodiments, the step of subjecting the first stop layer oxidation-susceptible region and the second stop layer to oxidation treatment within the sidewall of the channel hole further comprises:

and forming a first protruding structure protruding out of the channel hole at the intersection part of the first stop layer easy oxidation area and the channel hole, wherein the transverse length of the first protruding structure protruding out of the channel hole is greater than that of the second protruding structure protruding out of the channel hole.

In some embodiments, the step of forming the stack further comprises:

phosphorus doping the first stop layer oxidizable region, and

and carrying out carbon doping on the second stop layer.

In some embodiments, the step of forming the stack further comprises:

phosphorus doping the first stop layer oxidizable region, and

and performing ammonia gas surface treatment on the second stop layer.

In some embodiments, the first protrusion structure forms a slit in the longitudinal direction within the channel hole, and the step of forming a channel structure includes:

forming a storage function layer which is attached to the inner wall of the channel hole and completely fills the gap in the channel hole;

and sequentially forming the channel layer and the insulating layer on the storage function layer in the channel hole.

In some embodiments, the first protrusion structure closes the channel hole within the channel hole to form a channel hole bottom, and the forming a channel structure comprises:

and forming a storage function layer, the channel layer and an insulating layer in the channel hole and on the bottom of the channel hole.

and forming the other of the dummy channel structure and the gate line isolation structure in the second region, wherein the other of the dummy channel structure and the gate line isolation structure extends into the spacing lamination layer and the substrate longitudinally.

forming a step structure in the stacked layers of the second region;

forming a dielectric layer covering the step structure in the second area;

forming a contact hole which longitudinally penetrates through the dielectric layer and stops at the second stop layer; and

and depositing a conductive material in the contact hole to form a contact structure.

In some embodiments, after the step of forming the source region, the method for manufacturing a semiconductor device further includes:

forming an insulating structure on the bottom surface of the source region, which is far away from the stacked layers;

and forming a conductive structure connected with the contact structure and the source region respectively on the bottom surface of the insulating structure.

In a second aspect, to solve the same technical problem, the present disclosure provides a semiconductor device comprising:

a source region having a lateral bottom surface, the source region including portions in a first region and a second region in the lateral direction;

the stack structure is positioned above the source region and away from the bottom surface, the stack structure comprises a spacing lamination layer and a first stack structure, the spacing lamination layer comprises a second stop layer and a first stop layer positioned in the second region, and the second stop layer and the first stop layer positioned in the first region are in contact with the source region;

a channel structure located in the first stack structure of the first region and extending longitudinally to the source region, and the channel structure including a channel layer having a lateral bottom surface;

and a second protrusion structure is formed at a position where the second stop layer and the channel structure meet, so that the inner diameter of the channel structure at a position corresponding to the second protrusion structure is smaller than that of other positions.

In some embodiments, the semiconductor device further comprises:

at least one of a dummy channel structure and a gate line isolation structure in the first stack structure in the second region and extending longitudinally into the spacer stack.

In some embodiments, the first stop layer oxidizable region has a phosphorus doping and the second stop layer has a carbon doping.

In some embodiments, the first stop layer oxidation prone region has a phosphorous doping and the second stop layer has an ammonia composition.

In some embodiments, the semiconductor device further comprises:

the conductive structure is positioned at the bottom of the source region and is electrically connected with the source region;

and the insulation structure is positioned between the source region and the conductive structure and is provided with a through hole for connecting the conductive structure with the source region.

In some embodiments, the semiconductor device further comprises:

and the other of the dummy channel structure and the gate line isolation structure is positioned in the second region, and the dummy channel structure and the gate line isolation structure longitudinally penetrate through the second stop layer and extend into the source region.

In some embodiments, the semiconductor device further comprises:

a step structure located in the stack structure of the second region;

a dielectric layer covering the stack structure of the second region; and

and the contact structure longitudinally penetrates through the dielectric layer, extends to a position corresponding to the transverse surface of the second stop layer, and is connected with the conductive structure.

In some embodiments, the first stop layer and the second stop layer longitudinally correspond to the contact structure, and the source region is provided with a through-silicon-via through which the contact structure is connected to the conductive structure.

In a third aspect, the present disclosure provides a memory comprising:

a semiconductor device manufactured by the method for manufacturing a semiconductor device according to any one of the above embodiments, and a peripheral circuit electrically connected to the semiconductor device.

In a fourth aspect, the present disclosure provides a memory system comprising:

the memory of the third aspect, and a controller electrically connected to the memory for controlling an access operation of the memory.

The utility model provides a semiconductor device and preparation method, memory and storage system thereof, through carrying out oxidation treatment to first stop layer easy oxidation district and second stop layer in the lateral wall of trench hole, wherein, the oxidation rate of carrying out oxidation treatment to first stop layer easy oxidation district is greater than the oxidation rate that the second stop layer carries out oxidation treatment, thereby can realize that the trench hole forms protruding structure in the position department that corresponds with first stop layer in order to reduce the degree of depth of trench hole when carrying out oxidation treatment to trench hole bottom, avoid producing the influence to the homogeneity of trench hole deep punchhole when trench hole bottom etching, and then increased the technology window of trench hole bottom etching.

Drawings

Fig. 1 is a schematic flow chart of a method of manufacturing a semiconductor device provided by the present disclosure;

FIGS. 2a-2e are schematic structural diagrams of a semiconductor device provided by the present disclosure during fabrication;

fig. 3 is a schematic structural diagram of a semiconductor device provided by the present disclosure;

FIG. 4 is a schematic structural diagram of a memory provided by the present disclosure;

fig. 5 is a schematic structural diagram of a storage system provided by the present disclosure.

Detailed Description

The technical solutions in the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the present disclosure. It is to be understood that the embodiments described are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.

It will be understood that, although the terms first, second, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first component could be termed a second component, and, similarly, a second component could be termed a first component, without departing from the scope of the present disclosure.

It will be understood that when an element is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element or intervening elements may also be present. Other words used to describe the relationship between components should be interpreted in a similar manner.

As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. The layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far from the substrate. The layer may extend over the entire underlying or overlying structure or may have an extent less than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. The layers may extend horizontally, vertically and/or along a tapered surface. The substrate may be a layer, which may include one or more layers, and/or may have one or more layers above, and/or below it. The layer may comprise a plurality of layers. For example, the interconnect layers may include one or more conductive layers and contact layers (in which contacts, interconnect lines, and one or more dielectric layers are formed).

The cross-section of the semiconductor device in various directions is represented herein by a cartesian coordinate system (X, Y and Z), where the XY plane is parallel to the substrate and the Z direction is perpendicular to the substrate.

It should be noted that the drawings provided in the present disclosure are only for illustrating the basic idea of the present disclosure, and although the drawings only show the components related to the present disclosure and are not drawn according to the number, shape and size of the components in actual implementation, the type, amount and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.

The semiconductor device in the present disclosure may be applied to a wafer or a three-dimensional memory. The three-dimensional memory can be applied to communication products, consumer electronics products, automobile products, aerospace products, artificial intelligence products, big data and the like. Among them, the consumer electronics products include, but are not limited to, mobile phones, computers, tablets, cameras, smart glasses, or game products.

In the related art, as the number of layers of the 3D NAND increases, the control of etching of the channel hole profile becomes more and more difficult. In order to improve the accuracy of etching control of the profile of the channel hole, in the related art, a low-temperature etching process is used to etch the memory structure. However, due to the fact that the low-temperature etching process has low selection ratio of SiN (silicon nitride), OX (oxide) and Poly (polysilicon), the uniformity of the gouges formed on the 3D NAND substrate is poor, and therefore the related preparation process of the subsequent back extraction structure is affected.

In order to solve the problem that the uniformity of the via holes formed on the 3D NAND substrate is poor due to the low-temperature etching process, please refer to fig. 1 and fig. 2a-2e, where fig. 1 is a schematic flow diagram of a manufacturing method of the semiconductor device provided by the present disclosure, and fig. 2a-2e are schematic structural diagrams of the semiconductor device provided by the present disclosure in a manufacturing process. It should be noted that fig. 2a-2e only show exemplary structures of the present disclosure, and the semiconductor device provided by the present disclosure may further include other components and/or structures for realizing the complete functions of the device.

Specifically, the method for manufacturing a semiconductor device according to the embodiment of the present disclosure includes steps 101 to 104.

Please refer to step 101 in fig. 1 and fig. 2a.

Step 101, providing a substrate 11, wherein the substrate 11 has a lateral surface, and the substrate 11 includes portions located in a first region M1 and a second region M2 in the lateral direction.

In the illustrated embodiment of the present disclosure, the substrate 11 may be a semiconductor substrate, and for example, may be a Silicon (Si), germanium (Ge), siGe substrate, silicon On Insulator (SOI), germanium On Insulator (GOI), or the like. The substrate 11 may be a substrate including other element semiconductors or compound semiconductors, or may have a stacked-layer structure such as Si/SiGe or the like.

As shown in fig. 2a, the Y direction is a lateral direction of the substrate 11, and a plane formed by the X direction and the Y direction is a lateral surface of the substrate 11.

It should be noted that, since the subsequent gate line gap is formed in the second region M2 and near the first region M1, and the gate line gap is disposed parallel to the X direction, in order to better illustrate the specific manufacturing method of the semiconductor device provided in this embodiment, the drawings of the left part of fig. 2 b-2 e are shown in the YZ direction, and the drawings of the right part are shown in the XZ direction in this embodiment.

Please refer to step 102 in fig. 1 and fig. 2b.

Step 102, forming a stacked layer 12 on one side of the substrate 11 in a longitudinal direction opposite to the lateral surface, where the stacked layer 12 includes a spacer stack 122 and a first stacked structure 121, the spacer stack 122 includes a first stop layer 1221 and a second stop layer 1222, and the first stop layer 1221 includes a first stop layer easy oxidation region M11 located in the first region M1 and a first stop layer non-doped region M21 located in the second region M2.

Wherein the stacked layer 12 includes, in the longitudinal direction, i.e., the Z direction, a first stacked structure 121 alternately stacked by sacrificial layers and interlayer insulating layers, and a spacer stack 122 alternately stacked by stop layers and spacer layers. The stacked layer 12 includes a first region M1 and a second region M2 in order in the lateral direction, i.e., the X direction. In the present disclosure, the process for preparing the stacked layer 12 of the semiconductor device provided by the present disclosure is: first, a stacked layer 12 including alternately stacked sacrificial layers and interlayer insulating layers, the number of which is controllable, may be formed on a substrate 11 through a deposition process, such as forming a desired number of sacrificial layers and interlayer insulating layers by adjusting parameters of the deposition process. Among them, an interlayer insulating layer is used to separate a plurality of sacrificial layers, and the material of the interlayer insulating layer may be composed of an oxide such as silicon oxide (SiO 2), and the material of the sacrificial layer may be composed of a nitride such as silicon nitride (SiN). Since the material of the sacrificial layer is mostly nitride, it is advantageous to simultaneously form the stacked layers 12 of the plurality of sacrificial layers and the plurality of interlayer insulating layers, which are alternately stacked, and thus, the stacked layers 12 including the sacrificial layers and the interlayer insulating layers, which are alternately stacked in a direction perpendicular to the lateral surface of the substrate 11, may be formed through a deposition process.

Through the first stop layer 1221 including the first stop layer easily-oxidized region M11 located in the first region M1 and the first stop layer non-doped region M21 located in the second region M2, the first stop layer 1221 located in the first stop layer non-doped region M21 of the second region M2 is not oxidized or slightly oxidized during subsequent oxidation treatment, so that the problem of obvious thickening is not caused sufficiently, and the tilting problem caused by the oxidized stop layer is effectively avoided.

In one embodiment, the step of forming the stack layer 12 specifically includes: the first stop layer easy oxidation region M11 is phosphorus doped, and the second stop layer 1222 is carbon doped. In another embodiment, the step of forming the stack layer 12 specifically further includes: the first stopper layer easily-oxidized region M11 is doped with phosphorus, and the second stopper layer 1222 is subjected to ammonia surface treatment. Specifically, it is not disclosed that the second stopper layer 1222 is primarily surface-treated with ammonia gas, and the first stopper layer easily-oxidized region M11 is not surface-treated.

In the present disclosure, the first stopper layer easily-oxidizable region M11 is doped with phosphorus, and the second stopper layer 1222 is doped with carbon or treated with ammonia, whereby an oxidation reaction of the surface of the second stopper layer 1222 can be suppressed during the oxidation treatment, and it can be ensured that at least when the first stopper layer easily-oxidizable region M11 is completely oxidized, a part of the second stopper layer 1222 is not oxidized. In addition, only the first stop layer easily-oxidized region M11 is doped, and the first stop layer non-doped region M21 is not doped, so that the doping modes of the first stop layer easily-oxidized region M11 and the first stop layer non-doped region M21 are different, and thus the oxidation rate of the first stop layer easily-oxidized region M11 during oxidation treatment is greater than that of the first stop layer non-doped region M21 during oxidation treatment, and further the first stop layer 1221 at the first stop layer easily-oxidized region M11 is completely oxidized during subsequent oxidation treatment, so that no first stop layer 1221 remains near the gate line isolation groove at the first region M1, and the first stop layer 1221 at the first stop layer non-doped region M21 is not oxidized, thereby avoiding the tilting problem caused by the oxide appearing near the gate line isolation groove at the second region M2.

In one case, the second stopper layer 1222 may be surface-treated with ammonia gas after the second stopper layer 1222 is carbon-doped. In other cases, the second stop layer 1222 may be surface-treated with ammonia gas before the second stop layer 1222 is carbon-doped. The specific processing method is not particularly limited, and may be any method that can make the oxidation rate of the first stop layer easily oxidized region M11 greater than the oxidation rate of the first stop layer non-doped region M21.

Please refer to step 103, step 104 in fig. 1 and fig. 2c-2d.

Step 103, forming a channel hole 123 extending into the spacer stack 122 in the stack 12 of the first region M1.

In step 104, the first stopper layer easy-oxidation region M11 and the second stopper layer 1222 are subjected to oxidation treatment in the sidewall of the channel hole 123, wherein an oxidation rate of the first stopper layer easy-oxidation region M11 is higher than an oxidation rate of the second stopper layer 1222.

It should be noted that, because the oxidation treatment of the first stop layer easy oxidation region M11 is performed through the inner wall of the channel hole 123, and the oxidation treatment of part of the first stop layer 1221 can cause the edge of the first stop layer 1221 close to the side of the channel hole 123 to generate an expansion phenomenon, therefore, when the oxidation treatment of the first stop layer easy oxidation region M11 is performed through the inner wall of the channel hole 123, the edge of the first stop layer easy oxidation region M11 close to the side of the channel hole 123 can cause the expansion phenomenon when performing the oxidation reaction, which causes the oxide corresponding to the first stop layer 1221 close to the gate line isolation trench to generate an obvious thickening and a tilting problem. Therefore, in this embodiment, the oxidation rate of the first stop layer easy oxidation region M11 during the oxidation process is greater than the oxidation rate of the second stop layer 1222 during the oxidation process, so that when the first stop layer easy oxidation region M11 is subjected to the oxidation process through the inner wall of the channel hole 123, the purpose of oxidizing all the first stop layer easy oxidation region M11 can be achieved, and the tilt-up problem is effectively avoided.

In some embodiments, the method for manufacturing a semiconductor device further includes: forming a channel structure 1231 extending into the spacer stack 122 in the stacked layer 12 in the first region M1, and forming at least one of a dummy channel structure and a gate line isolation structure 125 in the stacked layer 12 in the second region M2; the channel structure 1231 includes a channel layer 12312, the channel layer 12312 has a lateral bottom surface 12314, and a second bump structure 1222 'is formed at a portion where the second stopper layer 1222 meets the channel structure 1231 such that an inner diameter of the channel structure 1231 at a portion corresponding to the second bump structure 1222' is smaller than inner diameters of other portions.

Wherein the step of forming a channel hole 123 extending into the spacer stack 122 in the stack of layers 12 of the first region M1 further comprises: a first bump structure 1221 ' protruding out of the channel hole 123 is formed at a position where the first stop layer easy oxidation region M11 meets the channel hole 123, and a lateral length of the first bump structure 1221 ' protruding out of the channel hole 123 is greater than a lateral length of the second bump structure 1222 ' protruding out of the channel hole 123.

The inner wall of the trench hole 123 may be sequentially filled with one or more filling materials through a deposition process, so as to form the trench structure 1231, where the filling material may be an insulating material or a conductive material.

This embodiment can control parameters of the oxidation reaction, such as the reaction time, to form the protruding structures with controllable thickness and length, so that the length of the second protruding structures 1222 'in the lateral direction is smaller than the length of the first protruding structures 1221' in the lateral direction, thereby achieving smooth stopping of the second protruding structures 1222 'at the positions of the first protruding structures 1221' during the filling process of the channel holes 123, such as filling polysilicon.

In one embodiment, with continued reference to fig. 2c, the first protruding structures 1221' form slits (not shown) in the channel holes 123 in the longitudinal direction, and the step of forming the channel structures 1231 includes: forming a memory function layer 12311 attached to an inner wall of the channel hole 123 and completely filling the gap in the channel hole 123; the channel layer 12312 and the insulating layer 12313 are sequentially formed on the memory function layer 12311 within the channel hole 123.

In another embodiment, the first protruding structure 1221' closes the channel hole 123 in the channel hole 123 to form a bottom of the channel hole (not shown), and the step of forming the channel structure 1231 includes: a memory function layer 12311, the channel layer 12312, and an insulating layer 12313 are formed in the channel hole 123 and on the bottom of the channel hole.

By directly and sequentially forming the storage function layer 12311, the channel layer 12312 and the insulating layer 12313 in the channel hole 123 above the first protruding structure 1221', the storage function layer 12311 can be prevented from being formed in the channel hole 123 below the first stop layer 1221, so that the material required for depositing the storage function layer 12311 below the first stop layer 1221 is reduced, the time required for forming the channel structure 1231 is reduced, the process flow is simplified, and the production cost is greatly reduced.

In other embodiments, the method for manufacturing a semiconductor device further includes: the other of the dummy channel structure and the gate line isolation structure 125 longitudinally extending into the spacer stack 122 and the substrate 11 is formed in the second region M2.

Specifically, the specific process of forming the gate line isolation structure 125 is as follows: before forming the gate line isolation structure 125, the stacked layer 12 needs to be etched to form a gate line isolation trench (not shown in the figure) that penetrates through the stacked layer 12 and extends into the substrate 11, because the number of stacked layers 12 is very large, a deposition process needs to be adopted to form sacrificial layers and interlayer insulating layers that are stacked alternately at one time, then the sacrificial layers are removed by a wet etching process, and finally, a gate layer is formed at the position of the original sacrificial layers, so that the stacked layer 12 including the gate layer and the interlayer insulating layers that are stacked alternately is formed. The gate line isolation groove is filled after the replacement process, so that the gate line isolation structure 125 can be obtained.

The specific process for forming the pseudo channel structure comprises the following steps: forming a dummy channel hole 124 longitudinally penetrating the stacked layer 12 in the second region M2; the dummy channel hole 124 is filled to form a dummy channel structure.

With continued reference to fig. 2c, as an alternative embodiment, the method for manufacturing a semiconductor device further includes: forming a step structure in the stacked layer 12 of the second region M2; forming a dielectric layer 1211 covering the step structure in the second region M2; forming a contact hole (not shown) longitudinally penetrating the dielectric layer 1211 and stopping on the second stop layer 1222; and depositing a conductive material in the contact hole to form a contact structure 126. The dielectric layer 1211 may include an insulating material such as silicon oxide.

It should be noted that, by etching the stacked layer 12, the etched stacked layer 12 may include the first region M1 and the second region M2. The second region M2 includes step regions in which the length of each step in a direction parallel to the lateral surface of the substrate 11 decreases in order from the direction close to the substrate 11 toward the direction away from the substrate 11. The second region M2 may be located around the first region M1 or in the middle of the first region M1. The second region M2 provided in this embodiment generally refers to the region outside the first region M1, which includes a step structure (not shown) and a region where no step structure is formed, wherein the region where no step structure is formed includes a non-step structure space surrounded by the step structure in the second region M2 and a non-step structure space outside the step structure.

Please refer to fig. 2d-2e.

The preparation method of the semiconductor device further comprises the following steps: removing the substrate 11 and the layers in the first region M1 between the substrate 11 and the second stop layer 1222 and in the second region M2 between the substrate 11 and the first stop layer non-doped region M21, and exposing the bottom surface 12314 of the channel layer 12312, the second stop layer 1222 in the first region M1, and the first stop layer non-doped region M21 in the second region M2; forming a source region 13, wherein the source region 13 covers the bottom surface 12314 of the channel layer 12312, the second stop layer 1222 in the first region M1, and the first stop layer non-doped region M21.

The substrate 11 may be removed by wet etching or dry etching, for example, by using a chemical solution with a certain selection ratio, the etching rate of the chemical solution to the substrate 11 is high, and the etching rate to other film layers is low, so that when the substrate 11 is removed, the other film layers are not damaged substantially, and thus the substrate 11 is removed. Subsequently, wet etching may be used to remove portions of the memory function layer 12311 at the bottom of the channel structure 1231, and the layers in the first region M1 between the substrate 11 and the second stop layer 1222, and in the second region M2 between the substrate 11 and the first stop layer undoped region M21, so as to expose the channel layer 12312 at the end of the channel structure 1231, and particularly, include the bottom surface 12314 of the channel layer 12312, the end side surface adjacent to the bottom surface 12314, the second stop layer 1222 in the first region M1, and the first stop layer undoped region M21 in the second region M2.

The source region 13 may be formed by depositing one or more polysilicon layers on the bottom of the stack layer 12, i.e., on the original substrate 11, and then performing ion implantation on the polysilicon layers. The source region 13 is used to provide carriers, which may be electrons or holes, to the semiconductor device. The channel layer 12312 is used to provide a path for the movement of carriers between the source region 13 and the memory function layer 12311, and therefore the material of the channel layer 12312 needs to be a conductive material, such as polysilicon. Among them, the storage function layer 12311 generally includes a tunneling layer, a charge trap layer, and a blocking layer. By removing the substrate 11, a portion of the memory function layer 12311 at the end of the channel structure 1231 is removed to expose the channel layer 12312 at the end of the channel structure 1231, and the source region 13 covers the channel structure 1231 and the bottom of the gate line isolation structure 125, so that the source region 13 is directly in contact with the channel layer 12312 of the channel structure 1231, thereby realizing that the carriers in the source region 13 can move freely in the channel layer 12312.

In some embodiments, as shown in fig. 2e, after the step of forming the source region 13, the method for manufacturing a semiconductor device specifically further includes: forming an insulating structure 14 on a bottom surface of the source region 13 facing away from the stacked layer 12; conductive structures 15 (PAD) respectively connected with the contact structures 126 and the source regions 13 are formed on the bottom surface of the insulating structure 14.

In particular, the insulating structure 14 is located between the source region 13 and the conductive structure 15, and is provided with a via (not shown in the figure) for connecting the conductive structure 15 and the source region 13.

In this embodiment, after forming the source region 13, a deposition process is performed on the bottom of the source region 13, specifically, by depositing an insulating material such as silicon oxide to form a bottom insulating layer (not shown) on the bottom of the source region 13, and then by etching the bottom insulating layer to form a via longitudinally leading to the bottom of the contact structure 126 and the source region 13, so that the insulating structure 14 shown in fig. 2e can be obtained. Thereafter, a conductive material is deposited on the bottom of the insulating structure 14, thereby forming a conductive structure 15 connected to the bottom of the contact structure 126, the source region 13, through the via.

Referring to fig. 3, fig. 3 is a schematic structural diagram of a semiconductor device according to the present disclosure, and as shown in fig. 3, the semiconductor device according to the present disclosure includes: a source region 23, the source region 23 having a lateral bottom surface, the source region 23 including portions located in a first region M1 and a second region M2 in the lateral direction; a stack structure 22 located above the source region 23 facing away from the bottom surface, the stack structure 22 including a spacer stack 222 and a first stack structure 221, the spacer stack 222 including a second stop layer 2222 and a first stop layer 2221 located in a second region M2, and the second stop layer 2222 and the first stop layer 2221 located in the first region M1 being in contact with the source region 23; a channel structure 2231 located in the first stack structure 221 of the first region M1 and extending longitudinally to the source region 23, and the channel structure 2231 includes a channel layer 22312, the channel layer 22312 having a lateral bottom surface 22314.

The channel structure 2231 is formed in the channel hole 223, and the channel structure 2231 further includes a storage functional layer 22311 and an insulating layer 22313, a second protruding structure 2222 'is formed at a position where the second stop layer 2222 meets the channel structure 2231, so that an inner diameter of the channel structure 2231 at a position corresponding to the second protruding structure 2222' is smaller than inner diameters of other positions.

In this embodiment, the source region 23 covers the bottom surface 22314 of the channel layer 22312, so that the source region 23 is in direct contact with the channel layer 22312 of the channel structure 2231, thereby enabling carriers in the source region 23 to move freely in the channel layer 22312.

In this embodiment, the second stop layer 2222 has carbon doping. In another embodiment, the second stop layer 2222 has an ammonia component. In other embodiments, the second stop layer 2222 may also have both carbon doping and ammonia components. Since the second stop layer 2222 has carbon doping and/or an ammonia component, the oxidation rate of the second stop layer 2222 when subjected to oxidation treatment is slowed down.

For a way of making the second stop layer 2222 have carbon doping and/or ammonia component, please refer to the above method embodiments, which will not be described herein again.

In this embodiment, since the second stop layer 2222 has carbon doping and/or ammonia components, the oxidation rate of the second stop layer 2222 is slower than the oxidation rate of the first stop layer 2221 originally in the first region M1, so that it can be avoided that the Bottom Select Gate (Bottom Select Gate) of the semiconductor device provided by this embodiment is significantly thickened (i.e., a lift-off problem occurs), so that a gap is formed in the Gate layer, and thus the risk of F attach exists.

With continued reference to fig. 3, the semiconductor device provided in this embodiment further includes: at least one of a dummy channel structure (formed after filling the dummy channel hole 224) and a gate line isolation structure 225 located in the first stack structure 221 of the second region M2 and extending longitudinally into the spacer stack 222, a conductive structure 25, an insulating structure 24, the other of the dummy channel structure and the gate line isolation structure 225, a step structure, a dielectric layer 2211, and a contact structure 226.

Specifically, the conductive structure 25 is located at the bottom of the source region 23 and is electrically connected to the source region 23. The insulating structure 24 is located between the source region 23 and the conducting structure 25, and is provided with a via (not shown in the figure) for connecting the conducting structure 25 with the source region 23. The other of the at least one of the dummy channel structure and the gate line isolation structure 225 is located in the second region M2, and the dummy channel structure and the gate line isolation structure 225 longitudinally penetrate the second stop layer 2222 and extend into the source region 23. The step structure (not shown) is located in the stack structure 22 of the second region M2. The dielectric layer 2211 covers the stack structure 22 of the second region M2. The contact structure 226 longitudinally penetrates through the dielectric layer 2211, extends to a position corresponding to the transverse surface of the stop layer 2222, and is connected to the conductive structure 25.

Specifically, the first stop layer 2221 and the second stop layer 2222 corresponding to the contact structure 226 in the longitudinal direction, and the source region 23 are provided with a through silicon via (not shown), through which the contact structure 226 is connected to the conductive structure 25.

In this embodiment, the source region 23 is provided with through-silicon vias longitudinally corresponding to the contact structure 226 and the source region 23, while the insulating structure 24 forms a via for connecting the conductive structure 25 with the contact structure 226 and the source region 23.

Referring to fig. 4, fig. 4 is a schematic structural diagram of a memory provided by the present disclosure. The memory 200 may be a three-dimensional memory, such as a 3D NAND, 3D NOR memory.

The memory 200 includes a semiconductor device 201 and a peripheral circuit 202, the semiconductor device 201 may be a semiconductor device manufactured by the manufacturing method of any one of the semiconductor devices in the above embodiments, and the peripheral circuit 202 may be cmos (complementary metal oxide semiconductor). The semiconductor device 201 may be stacked with the peripheral circuit 202 or may be offset from the peripheral circuit 202, which is not limited in the present application. The peripheral circuit 202 is electrically connected to the semiconductor device 201 to transmit signals with the semiconductor device 201. The peripheral circuit 202 may be used for logic operation and controlling and detecting the switching state of each memory cell in the semiconductor device 201 through a metal wire, so as to implement data storage and data reading.

Wherein the semiconductor device 201 comprises a source region having a lateral bottom surface, the source region comprising in the lateral direction a portion located at a first region and a second region; a stack structure located above the source region facing away from the bottom surface, the stack structure including a spacer stack and a first stack structure, the spacer stack including a first stop layer and a second stop layer, and the first stop layer including a first stop layer non-doped region located in the second region; a channel structure located in the first stack structure of the first region and extending longitudinally to the source region, and the channel structure including a channel layer having a lateral bottom surface; and at least one of a dummy channel structure and a gate line isolation structure located in the first stack structure of the second region and extending longitudinally into the spacer stack; a second protrusion structure is formed at a position where the second stop layer and the channel structure meet, so that the inner diameter of the channel structure at a position corresponding to the second protrusion structure is smaller than the inner diameters of other positions, and the source region covers the bottom surface of the channel layer, the second stop layer in the first region, and the non-doped region of the first stop layer.

Referring to fig. 5, fig. 5 is a schematic structural diagram of a memory system provided in the present disclosure. The memory system 300 includes a memory 301 and a controller 302, the memory 301 may be the memory in any of the above embodiments, the memory 301 may include any one of the semiconductor devices in the above embodiments, the controller 302 is electrically connected to the memory 301 for controlling the memory 301 to store data, and the memory 301 may perform an operation of storing data based on the control of the controller 302.

In some embodiments, the storage system may be implemented as a device such as a Universal Flash Storage (UFS) device, a Solid State Disk (SSD), a multi-media card in the form of an MMC, eMMC, RS-MMC, and micro-MMC, a secure digital card in the form of an SD, mini-SD, and micro-SD, a Personal Computer Memory Card International Association (PCMCIA) card type storage device, a Peripheral Component Interconnect (PCI) type storage device, a PCI express (PCI-E) type storage device, a Compact Flash (CF) card, a smart media card, or a memory stick, etc.

The semiconductor device in the memory 301 includes a source region having a lateral bottom surface, the source region including portions in a first region and a second region in the lateral direction; a stack structure located above the source region facing away from the bottom surface, the stack structure including a spacer stack and a first stack structure, the spacer stack including a first stop layer and a second stop layer, and the first stop layer including a first stop layer undoped region located in the second region; a channel structure located in the first stack structure of the first region and extending longitudinally to the source region, and the channel structure including a channel layer having a lateral bottom surface; and at least one of a dummy channel structure and a gate line isolation structure located in the first stack structure of the second region and extending longitudinally into the spacer stack; a second protrusion structure is formed at a position where the second stop layer meets the channel structure, so that an inner diameter of the channel structure at a position corresponding to the second protrusion structure is smaller than inner diameters of other positions, and the source region covers the bottom surface of the channel layer, the second stop layer in the first region, and the first stop layer non-doped region.

The above description of the embodiments is only for helping understanding the technical solutions of the present disclosure and the core ideas thereof; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present disclosure.

Claims

1. A method of manufacturing a semiconductor device, comprising:

forming a stacked layer on one side of the substrate in a longitudinal direction opposite to the transverse surface, wherein the stacked layer comprises a spacing stacked layer and a first stacked structure, the spacing stacked layer comprises a first stop layer and a second stop layer, and the first stop layer comprises a first stop layer oxidation-prone area located in the first area and a first stop layer non-doped area located in the second area;

2. The method for manufacturing a semiconductor device according to claim 1, further comprising:

3. The method for manufacturing a semiconductor device according to claim 2, wherein the step of subjecting the first stop layer easily-oxidized region and the second stop layer to oxidation treatment in the sidewall of the channel hole further comprises:

4. The method for manufacturing a semiconductor device according to claim 1, wherein the step of forming the stack layer further comprises:

phosphorus doping the first stop layer oxidizable region, and

and carrying out carbon doping on the second stop layer.

5. The method for manufacturing a semiconductor device according to claim 1, wherein the step of forming the stack layer further comprises:

phosphorus doping the first stop layer oxidizable region, and

and performing ammonia gas surface treatment on the second stop layer.

6. The method for manufacturing a semiconductor device according to claim 3, wherein the first bump structure forms a slit in the longitudinal direction in the channel hole, and the step of forming the channel structure includes:

7. The method of manufacturing a semiconductor device according to claim 3, wherein the first bump structure closes the channel hole in the channel hole to form a bottom of the channel hole, and the step of forming the channel structure includes:

8. The method for manufacturing a semiconductor device according to claim 2, further comprising:

9. The method for manufacturing a semiconductor device according to claim 2, further comprising:

forming a step structure in the stacked layers of the second region;

forming a dielectric layer covering the step structure in the second area;

10. The method for manufacturing a semiconductor device according to claim 9, wherein after the step of forming a source region, the method for manufacturing a semiconductor device further comprises:

11. A semiconductor device, characterized in that the semiconductor device comprises:

the stack structure is positioned above the source region and departs from the bottom surface, the stack structure comprises a spacing lamination layer and a first stack structure, the spacing lamination layer comprises a second stopping layer and a first stopping layer positioned in the second region, and the second stopping layer and the first stopping layer positioned in the first region are in contact with the source region;

and a second protrusion structure is formed at a position where the second stop layer and the channel structure meet, so that the inner diameter of the channel structure at a position corresponding to the second protrusion structure is smaller than the inner diameter of other positions.

12. The semiconductor device according to claim 11, further comprising:

13. The semiconductor device of claim 11, in which the second stop layer has carbon doping.

14. The semiconductor device according to claim 11, wherein the second stop layer has an ammonia component.

15. The semiconductor device according to claim 11, further comprising:

16. The semiconductor device according to claim 12, further comprising:

and the other one of the dummy channel structure and the grid line isolation structure is positioned in the second region, and the dummy channel structure and the grid line isolation structure longitudinally penetrate through the second stop layer and extend into the source region.

17. The semiconductor device according to claim 15, further comprising:

a step structure located in the stack structure of the second region;

a dielectric layer covering the stack structure of the second region; and

18. The semiconductor device of claim 17, wherein the first stop layer and the second stop layer longitudinally correspond to the contact structure, and the source region is provided with a through-silicon-via through which the contact structure is connected to the conductive structure.

19. A memory, comprising: a semiconductor device produced by the method for producing a semiconductor device according to any one of claims 1 to 10, and a peripheral circuit electrically connected to the semiconductor device.

20. A storage system, comprising:

the memory of claim 19, and

a controller electrically connected with the memory for controlling access operations of the memory.