CN115411044A - Flash memory device and method of manufacturing the same - Google Patents

Abstract

The present invention provides a flash memory device and a method of manufacturing the same, wherein the flash memory device includes: a substrate including a first region and a second region; word lines extending along straight lines in the first region; the floating gate and the control gate are sequentially stacked on the surfaces of the first region and the second region and are positioned on two sides of the word line, wherein in the second region, part of the surface of the control gate is provided with an electric connector. According to the invention, the word line is arranged in the first region, and the electric connecting piece is arranged on part of the surface of the control gate in the second region, so that the distance between the word line and the electric connecting piece is increased, the connection difficulty of the control gate is reduced, and the short circuit risk of the flash memory device is reduced. Meanwhile, the word line and the grid structure extend along a straight line, so that the process window of a subsequent photoetching process is enlarged, and the size reduction of the flash memory device is facilitated.

Description

Flash memory device and method of manufacturing the same

Technical Field

The present invention relates to the field of integrated circuit manufacturing technologies, and in particular, to a flash memory device and a method for manufacturing the same.

Background

The flash memory device is used as a nonvolatile memory, has the characteristics of convenience, high storage density, strong reliability and the like, and is widely applied. The structure of the existing flash memory device generally includes a split gate structure, a stacked gate structure or a combination thereof, wherein the split gate flash memory device has the characteristic of high programming efficiency.

As the state of the art of integrated circuit fabrication continues to advance, the size of flash memory devices continues to shrink. However, referring to fig. 1, in the flash memory device, a header region X1 is smaller than a device cell region X2 (only a portion of the device cell region X2 is shown in fig. 1), and in the process of forming a patterned hard mask layer (not shown in the figure) using the first photoresist layer 1 as a mask, as the size of the flash memory device is reduced, a minimum distance a between individual patterns of the first photoresist layer 1 is reduced, which reduces a photolithography process space of the flash memory device, so that the hard mask layer (not shown in the figure) formed in the header region X1 is easily broken at a location b. Referring to fig. 2, in the process of forming a floating gate (not shown) and a control gate (not shown) by etching using the second photoresist layer 2 as a mask, as the size of the flash memory device is reduced, the area of the second photoresist layer 2 is correspondingly reduced, and the second photoresist layer 2 covers the word line 3 and the control gate layer 4 at the same time, so that the second photoresist layer 2 is prone to generate floating under the action of stress. In addition, the reduction in size of the flash memory device enables the distance between the word line 3 and the contact hole 5 formed subsequently to be correspondingly reduced, increasing the risk of short circuit of the flash memory device.

Disclosure of Invention

The invention aims to provide a flash memory device and a manufacturing method thereof, which reduce the connection difficulty of a control gate and reduce the short circuit risk of the flash memory device.

In order to achieve the above object, the present invention provides a flash memory device comprising:

a substrate including a first region and a second region;

word lines extending along straight lines in the first region;

the floating gate and the control gate are sequentially stacked on the surfaces of the first region and the second region and positioned on two sides of the word line, wherein in the second region, part of the surface of the control gate is provided with an electric connector.

Optionally, a plurality of isolation trenches are disposed in the substrate at intervals, an extending direction of the isolation trenches is perpendicular to an extending direction of the word lines, and the floating gates are disposed on the surface of the substrate between the isolation trenches.

Optionally, the flash memory device includes a device cell region and a header region adjacent to the device cell region, the first region and the second region are both located in the header region, and an intersection line of the first region and the second region is parallel to an intersection line of the device cell region and the header region.

Optionally, a first side wall is further disposed on the surface of the control gate, in the first region, a second side wall is disposed on the first side wall and a side wall of the control gate close to the word line, and in the second region, a second side wall is disposed on a side wall of the control gate close to the word line.

Optionally, the second side wall and the side wall of the floating gate close to the word line are provided with a third side wall, and the first side wall, the control gate and the side wall of the floating gate different from the word line are provided with a fourth side wall.

Correspondingly, the invention also provides a manufacturing method of the flash memory device, which comprises the following steps:

providing a substrate, wherein the substrate comprises a first region and a second region, word lines extending along straight lines and floating gates and control gates which are stacked in sequence and are arranged on two sides of the word lines are formed on the surfaces of the first region and the second region;

removing the word lines in the second region; and the number of the first and second groups,

forming electrical connections at a surface of the control gate of the second region.

Optionally, the process of forming the word line, the floating gate and the control gate includes:

sequentially forming a floating gate layer, a control gate layer and a hard mask layer on the surface of the substrate, wherein an opening for exposing the control gate layer is formed on the hard mask layer;

forming a first side wall on the side wall of the opening, and etching the control gate layer by taking the hard mask layer and the first side wall as masks so as to enable the opening to expose the floating gate layer;

forming a second side wall on the side wall of the opening, and etching the floating gate layer by taking the hard mask layer and the second side wall as masks so as to expose the substrate from the opening;

forming third side walls on the side walls and the bottoms of the openings, and forming the word lines in the openings; and the number of the first and second groups,

and removing the hard mask layer and the control gate layer and the floating gate layer below the hard mask layer to form the control gate and the floating gate.

Optionally, after forming the word line, the floating gate, and the control gate, before removing the word line in the second region, the method further includes:

and forming a fourth side wall on one side of the control gate and the floating gate, which is different from the word line.

Optionally, the process of removing the word line in the second region includes:

forming a photoresist layer covering the substrate, the fourth side wall and the word line in the first region;

etching the word line by using the photoresist layer and the fourth side wall as masks to remove the word line in the second region, and simultaneously etching part of the first side wall, the third side wall and the fourth side wall to expose part of the surface of the control gate; and the number of the first and second groups,

and removing the photoresist layer.

Optionally, the word line is etched by using a dry etching process.

Optionally, the process of forming an electrical connection on the control gate surface of the second region includes:

forming an interlayer dielectric layer covering the substrate, the word lines, the control gates and the fourth side walls;

and forming a contact hole for exposing the control gate in the interlayer dielectric layer of the second region, and forming the electric connector in the contact hole.

In summary, the present invention provides a flash memory device and a method for manufacturing the same, wherein the flash memory device includes: a substrate including a first region and a second region; word lines extending along straight lines in the first region; the floating gate and the control gate are sequentially stacked on the surfaces of the first region and the second region and positioned on two sides of the word line, wherein in the second region, part of the surface of the control gate is provided with an electric connector. According to the invention, the word line is arranged in the first region, and the electric connecting piece is arranged on part of the surface of the control gate in the second region, so that the distance between the word line and the electric connecting piece is increased, the connection difficulty of the control gate is reduced, and the short circuit risk of the flash memory device is reduced. Meanwhile, the word line and the grid structure extend along a straight line, so that the process window of a subsequent photoetching process is enlarged, and the size of a flash memory device is reduced.

Drawings

FIG. 1 is a design layout for a flash memory device with a hard mask layer formed;

FIG. 2 is a design layout before a flash memory device is formed with a contact hole;

fig. 3 is a schematic structural diagram of a flash memory device according to an embodiment of the present invention;

fig. 4 is a flowchart of a method for manufacturing a flash memory device according to an embodiment of the invention;

fig. 5-18 are schematic structural diagrams corresponding to steps in a method for manufacturing a flash memory device according to an embodiment of the invention;

wherein the reference numbers are as follows:

1-a first photoresist layer; 2-a second photoresist layer; 3-word line; 4-a control gate layer; 5-contact holes;

100-a substrate; 101-an isolation trench; 110-a floating gate layer; 111-floating gate; 120-control gate layer; 121-control gate; 130-a hard mask layer; 140-an opening; 141-a first sidewall; 142-a second sidewall; 143-a third sidewall; 144-a fourth sidewall; 150-word line; 151-photoresist layer; 160-interlayer dielectric layer; 161. 162-electrical connection;

x1-terminal region; x2-device unit area; a1-a first region; a2-second region.

Detailed Description

The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

Fig. 3 is a schematic structural diagram of a flash memory device according to an embodiment of the invention. Referring to fig. 3, the flash memory device according to the present embodiment includes:

a substrate 100 including a first region A1 and a second region A2;

word lines 150 extending in a straight line in the first region A1;

and a floating gate 111 and a control gate 121 sequentially stacked on the surfaces of the first and second regions A1 and A2 and located at both sides of the word line 150, wherein in the second region A2, a part of the surface of the control gate 121 is provided with an electrical connector 161.

With continued reference to fig. 3, in the present embodiment, a plurality of isolation trenches 101 are disposed at intervals in the substrate 100, an extending direction of the isolation trenches 101 (i.e., the Y2 direction in fig. 3) is perpendicular to an extending direction of the word lines 150 (i.e., the Y1 direction in fig. 3), and the floating gates 111 are disposed on the surface of the substrate 100 between the isolation trenches 101.

In this embodiment, a first sidewall (not shown in the figure) is further disposed on the surface of the control gate 121, in the first region A1, a second sidewall (not shown in the figure) is disposed on the first sidewall and a sidewall of the control gate 121 close to the word line 150, and in the second region A2, a sidewall of the control gate 121 close to the word line 150 is disposed with the second sidewall; the second side walls and the side walls of the floating gates 111 close to the word lines 150 are provided with third side walls (not shown in the figure), and the first side walls, the control gates 121 and the side walls of the floating gates 111 different from the side walls of the word lines 150 are provided with fourth side walls (not shown in the figure). Optionally, a metal silicide layer (not shown in the figure) and an interlayer dielectric layer (not shown in the figure) are sequentially disposed on the surfaces of the substrate 100, the fourth sidewall, the control gate 121, and the third sidewall, the electrical connection member 161 in the second region A2 penetrates through the metal silicide layer and the interlayer dielectric layer and connects the control gate 121, and the electrical connection member 162 connected to the word line 150 is further disposed in the first region A1.

Optionally, referring to fig. 4, the flash memory device includes a device cell area X2 and a header area X1 adjacent to the device cell area X2, the first area A1 and the second area A2 are both located in the header area X1, and an intersection line of the first area A1 and the second area A2 is parallel to an intersection line of the device cell area X2 and the header area X1.

In this embodiment, the device size of the flash memory device is smaller than 90nm, the flash memory device increases the distance between the word line 150 and the electrical connection member 161 by arranging the word line 150 in the first region A1 and arranging the electrical connection member 161 on the surface of the control gate 121 in the second region A2, which is close to the word line 150, reduces the difficulty of taking out the control gate 121, avoids the occurrence of short circuit between the word line 150 and the electrical connection member 161 due to the reduction of the device size, and reduces the risk of short circuit of the flash memory device. Meanwhile, the word line 150 and the gate structure both extend along a straight line, which helps to reduce the device size of the flash memory device.

Accordingly, the present invention further provides a method for manufacturing a flash memory device, and fig. 5 is a flowchart of the method for manufacturing a flash memory device according to this embodiment, and referring to fig. 5, the method for manufacturing a flash memory device includes:

step S01: providing a substrate, wherein the substrate comprises a first region and a second region, word lines extending along straight lines and floating gates and control gates which are stacked in sequence and are arranged on two sides of the word lines are formed on the surfaces of the first region and the second region;

step S02: removing the word lines in the second region; and the number of the first and second groups,

step S03: forming electrical connections at a surface of the control gate of the second region.

Fig. 6 to fig. 18 are schematic structural diagrams corresponding to steps in the manufacturing method of the flash memory device according to the embodiment. The method for manufacturing the flash memory device according to the present embodiment will be described in detail with reference to fig. 6 to 18.

First, referring to fig. 6 to 12, step S01 is performed to provide a substrate 100, where the substrate 100 includes a first region A1 and a second region A2, and the surfaces of the first region A1 and the second region A2 are formed with a word line 150 extending along a straight line and a floating gate 111 and a control gate 121 stacked in sequence on both sides of the word line 150. Specifically, the process of forming the word line 150, the floating gate 111 and the control gate 121 includes: referring to fig. 6, a floating gate layer 110, a control gate layer 120 and a hard mask layer 130 are sequentially formed on a surface of the substrate 100, and an opening 140 exposing the control gate layer 120 is formed on the hard mask layer 130; referring to fig. 7, a first sidewall 141 is formed on a sidewall of the opening 140, and the control gate layer 120 is etched using the hard mask layer 130 and the first sidewall 141 as a mask, so that the opening 140 exposes the floating gate layer 110; referring to fig. 8, a second sidewall 142 is formed on a sidewall of the opening 140, and the floating gate layer 110 is etched using the hard mask layer 130 and the second sidewall 142 as a mask, so that the opening 140 exposes the substrate 100; referring to fig. 9, third sidewalls 143 are formed on sidewalls and a bottom of the opening 140, and the word lines 150 are formed in the opening 140; referring to fig. 10, the hard mask layer 130 and the control gate layer 120 and the floating gate layer 110 under the hard mask layer 130 are removed to form the control gate 121 and the floating gate 111.

Fig. 11 is a schematic top view of the flash memory device in step S01 (the first sidewall 140, the second sidewall 141, the third sidewall 142, and the upper half of the word line 150 are omitted). Fig. 6 to 10 and 12 are schematic cross-sectional views of the first region A1 along the BB 'direction and the second region A2 along the CC' direction in fig. 11. Referring to fig. 11, a plurality of isolation trenches 101 are formed in the substrate 100 at intervals, and an extending direction of the isolation trenches 101 (i.e., a Y2 direction in fig. 11) is perpendicular to an extending direction of the word lines 150. Alternatively, referring to fig. 3, the floating gate 111 is formed on the surface of the substrate 100 between the isolation trenches 101. Further, referring to fig. 12, between step S01 and step S02, the method further includes: a fourth sidewall 144 is formed on a side of the control gate 121 and the floating gate 111 other than the word line 150.

In this embodiment, the substrate 100 is a silicon substrate, the floating gate 111, the control gate 121, and the word line 150 are made of polysilicon, and the first sidewall 141, the second sidewall 142, the third sidewall 143, and the fourth sidewall 144 are made of silicon oxide and/or silicon nitride.

Next, referring to fig. 13-15, step S02 is performed to remove the word lines 150 in the second area A2. Fig. 14 is a schematic cross-sectional structure along the direction BB 'in fig. 13 (i.e., a schematic cross-sectional structure of the first region A1), and fig. 15 is a schematic cross-sectional structure along the direction DD' in fig. 13 (i.e., a schematic cross-sectional structure corresponding to the location of the isolation trench 101 in the second region A2). Specifically, the process of removing the word line 150 in the second area A2 includes: forming a photoresist layer 151 covering the substrate 100, the fourth sidewalls 144 and the word lines 150 in the first region A1; etching the word line 150 using the photoresist layer 151 and the fourth sidewall 144 as a mask to remove the word line 150 in the second region A2, and simultaneously etching a portion of the first sidewall 141, the third sidewall 143, and the fourth sidewall 144 to expose a portion of the surface of the control gate 121; and, removing the photoresist layer 151. Optionally, the word line is etched by using a dry etching process. It should be noted that, in the dry etching process, the etching rate of silicon oxide is less than the etching rate of polysilicon, so that the etching rates of the first sidewall 141, the third sidewall 143, and the fourth sidewall 144 are less than the etching rate of the word line 150, so as to protect the control gate 121 from being damaged in the dry etching, where the fourth sidewall 144 covers the sidewall of the control gate 121 on the side far from the second sidewall 142, so as to prevent the sidewall of the control gate 121 from being etched, and thus prevent the width of the control gate 121 from being reduced.

Subsequently, referring to fig. 16 to 18, step S03 is performed to form an electrical connection on the control gate surface of the second region A2. Fig. 17 is a schematic cross-sectional structure view along the direction BB 'in fig. 16 (i.e., a schematic cross-sectional structure view of the first region A1), and fig. 18 is a schematic cross-sectional structure view along the direction DD' in fig. 16 (i.e., a schematic cross-sectional structure view corresponding to the position of the isolation trench 101 in the second region A2). Specifically, the process of forming the electrical connection member 161 on the surface of the control gate 121 in the second region A2 includes: forming an interlayer dielectric layer 160 covering the substrate 100, the word line 150, the control gate 121 and the fourth sidewall 144; contact holes (not shown) exposing the control gates 121 are formed in the interlayer dielectric layer 160 of the second region A2, and the electrical connectors 161 are formed in the contact holes. Alternatively, while a contact hole exposing the control gate 121 is formed and the electrical connection member 161 is formed in the contact hole, a contact hole (not shown) exposing the word line 150 is formed in the first region A1, and an electrical connection member 162 connecting the word line 150 is formed in the contact hole. Optionally, between step S02 and step S03, the method further includes: a metal silicide layer (not shown) is formed on the substrate 100, the word line 150, the control gate 121, and the fourth sidewall 144, and the interlayer dielectric layer is formed on the metal silicide layer.

As can be seen from comparing fig. 1 and fig. 13, in the conventional flash memory device, a partial region of a floating gate (not shown in the drawings, the topography of the floating gate is the same as that of the first photoresist layer 1) is a step-like structure (i.e., the portion indicated by c in fig. 1), so that the distance between the step-like structure in the floating gate and an adjacent floating gate is smaller than the distance between other portions in the floating gate and the adjacent floating gate, and when the device size is reduced, there is a risk of breaking a film layer between the step-like structure and the adjacent floating gate; in the flash memory device of the embodiment, the floating gate 111, the control gate 121 and the word line 150 all extend along a straight line, and the distances between adjacent gate structures are the same everywhere, so that the risk of film layer disconnection between adjacent gate structures when the size of the device is reduced.

As can be seen from fig. 16 to 18, in the finally formed flash memory device of this embodiment, the word line 150 is formed only in the first region A1, and the control gate 121 is connected out through the electrical connection member 161 formed in the second region A2, so that the difficulty in connecting out the control gate 121 is reduced, and the distance between the electrical connection member 161 and the word line 150 is increased, thereby avoiding the occurrence of short circuit between the word line 150 and the electrical connection member 161 due to the reduction of the device size, and reducing the risk of short circuit of the flash memory device while reducing the device area.

As can be seen from comparing fig. 2 and fig. 16, in the embodiment, the area of the photoresist layer 151 is significantly larger than the area of the second photoresist layer 2 in the conventional method for manufacturing a flash memory device, so that the risk of photoresist floating of the photoresist layer 151 is reduced or avoided, and the process window of the subsequent photolithography process is correspondingly increased.

In summary, the present invention provides a flash memory device and a method for manufacturing the same, wherein the flash memory device includes: a substrate including a first region and a second region; word lines extending along straight lines in the first region; the floating gate and the control gate are sequentially stacked on the surfaces of the first region and the second region and positioned on two sides of the word line, wherein in the second region, part of the surface of the control gate is provided with an electric connector. According to the invention, the word line is arranged in the first region, and the electric connecting piece is arranged on part of the surface of the control gate in the second region, so that the distance between the word line and the electric connecting piece is increased, the connection difficulty of the control gate is reduced, and the short circuit risk of the flash memory device is reduced. Meanwhile, the word line and the grid structure extend along a straight line, so that the process window of a subsequent photoetching process is enlarged, and the size reduction of the flash memory device is facilitated.

The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. Any person skilled in the art can make any equivalent substitutions or modifications on the technical solutions and technical contents disclosed in the present invention without departing from the scope of the technical solutions of the present invention, and still fall within the protection scope of the present invention without departing from the technical solutions of the present invention.

Claims (11)

1. A flash memory device, comprising:

a substrate including a first region and a second region;

word lines extending along straight lines in the first region;

the floating gate and the control gate are sequentially stacked on the surfaces of the first region and the second region and positioned on two sides of the word line, wherein in the second region, part of the surface of the control gate is provided with an electric connector.

2. The flash memory device of claim 1, wherein a plurality of spaced-apart isolation trenches are disposed in the substrate, the isolation trenches extending in a direction perpendicular to a direction in which the word lines extend, the floating gate being disposed on the surface of the substrate between the isolation trenches.

3. The flash memory device according to claim 1 or 2, wherein the flash memory device includes a device cell region and a header region adjacent to the device cell region, the first region and the second region are both located within the header region, and an intersection line of the first region and the second region is parallel to an intersection line of the device cell region and the header region.

4. The flash memory device according to claim 3, wherein a first sidewall is further disposed on the surface of the control gate, a second sidewall is disposed on the sidewalls of the first sidewall and the control gate close to the word line in the first region, and a second sidewall is disposed on the sidewalls of the control gate close to the word line in the second region.

5. The flash memory device according to claim 4, wherein the second sidewall and the sidewall of the floating gate adjacent to the word line are provided with a third sidewall, and the first sidewall, the control gate and the sidewall of the floating gate different from the word line are provided with a fourth sidewall.

6. A method of manufacturing a flash memory device, comprising:

providing a substrate, wherein the substrate comprises a first region and a second region, word lines extending along straight lines and floating gates and control gates which are stacked in sequence and are arranged on two sides of the word lines are formed on the surfaces of the first region and the second region;

removing the word lines in the second region; and the number of the first and second groups,

forming electrical connections at a surface of the control gate of the second region.

7. The method of manufacturing a flash memory device according to claim 6, wherein the process of forming the word line, the floating gate, and the control gate includes:

sequentially forming a floating gate layer, a control gate layer and a hard mask layer on the surface of the substrate, wherein an opening for exposing the control gate layer is formed on the hard mask layer;

forming a first side wall on the side wall of the opening, and etching the control gate layer by taking the hard mask layer and the first side wall as masks so as to expose the floating gate layer from the opening;

forming a second side wall on the side wall of the opening, and etching the floating gate layer by taking the hard mask layer and the second side wall as masks so as to expose the substrate from the opening;

forming third side walls on the side walls and the bottoms of the openings, and forming the word lines in the openings; and the number of the first and second groups,

and removing the hard mask layer and the control gate layer and the floating gate layer below the hard mask layer to form the control gate and the floating gate.

8. The method of manufacturing a flash memory device according to claim 7, wherein after the forming of the word line, the floating gate, and the control gate, and before the removing of the word line in the second region, further comprises:

and forming a fourth side wall on one side of the control gate and the floating gate, which is different from the word line.

9. The method of manufacturing a flash memory device according to claim 8, wherein the process of removing the word line in the second region includes:

forming a photoresist layer covering the substrate, the fourth side walls and the word lines in the first region;

etching the word line by using the photoresist layer and the fourth side wall as masks to remove the word line in the second region, and simultaneously etching part of the first side wall, the third side wall and the fourth side wall to expose part of the surface of the control gate; and the number of the first and second groups,

and removing the photoresist layer.

10. The method of manufacturing a flash memory device according to claim 9, wherein the word line is etched using a dry etching process.

11. The method of manufacturing a flash memory device according to claim 10, wherein the process of forming an electrical connection at the control gate surface of the second region comprises:

forming an interlayer dielectric layer covering the substrate, the word lines, the control gates and the fourth side walls;

and forming a contact hole for exposing the control gate in the interlayer dielectric layer of the second region, and forming the electric connector in the contact hole.

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