CN104576646B - A kind of IC chip and its manufacture method - Google Patents
A kind of IC chip and its manufacture method Download PDFInfo
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- CN104576646B CN104576646B CN201310472506.8A CN201310472506A CN104576646B CN 104576646 B CN104576646 B CN 104576646B CN 201310472506 A CN201310472506 A CN 201310472506A CN 104576646 B CN104576646 B CN 104576646B
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- 239000004065 semiconductor Substances 0.000 claims abstract description 51
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- 229920005591 polysilicon Polymers 0.000 claims description 113
- 238000005530 etching Methods 0.000 claims description 40
- 239000002019 doping agent Substances 0.000 claims description 39
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Abstract
Present invention is disclosed a kind of IC chip and its manufacture method, including a Semiconductor substrate；Half floating gate memory array and nonvolatile memory array formed on the semiconductor substrate；The first input/output terminal and the second input/output terminal for connecting half floating gate memory array and the nonvolatile memory array.The present invention is integrated on the same chip by half floating gate memory array and nonvolatile memory array, using half floating gate memory array as nonvolatile memory array caching, the storage speed of nonvolatile memory array can be accelerated, Large Copacity, the formula of high speed and data storage and operation is realized.
Description
Technical field
The invention belongs to semiconductor device chip technical field, more particularly to a kind of IC chip and its manufacturer
Method.
Background technology
With the progress of mobile device, the requirement more and more higher of capacity and speed to semiconductor memory.It is now mobile
The data and program of equipment such as mobile phone are stored in the chip being made up of NAND memory array or NOR memory arrays
It is interior, and the operating voltage for the chip being made up of NAND memory array or NOR memory arrays is higher, power consumption is larger.Meanwhile,
In order to accelerate the speed of semiconductor memory data access, generally require to be used as computing list with dram chip in a mobile device
Caching in member and NAND memory chip or NOR memory chips.
Existing DRAM memory is made up of single-transistor and single capacitor（1T-1C DRAM）.Referring to Fig. 1, one traditional
1T-1C DRAM memories are made up of a transistor 103 and a capacitor 104.During work, it can be stored into one and patrol
Position is collected, the first logic state is expressed as when the voltage of capacitor 104 is high（1 or 0）；When the voltage of capacitor 104 is low then
It is expressed as second of logic state（0 or 1）.When this element is read out, transistor 103 is controlled to open by wordline 101, bit line
102 and capacitor 104 produce that electric charge is shared and cause the voltage change of bit line 102, this voltage change is amplified by voltage induced
Device amplification is so as to differentiate the logic state of the unit.
The capacitor 104 of 1T-1C DRAM memories needs sufficiently large capacitance just to can guarantee that to be enough to store enough electricity
Lotus, therefore its area taken is difficult to be reduced, this improves the difficulty and complexity of manufacture 1T-1C DRAM memories.Together
When, there is a great difference in the structure of 1T-1C DRAM memories and the structure of nand memory and the structure of NOR memories, because
The difficulty that this integrates 1T1C DRAM memories and nand memory or NOR memories is very big, and this is accomplished by with another
Chip piece is used as the speed-up chip of NAND memory chip or NOR storage chips.
Half floating transistor is a kind of device of use dual poly gate, in paper " A Semi-Floating Gate
Transistor for Low-Voltage Ultrafast Memory and Sensing Operation, Science.
Described in 341,640 (2013) ", there is high speed, high density and low-power consumption.
The content of the invention
In view of the defect that above-mentioned prior art is present, the purpose of the present invention is to propose to a kind of IC chip and its manufacture
Method, so as to which half floating transistor DRAM memory and nand memory or NOR memories are integrated in into same chip
On.
The purpose of the present invention will be achieved by the following technical programs：
A kind of IC chip, including：
One Semiconductor substrate；
Half floating gate memory array and nonvolatile memory array formed on the semiconductor substrate；
The first input/output terminal for connecting half floating gate memory array and the nonvolatile memory array
With the second input/output terminal.
It is preferred that, a kind of above-mentioned IC chip, wherein：Also include being used to control half floating gate memory array
The data control circuit of data transfer between the nonvolatile memory array.
It is preferred that, a kind of above-mentioned IC chip, wherein：The nonvolatile memory array is nand memory
Any one in array and NOR memory arrays.
It is preferred that, a kind of above-mentioned IC chip, wherein：Half floating gate memory array and described non-volatile
Isolated between memory array by fleet plough groove isolation structure.
A kind of manufacture method of said integrated circuit chip, comprises the following steps：
The dopant well with second of doping type is formed in the Semiconductor substrate with the first doping type；
In the superficial growth first layer gate dielectric layer of Semiconductor substrate, and by photoetching process and etching technics described
A floating boom opening is formed in one layer of gate dielectric layer, the floating boom opening is located at the dopant well with second of doping type
On；
The formed structure deposit first layer polysilicon of covering；
The position of the fleet plough groove isolation structure for isolating device is defined by photoetching process；
Using photoresist described in mask etching first layer polysilicon, and continue to etch the first layer gate dielectric layer and described
Semiconductor substrate, forms shallow trench in the Semiconductor substrate, forms insulating barrier, the insulation in the shallow trench afterwards
Layer causes the dopant well with second of doping type to be only located in the substrate area of half floating-gate memory；
Carry out ion doping so that the first layer polysilicon in half floating-gate memory region is mixed with the first
Miscellany type, the first layer polysilicon in nonvolatile memory has second of doping type；
By photoetching process and etching technics, the first layer polysilicon is etched, half floating-gate memory is formed respectively and non-
The first layer polysilicon gate of volatile memory, wherein the first layer polysilicon gate covering of half floating-gate memory it is whole or
The part floating boom opening, and be connected by the floating boom opening with the dopant well with second of doping type；
Etch away the first layer gate dielectric layer exposed；
The formed structure formation second layer gate dielectric layer of covering, and the formation second layer is more on second layer gate dielectric layer
Crystal silicon, then etches the second layer polysilicon by photoetching process and etching technics, forms half floating-gate memory respectively and non-
The second layer polysilicon gate of volatile memory, wherein the second layer polysilicon gate of half floating-gate memory at least extends to institute
State on the dopant well with second of doping type；
Grid is formed respectively in the both sides of half floating-gate memory and the second layer polysilicon gate of nonvolatile memory
Side wall, and the second layer gate dielectric layer is etched along the edge of the grid curb wall, to expose the Semiconductor substrate；
The semiconductor in half floating-gate memory and the both sides of the second layer polysilicon gate of nonvolatile memory
Source region and the drain region of device are formed in substrate；
Deposit passivation layer, and formation contact hole and metal electrode in the passivation layer.
A kind of manufacture method of said integrated circuit chip, comprises the following steps：
The dopant well with second of doping type is formed in the Semiconductor substrate with the first doping type；
In the superficial growth first layer gate dielectric layer of Semiconductor substrate, and by photoetching process and etching technics described
A floating boom opening is formed in one layer of gate dielectric layer, the floating boom opening is located at the dopant well with second of doping type
On；
The formed structure deposit first layer polysilicon of covering；
The position of the fleet plough groove isolation structure for isolating device is defined by photoetching process；
Using photoresist described in mask etching first layer polysilicon, and continue to etch the first layer gate dielectric layer and described
Semiconductor substrate, forms shallow trench in the Semiconductor substrate, forms insulating barrier, the insulation in the shallow trench afterwards
Layer causes the dopant well with second of doping type to be only located in the substrate area of half floating-gate memory；
Carry out ion doping so that the first layer polysilicon in half floating-gate memory region is mixed with the first
Miscellany type, the first layer polysilicon in nonvolatile memory has second of doping type；
By photoetching process and etching technics, etching is located at the institute on the dopant well with second of doping type
State the first layer polysilicon after first layer polysilicon, etching can by the whole or part floating boom opening with it is described
Dopant well connection with second of doping type；
Etch away the first layer gate dielectric layer exposed；
The formed structure formation second layer gate dielectric layer of covering, and the formation second layer is more on second layer gate dielectric layer
Crystal silicon, then etches the second layer polysilicon by photoetching process and etching technics, forms half floating-gate memory respectively and non-
The second layer polysilicon gate of volatile memory, wherein the second layer polysilicon gate of half floating-gate memory extends to the tool
On the dopant well for having second of doping type；
Along half floating-gate memory and the edge of the second layer polysilicon gate of nonvolatile memory, exposure is etched away
The second layer gate dielectric layer gone out, and continue to etch away remaining described after the first layer polysilicon exposed, etching
First layer polysilicon forms the first layer polysilicon gate of half floating-gate memory and nonvolatile memory respectively, now with second
The dopant well for planting doping type is partially etched；
Grid is formed respectively in the both sides of half floating-gate memory and the second layer polysilicon gate of nonvolatile memory
Side wall, and etch away the second layer gate dielectric layer exposed along the edge of the grid curb wall, described is partly led with exposing
Body substrate；
The semiconductor in half floating-gate memory and the both sides of the second layer polysilicon gate of nonvolatile memory
Source region and the drain region of device are formed in substrate；
Deposit passivation layer, and formation contact hole and metal electrode in the passivation layer.
It is preferred that, the manufacture method of said integrated circuit chip, wherein：The first described doping type is n-type, described the
Two kinds of doping types are p-type, or, the first described doping type is p-type, and second of doping type is n-type.
The present invention protrusion effect be：
A kind of IC chip and its manufacture method of the present invention use half floating-gate memory of dual poly gate, will be partly
Floating gate memory array and nonvolatile memory array are integrated on the same chip, simplify manufacturing process.Deposited with half floating boom
Memory array can accelerate the storage speed of nonvolatile memory array as the caching of nonvolatile memory array.It is non-
The storage density of volatile memory array is high, and the storage speed of half floating gate memory array is fast, by half floating gate memory array
It is integrated on the same chip with nonvolatile memory array, it is possible to achieve Large Copacity, the formula of high speed and data storage with
Operation.
Just accompanying drawing in conjunction with the embodiments below, the embodiment to the present invention is described in further detail, so that of the invention
Technical scheme is more readily understood, grasped.
Brief description of the drawings
Fig. 1 is the electrical block diagram of the 1T-1C DRAM memories of prior art；
Fig. 2 is a kind of structural representation of one embodiment of IC chip of the present invention；
Fig. 3 is a kind of half single floating-gate memory of IC chip of the present invention and single non-volatile deposited
The section of structure of one embodiment of reservoir；
Fig. 4 to Fig. 9 is the present invention by the integrated system on the same chip of half floating-gate memory and nonvolatile memory
Make the process chart of one embodiment of method；
Figure 10 to Figure 14 is the present invention half floating-gate memory and nonvolatile memory is integrated on the same chip
The process chart of second embodiment of manufacture method.
Embodiment
The present invention is further detailed explanation with embodiment below in conjunction with the accompanying drawings.In figure, for convenience
Illustrate, be exaggerated layer and the thickness in region, shown size does not represent actual size.Implement with reference to the idealization that figure is the present invention
The schematic diagram of example, the embodiment shown in the present invention should not be considered limited to the given shape in region shown in figure, but wrap
Resulting shape is included, such as manufactures caused deviation.The characteristics of obtained curve generally has bending or be mellow and full is for example etched,
But in an embodiment of the present invention, represented with rectangle, the expression in figure is schematical, but this should not be construed as limiting
The scope of the present invention.In the following description, used term substrate can be understood as including just in technique processing simultaneously
Semiconductor wafer, may be included in other film layers prepared thereon.
Fig. 2 is a kind of structural representation of one embodiment of IC chip of the present invention.As shown in Fig. 2 including
Half floating gate memory array and nonvolatile memory array formed on the same semiconductor substrate, in addition to connect half floating boom
The first input/output terminal and the second input/output terminal of memory array and nonvolatile memory array.Wherein, it is non-volatile
Memory array is classified as any one in NAND memory array and NOR memory arrays.
By the first input/output terminal and the second input/output terminal, in half floating gate memory array and non-volatile it can deposit
Data exchange is carried out between memory array.Such as the data or program in nonvolatile memory array are read same
In half floating gate memory array on chip, quickly accessed for arithmetic processor.Or, by the number in half floating gate memory array
According to or program write back in nonvolatile memory array.That is, being deposited with half floating gate memory array as non-volatile
The caching of memory array, accelerates the speed that nonvolatile memory array accesses data.
As shown in Fig. 2 also including being used to control the number between half floating gate memory array and nonvolatile memory array
According to the data control circuit of transmission.
Each nonvolatile memory in nonvolatile memory array includes two layers gate dielectric layer, two-layer polysilicon
Grid and source region and drain region.Each half floating-gate memory in half floating gate memory array includes two layers gate dielectric layer, more than two layers
Crystal silicon grid and source region and drain region, wherein be connected as the polysilicon gate of floating grid with drain region by a diode, as
The polysilicon gate of control gate is at least extended on above-mentioned diode.
Fig. 3 be the present invention half floating gate memory array integrated on the same chip and nonvolatile memory array in
Single half floating-gate memory and single nonvolatile memory one embodiment section of structure.As shown in figure 3, including
Half floating-gate memory 401 and nonvolatile memory formed in the Semiconductor substrate 200 with the first doping type
402.Half floating-gate memory 401 and nonvolatile memory 402 are isolated by fleet plough groove isolation structure 300.Half floating-gate memory 401
Including two layers of gate dielectric layer（First layer gate dielectric layer 203a and second layer gate dielectric layer 207a）, two-layer polysilicon grid（First layer
Polysilicon gate 205a and second layer polysilicon gate 208a）, the first source region 210 and the first drain region 211.Wherein as floating grid
Impurity in first layer polysilicon gate 205a with the first doping type can be diffused to by floating boom opening 204 to be had
Diffusion region 206, one pole of pn-junction two in diffusion region 206 and the formation of dopant well 202 are formed in the dopant well 202 of second of doping type
Tubular construction, so that being connected as the first layer polysilicon gate 205a and the first drain region 211 of floating grid by a diode
Connect, and at least extended to as the second layer polysilicon gate 208a of control gate on above-mentioned diode.Nonvolatile memory
402 include two layers of gate dielectric layer（First layer gate dielectric layer 203b and second layer gate dielectric layer 207b）, two-layer polysilicon grid（First
Layer polysilicon gate 205b and second layer polysilicon gate 208b）, the second source region 212 and the second drain region 213.In half floating-gate memory
401 second layer polysilicon gate 208a and the second layer polysilicon gate 208b of nonvolatile memory 402 both sides are formed respectively
There is the grid curb wall 209 formed by insulating materials.In the collection being made up of half floating-gate memory 401 and nonvolatile memory 402
Into in circuit chip, include the passivation layer 311 and metal electrode 312 of isolation electrode.
The IC chip of the present invention can be manufactured by a variety of methods, and Fig. 4 to Fig. 9 describes the integrated circuit of the present invention
The technological process of one embodiment of the manufacture method of chip, wherein, illustrate only in figure single half floating-gate memory and
Single nonvolatile memory.
First, as shown in figure 4, in the oxide layer of superficial growth one of the Semiconductor substrate 200 with the first doping type
201, photoresist 301 is then deposited on oxide layer 201 and by photoetching process formation figure, be then with photoresist 301
Mask etching oxide layer 301 is to expose Semiconductor substrate 200, then by the method for ion implanting in Semiconductor substrate 200
Form the dopant well 202 with second of doping type.Wherein, the first doping type is n-type, and second of doping type is p
Type, or, correspondingly, the first doping type is p-type, and second of doping type is n-type.
Next, photoresist 301 and oxide layer 201 are divested, then in the superficial growth first layer grid of Semiconductor substrate 200
Dielectric layer 203, one layer of photoresist 302 is then deposited on first layer gate dielectric layer 203 and half is defined by photoetching process
The position of the floating boom opening 204 of floating-gate memory, then with photoresist 302 for mask etching first layer gate dielectric layer 203, the
A floating boom opening 204 is formed in one layer of gate dielectric layer 203, floating boom opening 204 is located at the doping with second of doping type
On trap 202, as shown in Figure 5.
Next, divesting photoresist 302, formed structure deposit first layer polysilicon 205 is then covered, is then passed through
Photoetching process defines the position of the fleet plough groove isolation structure for isolating device, then using photoresist as mask etching first layer
Polysilicon 205, and continue to etch the first layer gate dielectric layer 203 exposed and Semiconductor substrate 200, in Semiconductor substrate 200
Interior formation shallow trench, forms insulating barrier 300 in shallow trench afterwards, and insulating barrier 300 causes mixing with second doping type
Miscellaneous trap 202 is only located in the substrate area of half floating-gate memory.Then ion doping is carried out so that positioned at half floating-gate memory area
First layer polysilicon 205 in domain is with the first doping type, and the first layer polysilicon in nonvolatile memory
205 have second of doping type, as shown in Figure 6.
Next, by photoetching process and etching technics, etching of first layer polysilicon 205 forms the storage of half floating boom respectively
The first layer polysilicon gate 205a of the device and first layer polysilicon gate 205b of nonvolatile memory, wherein half floating-gate memory
First layer polysilicon gate 205a covers whole or part floating boom opening 204, and by floating boom opening 204 with being mixed with second
The dopant well 202 of miscellany type is connected.Wherein, first layer polysilicon gate 205a covers structure such as Fig. 7 a of whole floating boom opening 204
Shown, the structure of first layer polysilicon gate 205a covering part floating booms opening 204 is as shown in Figure 7b.
Next, by taking the structure shown in Fig. 7 a as an example, etching away exposed first layer gate dielectric layer 203, then covering institute
The structure formation second layer gate dielectric layer 207 of formation, and second layer polysilicon is formed on second layer gate dielectric layer 207, so
Afterwards by photoetching process and etching technics etching of second layer polysilicon, the second layer polysilicon gate of half floating-gate memory is formed respectively
208a and nonvolatile memory second layer polysilicon gate 208b, the second layer polysilicon gate 208a of half floating-gate memory is at least
Extend on the dopant well 202 with second of doping type.Wherein, the second layer polysilicon gate 208a of half floating-gate memory
Extend only on dopant well 202, first layer polysilicon gate 205a structure such as Fig. 8 a institutes are only surrounded in the side of dopant well 202
Show, the second layer polysilicon gate 208a of half floating-gate memory exceeds first layer polysilicon in first layer polysilicon gate 205a both sides
Grid 205a, first layer polysilicon gate 205a structure is surrounded as shown in Figure 8 b in its both sides.
Can also be while integration logic device, such as more in the second layer for forming half floating-gate memory and nonvolatile memory
During crystal silicon grid, the grid 208c of logical device can also be formed simultaneously, as shown in Figure 8 c.
Finally, in the second layer polysilicon gate 208a and the second layer polycrystalline of nonvolatile memory of half floating-gate memory
Si-gate 208b both sides form grid curb wall 209 respectively, and along the edge etching of second layer gate dielectric layer of grid curb wall 209
207 to expose Semiconductor substrate 200, and then the semiconductor in the second layer polysilicon gate 208a of half floating-gate memory both sides is served as a contrast
The first source region 210 and the first drain region 211 of half floating-gate memory are formed in bottom 200, and the second of nonvolatile memory
The second source region 212 and the second leakage of nonvolatile memory are formed in the Semiconductor substrate 200 of layer polysilicon gate 208b both sides
Area 213, finally deposits passivation layer 311, and forms contact hole and metal electrode 312 in passivation layer 311, as illustrated in fig. 9.Its
In, the structure of integration logic device as shown in figure 9b, includes the 3rd source region 214 and the 3rd of logical device simultaneously in the chips
Drain region 215.
Figure 10 to Figure 14 describes the technique stream of second embodiment of the manufacture method of the IC chip of the present invention
Journey, wherein, single half floating-gate memory and single nonvolatile memory are illustrate only in figure.
First, as shown in Figure 10, formed to have second in the Semiconductor substrate 200 with the first doping type and mixed
The dopant well 202 of miscellany type.Wherein, the first doping type is n-type, and second of doping type is p-type, or, correspondingly, the
A kind of doping type is p-type, and second of doping type is n-type.Then it is situated between in the superficial growth first layer grid of Semiconductor substrate 200
Matter layer 203, then in the one floating boom opening 204 of formation of first layer gate dielectric layer 203, floating boom opening 204, which is located at, to be had second
On the dopant well 202 of doping type.Then formed structure deposit first layer polysilicon 205 is covered, and passes through photoetching work
Skill defines the position of the fleet plough groove isolation structure for isolating device, then using photoresist as mask etching first layer polysilicon
205, and continue to etch the first layer gate dielectric layer 203 exposed and Semiconductor substrate 200, formed in Semiconductor substrate 200
Shallow trench, forms insulating barrier 300 in shallow trench afterwards, and insulating barrier 300 causes the dopant well 202 with second of doping type
In the substrate area for being only located at half floating-gate memory.Then ion doping is carried out so that in half floating-gate memory region
First layer polysilicon 205 has the first doping type, and the first layer polysilicon 205 in nonvolatile memory has
Second of doping type.
Next, by photoetching process and etching technics, etching be located at the dopant well 202 with second of doping type it
On first layer polysilicon 205, first layer polysilicon 205 after etching can by whole or part floating boom opening 204 with
Dopant well 202 with second of doping type is connected, wherein, the first layer polysilicon 205 on dopant well 202 is covered
The structure of whole floating boom opening 204 as shown in fig. 11a, float by the covering part of first layer polysilicon 205 on dopant well 202
The structure of grid opening 204 is as shown in figure 11b.
Next, by taking the structure shown in Figure 11 b as an example, etching away the first layer gate dielectric layer 203 exposed, then covering
The structure formation second layer gate dielectric layer 207 formed, and the formation second layer polysilicon on second layer gate dielectric layer 207,
Then by photoetching process and etching technics etching of second layer polysilicon, the second layer polysilicon of half floating-gate memory is formed respectively
Grid 208a and nonvolatile memory second layer polysilicon gate 208b.Wherein, the second layer polysilicon gate of half floating-gate memory
208a is extended on the dopant well 202 with second of doping type, as shown in figure 12.
Next, many along the second layer polysilicon gate 208a of half floating-gate memory and the second layer of nonvolatile memory
Crystal silicon grid 208b edge, etches away the second layer gate dielectric layer 207 and first layer polysilicon 205 exposed, now with
The dopant well 202 of two kinds of doping types can be partially etched, and remaining first layer polysilicon forms half floating boom respectively after etching
The first layer polysilicon gate 205a of the memory and first layer polysilicon gate 205b of nonvolatile memory, as shown in figure 13.
Finally, in the second layer polysilicon gate 208a and the second layer polycrystalline of nonvolatile memory of half floating-gate memory
Si-gate 208b both sides form grid curb wall 209 respectively, and along the edge etching of second layer gate dielectric layer of grid curb wall 209
207 to expose Semiconductor substrate 200, and then the semiconductor in the second layer polysilicon gate 208a of half floating-gate memory both sides is served as a contrast
The first source region 210 and the first drain region 211 of half floating-gate memory are formed in bottom 200, and the second of nonvolatile memory
The second source region 212 and the second leakage of nonvolatile memory are formed in the Semiconductor substrate 200 of layer polysilicon gate 208b both sides
Area 213, finally deposits passivation layer 311, and forms contact hole and metal electrode 312 in passivation layer 311, as shown in figure 14.
The present invention still has numerous embodiments, all technical sides formed by all use equivalents or equivalent transformation
Case, is within the scope of the present invention.
Claims (3)
1. a kind of manufacture method of IC chip, the IC chip, including：One Semiconductor substrate；
Half floating gate memory array and nonvolatile memory array formed on the semiconductor substrate；
The first input/output terminal and for connecting half floating gate memory array and the nonvolatile memory array
Two input/output terminals；
Also include being used to control the data transfer between half floating gate memory array and the nonvolatile memory array
Data control circuit；
The nonvolatile memory array is any one in NAND memory arrays and NOR memory arrays；
Isolated between half floating gate memory array and the nonvolatile memory array by fleet plough groove isolation structure；
It is characterized in that：The ic core piece making method comprises the following steps：
The dopant well with second of doping type is formed in the Semiconductor substrate with the first doping type；
In the superficial growth first layer gate dielectric layer of Semiconductor substrate, and by photoetching process and etching technics in the first layer
Form a floating boom opening in gate dielectric layer, the floating boom opening be located at the dopant well with second of doping type it
On；
The formed structure deposit first layer polysilicon of covering；
The position of the fleet plough groove isolation structure for isolating device is defined by photoetching process；
Using photoresist described in mask etching first layer polysilicon, and continue to etch the first layer gate dielectric layer and described partly lead
Body substrate, forms shallow trench in the Semiconductor substrate, forms insulating barrier in the shallow trench afterwards, and the insulating barrier makes
The dopant well that must have second of doping type is only located in the substrate area of half floating-gate memory；
Carry out ion doping so that the first layer polysilicon in half floating-gate memory region has the first doping class
Type, the first layer polysilicon in nonvolatile memory has second of doping type；
By photoetching process and etching technics, the first layer polysilicon is etched, half floating-gate memory is formed respectively and non-volatile
Property memory first layer polysilicon gate, wherein the first layer polysilicon gate covering of half floating-gate memory is whole or part
The floating boom opening, and be connected by the floating boom opening with the dopant well with second of doping type；Etch away sudden and violent
The first layer gate dielectric layer exposed；
The formed structure formation second layer gate dielectric layer of covering, and the formation second layer polycrystalline on second layer gate dielectric layer
Silicon, then etches the second layer polysilicon by photoetching process and etching technics, forms half floating-gate memory and Fei Yi respectively
The second layer polysilicon gate of the property lost memory, wherein the second layer polysilicon gate of half floating-gate memory at least extend to it is described
On dopant well with second of doping type；
Grid curb wall is formed respectively in the both sides of half floating-gate memory and the second layer polysilicon gate of nonvolatile memory,
And the second layer gate dielectric layer is etched along the edge of the grid curb wall, to expose the Semiconductor substrate；
The Semiconductor substrate in half floating-gate memory and the both sides of the second layer polysilicon gate of nonvolatile memory
The interior source region for forming device and drain region；
Deposit passivation layer, and formation contact hole and metal electrode in the passivation layer.
2. a kind of manufacture method of IC chip, the IC chip, including：One Semiconductor substrate；Described
Half floating gate memory array and nonvolatile memory array formed in Semiconductor substrate；For connecting the half floating boom storage
The first input/output terminal and the second input/output terminal of device array and the nonvolatile memory array, it is characterised in that institute
Manufacture method is stated to comprise the following steps：Being formed in the Semiconductor substrate with the first doping type has second of doping class
The dopant well of type；In the superficial growth first layer gate dielectric layer of Semiconductor substrate, and by photoetching process and etching technics in institute
State in first layer gate dielectric layer one floating boom opening of formation, the floating boom opening, which is located at, described has mixing for second doping type
On miscellaneous trap；
The formed structure deposit first layer polysilicon of covering；
The position of the fleet plough groove isolation structure for isolating device is defined by photoetching process；
Using photoresist described in mask etching first layer polysilicon, and continue to etch the first layer gate dielectric layer and described partly lead
Body substrate, forms shallow trench in the Semiconductor substrate, forms insulating barrier in the shallow trench afterwards, and the insulating barrier makes
The dopant well that must have second of doping type is only located in the substrate area of half floating-gate memory；
Carry out ion doping so that the first layer polysilicon in half floating-gate memory region has the first doping class
Type, the first layer polysilicon in nonvolatile memory has second of doping type；
By photoetching process and etching technics, etching is located at described the on the dopant well with second of doping type
The first layer polysilicon after one layer of polysilicon, etching has second by the whole or part floating boom opening with described
Plant the dopant well connection of doping type；
Etch away the first layer gate dielectric layer exposed；
The formed structure formation second layer gate dielectric layer of covering, and the formation second layer polycrystalline on second layer gate dielectric layer
Silicon, then etches the second layer polysilicon by photoetching process and etching technics, forms half floating-gate memory and Fei Yi respectively
The second layer polysilicon gate of the property lost memory, wherein the second layer polysilicon gate of half floating-gate memory is extended to and described had
On the dopant well of second of doping type；
Along half floating-gate memory and the edge of the second layer polysilicon gate of nonvolatile memory, etch away what is exposed
The second layer gate dielectric layer, and continue to etch away remaining described first after the first layer polysilicon exposed, etching
Layer polysilicon forms the first layer polysilicon gate of half floating-gate memory and nonvolatile memory respectively, is now mixed with second
The dopant well of miscellany type is partially etched；
Grid curb wall is formed respectively in the both sides of half floating-gate memory and the second layer polysilicon gate of nonvolatile memory,
And the second layer gate dielectric layer exposed is etched away along the edge of the grid curb wall, served as a contrast with exposing the semiconductor
Bottom；
The Semiconductor substrate in half floating-gate memory and the both sides of the second layer polysilicon gate of nonvolatile memory
The interior source region for forming device and drain region；
Deposit passivation layer, and formation contact hole and metal electrode in the passivation layer.
3. the manufacture method of any one IC chip according to claim 1 or 2, it is characterised in that：Described
A kind of doping type is n types, and second of doping type is p types；Or, the first described doping type is p types, institute
It is n types to state second of doping type.
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| CN111477624B (en) * | 2020-04-27 | 2022-10-11 | 复旦大学 | Semi-floating gate memory based on longitudinal tunneling transistor and preparation method thereof |
| CN111540740B (en) * | 2020-05-13 | 2022-06-21 | 复旦大学 | Semi-floating gate memory based on pn junction and Schottky diode and preparation method thereof |
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