CN104576646A - Integrated circuit chip and manufacturing method thereof - Google Patents
Integrated circuit chip and manufacturing method thereof Download PDFInfo
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- CN104576646A CN104576646A CN201310472506.8A CN201310472506A CN104576646A CN 104576646 A CN104576646 A CN 104576646A CN 201310472506 A CN201310472506 A CN 201310472506A CN 104576646 A CN104576646 A CN 104576646A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
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- 239000004065 semiconductor Substances 0.000 claims abstract description 52
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 122
- 229920005591 polysilicon Polymers 0.000 claims description 122
- 238000000034 method Methods 0.000 claims description 45
- 239000002019 doping agent Substances 0.000 claims description 42
- 238000005530 etching Methods 0.000 claims description 39
- 230000008569 process Effects 0.000 claims description 29
- 238000001259 photo etching Methods 0.000 claims description 24
- 238000002161 passivation Methods 0.000 claims description 13
- 230000004888 barrier function Effects 0.000 claims description 12
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- 238000002955 isolation Methods 0.000 claims description 9
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- 239000003990 capacitor Substances 0.000 description 6
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- 238000005516 engineering process Methods 0.000 description 1
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Abstract
The invention discloses an integrated circuit chip and a manufacturing method thereof. The integrated circuit chip comprises a semi-conductor substrate, a semi-floating gate memory array, a nonvolatile memory array, a first input and output end and a second input and output end, wherein the semi-floating gate memory array and the nonvolatile memory array are formed on the semi-conductor substrate, and the first input and output end and the second input and output end are used for connecting the semi-floating gate memory array and the nonvolatile memory array. The semi-floating gate memory array and the nonvolatile memory array are integrated on the same chip, the semi-floating gate memory array serving as cache of the nonvolatile memory array can increase the storage speed of the nonvolatile memory array, and large-capacity high-speed program and data storage and operations can be realized.
Description
Technical field
The invention belongs to semiconductor device chip technical field, particularly relate to a kind of integrated circuit (IC) chip and manufacture method thereof.
Background technology
Along with the progress of mobile device, to the capacity of semiconductor memory and the requirement of speed more and more higher.The data of present mobile device such as mobile phone and program are all stored in the chip that is made up of nand memory array or NOR memory array, and the operating voltage of the chip be made up of nand memory array or NOR memory array is higher, and power consumption is larger.Meanwhile, in order to accelerate the speed of semiconductor memory data access, often need to be used as the buffer memory in arithmetic element and NAND memory chip or NOR memory chip with dram chip in a mobile device.
Existing DRAM memory is made up of (1T-1C DRAM) single-transistor and single capacitor.See Fig. 1, a traditional 1T-1C DRAM memory is made up of a transistor 103 and a capacitor 104.During work, it can be stored into a logical bit, is expressed as the first logic state (1 or 0) when capacitor 104 voltage is high; The second logic state (0 or 1) is then expressed as when capacitor 104 voltage is low.When this element is read, transistor 103 is controlled to open by wordline 101, and bit line 102 and capacitor 104 produce electric charge and share and the change in voltage that causes bit line 102, and this change in voltage is amplified by voltage induced amplifier thus differentiated the logic state of this unit.
The capacitor 104 of 1T-1C DRAM memory needs enough large capacitance guarantee to be enough to store enough electric charges, and therefore its area taken is difficult to reduced, which increases the difficulty and complexity that manufacture 1T-1C DRAM memory.Simultaneously, there is a great difference in the structure of the structure of 1T-1C DRAM memory and the structure of nand memory and NOR memory, therefore difficulty 1T1C DRAM memory and nand memory or NOR memory integrated is very large, and this just needs the speed-up chip being used as NAND memory chip or NOR storage chip with another chip block.
Half floating transistor is a kind of device adopting dual poly gate, record in the paper " A Semi-Floating Gate Transistor for Low-Voltage Ultrafast Memory and Sensing Operation; Science. 341; 640 (2013) ", have at a high speed, the advantage of high density and low-power consumption.
Summary of the invention
In view of the defect that above-mentioned prior art exists, the object of the invention is to propose a kind of integrated circuit (IC) chip and manufacture method thereof, thus can by half floating transistor DRAM memory and nand memory or NOR memory on the same chip integrated.
Object of the present invention will be achieved by the following technical programs:
A kind of integrated circuit (IC) chip, comprising:
A Semiconductor substrate;
Half floating gate memory array formed on the semiconductor substrate and nonvolatile memory array;
For connecting the first input/output terminal and second input/output terminal of described half floating gate memory array and described nonvolatile memory array.
Preferably, above-mentioned a kind of integrated circuit (IC) chip, wherein: also comprise the data control circuit for controlling the transfer of data between described half floating gate memory array and described nonvolatile memory array.
Preferably, above-mentioned a kind of integrated circuit (IC) chip, wherein: described nonvolatile memory array is any one in nand memory array and NOR memory array.
Preferably, above-mentioned a kind of integrated circuit (IC) chip, wherein: isolated by fleet plough groove isolation structure between described half floating gate memory array and described nonvolatile memory array.
A manufacture method for said integrated circuit chip, comprises the following steps:
The dopant well with the second doping type is formed in the Semiconductor substrate with the first doping type;
At the superficial growth ground floor gate dielectric layer of Semiconductor substrate, and in described ground floor gate dielectric layer, form a floating boom opening by photoetching process and etching technics, on the dopant well described in described floating boom opening is positioned at the second doping type;
Cover the structure deposit ground floor polysilicon formed;
The position of the fleet plough groove isolation structure for isolating device is defined by photoetching process;
Take photoresist as ground floor polysilicon described in mask etching, and continue the described ground floor gate dielectric layer of etching and described Semiconductor substrate, shallow trench is formed in described Semiconductor substrate, in described shallow trench, form insulating barrier afterwards, described insulating barrier makes the dopant well with the second doping type only be positioned at the substrate region of half floating-gate memory;
Carry out ion doping, make the described ground floor polysilicon being positioned at half floating-gate memory region have the first doping type, the described ground floor polysilicon being positioned at nonvolatile memory has the second doping type;
By photoetching process and etching technics, etch described ground floor polysilicon, form the ground floor polysilicon gate of half floating-gate memory and nonvolatile memory respectively, the ground floor polysilicon gate of wherein said half floating-gate memory covers the whole or described floating boom opening of part, and is connected with the described dopant well with the second doping type by described floating boom opening;
Etch away the described ground floor gate dielectric layer exposed;
Cover the structure formed and form second layer gate dielectric layer, and second layer polysilicon is formed on second layer gate dielectric layer, then described second layer polysilicon is etched by photoetching process and etching technics, form the second layer polysilicon gate of half floating-gate memory and nonvolatile memory respectively, on the dopant well described in the second layer polysilicon gate of wherein said half floating-gate memory at least extends to the second doping type;
Form grid curb wall respectively in the both sides of the second layer polysilicon gate of described half floating-gate memory and nonvolatile memory, and etch described second layer gate dielectric layer, to expose described Semiconductor substrate along the edge of described grid curb wall;
Source region and the drain region of device is formed in the described Semiconductor substrate of the both sides of the second layer polysilicon gate of described half floating-gate memory and nonvolatile memory;
Deposit passivation layer, and contact hole and metal electrode is formed in described passivation layer.
A manufacture method for said integrated circuit chip, comprises the following steps:
The dopant well with the second doping type is formed in the Semiconductor substrate with the first doping type;
At the superficial growth ground floor gate dielectric layer of Semiconductor substrate, and in described ground floor gate dielectric layer, form a floating boom opening by photoetching process and etching technics, on the dopant well described in described floating boom opening is positioned at the second doping type;
Cover the structure deposit ground floor polysilicon formed;
The position of the fleet plough groove isolation structure for isolating device is defined by photoetching process;
Take photoresist as ground floor polysilicon described in mask etching, and continue the described ground floor gate dielectric layer of etching and described Semiconductor substrate, shallow trench is formed in described Semiconductor substrate, in described shallow trench, form insulating barrier afterwards, described insulating barrier makes the dopant well with the second doping type only be positioned at the substrate region of described half floating-gate memory;
Carry out ion doping, make the described ground floor polysilicon being positioned at half floating-gate memory region have the first doping type, the described ground floor polysilicon being positioned at nonvolatile memory has the second doping type;
By photoetching process and etching technics, etch the described ground floor polysilicon on the dopant well described in being positioned at the second doping type, the described ground floor polysilicon after etching can be connected with the described dopant well with the second doping type by whole or part described floating boom opening;
Etch away the described ground floor gate dielectric layer exposed;
Cover the structure formed and form second layer gate dielectric layer, and second layer polysilicon is formed on second layer gate dielectric layer, then described second layer polysilicon is etched by photoetching process and etching technics, form the second layer polysilicon gate of half floating-gate memory and nonvolatile memory respectively, on the dopant well described in the second layer polysilicon gate of wherein said half floating-gate memory extends to the second doping type;
Along the edge of the second layer polysilicon gate of described half floating-gate memory and nonvolatile memory, etch away the described second layer gate dielectric layer exposed, and continue to etch away the described ground floor polysilicon exposed, after etching, remaining described ground floor polysilicon forms the ground floor polysilicon gate of half floating-gate memory and nonvolatile memory respectively, and the dopant well now with the second doping type is partially etched;
Form grid curb wall respectively in the both sides of the second layer polysilicon gate of described half floating-gate memory and nonvolatile memory, and etch away the described second layer gate dielectric layer exposed, to expose described Semiconductor substrate along the edge of described grid curb wall;
Source region and the drain region of device is formed in the described Semiconductor substrate of the both sides of the second layer polysilicon gate of described half floating-gate memory and nonvolatile memory;
Deposit passivation layer, and contact hole and metal electrode is formed in described passivation layer.
Preferably, the manufacture method of said integrated circuit chip, wherein: the first doping type described is N-shaped, described the second doping type is p-type, or the first doping type described is p-type, and described the second doping type is N-shaped.
Outstanding effect of the present invention is:
A kind of integrated circuit (IC) chip of the present invention and manufacture method thereof adopt half floating-gate memory of dual poly gate, by half floating gate memory array and nonvolatile memory array on the same chip integrated, simplify manufacturing process.With the buffer memory of half floating gate memory array as nonvolatile memory array, the storage speed of nonvolatile memory array can be accelerated.The storage density of nonvolatile memory array is high, the storage speed of half floating gate memory array is fast, by half floating gate memory array and nonvolatile memory array on the same chip integrated, can realize Large Copacity, high speed formula and data store with operation.
Below just accompanying drawing in conjunction with the embodiments, is described in further detail the specific embodiment of the present invention, is easier to understand, grasp to make technical solution of the present invention.
Accompanying drawing explanation
Fig. 1 is the electrical block diagram of the 1T-1C DRAM memory of prior art;
Fig. 2 is the structural representation of an embodiment of a kind of integrated circuit (IC) chip of the present invention;
Fig. 3 is the section of structure of the half single floating-gate memory of a kind of integrated circuit (IC) chip of the present invention and an embodiment of single nonvolatile memory;
Fig. 4 to Fig. 9 is of the present invention by the process chart of first embodiment of half floating-gate memory and the integrated manufacture method on the same chip of nonvolatile memory;
Figure 10 to Figure 14 is of the present invention by the process chart of second embodiment of half floating-gate memory and the integrated manufacture method on the same chip of nonvolatile memory.
Embodiment
Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation.In the drawings, for convenience of description, be exaggerated the thickness in layer and region, shown size does not represent actual size.Reference diagram is the schematic diagram of idealized embodiments of the present invention, and illustrated embodiment should not be considered to the given shape being only limitted to region shown in figure, but comprises obtained shape, such as manufactures the deviation caused.Such as etch the curve obtained and usually have bending or mellow and full feature, but in an embodiment of the present invention, all represent with rectangle, the expression in figure is schematic, but this should not be considered to limit the scope of the invention.In the following description, the term substrate used can be understood as the semiconductor wafer comprised just in processes simultaneously, may comprise other prepared thin layer thereon.
Fig. 2 is the structural representation of an embodiment of a kind of integrated circuit (IC) chip of the present invention.As shown in Figure 2, comprise half floating gate memory array and nonvolatile memory array that are formed on the same semiconductor substrate, also comprise the first input/output terminal and second input/output terminal of connection half floating gate memory array and nonvolatile memory array.Wherein, nonvolatile memory array is any one in nand memory array and NOR memory array.
By the first input/output terminal and the second input/output terminal, exchanges data can be carried out between half floating gate memory array and nonvolatile memory array.Such as the data in nonvolatile memory array or program are read in half floating gate memory array on same chip, for arithmetic processor fast access.Or, the data in half floating gate memory array or program are write back in nonvolatile memory array.That is, with the buffer memory of half floating gate memory array as nonvolatile memory array, accelerate the speed of nonvolatile memory array access data.
As shown in Figure 2, the data control circuit for controlling the transfer of data between half floating gate memory array and nonvolatile memory array is also comprised.
Each nonvolatile memory in nonvolatile memory array comprises two-layer gate dielectric layer, two-layer polysilicon grid and source region and drain region.Each half floating-gate memory in half floating gate memory array comprises two-layer gate dielectric layer, two-layer polysilicon grid and source region and drain region, wherein as floating grid with polysilicon gate be connected by a diode with drain region, the polysilicon gate as control gate at least extends on above-mentioned diode.
Fig. 3 is the section of structure of an embodiment of single half floating-gate memory in integrated half floating gate memory array on the same chip of the present invention and nonvolatile memory array and single nonvolatile memory.As shown in Figure 3, half floating-gate memory 401 and nonvolatile memory 402 that the Semiconductor substrate 200 with the first doping type is formed is included in.Half floating-gate memory 401 and nonvolatile memory 402 are isolated by fleet plough groove isolation structure 300.Half floating-gate memory 401 comprises two-layer gate dielectric layer (ground floor gate dielectric layer 203a and second layer gate dielectric layer 207a), two-layer polysilicon grid (ground floor polysilicon gate 205a and second layer polysilicon gate 208a), the first source region 210 and the first drain region 211.The impurity had in the ground floor polysilicon gate 205a of the first doping type wherein as floating grid can diffuse to the interior formation diffusion region 206 of the dopant well 202 with the second doping type by floating boom opening 204, diffusion region 206 and dopant well 202 form a pn junction diode structure, thus make as floating grid with ground floor polysilicon gate 205a be connected by a diode with the first drain region 211, and at least to extend on above-mentioned diode as the second layer polysilicon gate 208a of control gate.Nonvolatile memory 402 comprises two-layer gate dielectric layer (ground floor gate dielectric layer 203b and second layer gate dielectric layer 207b), two-layer polysilicon grid (ground floor polysilicon gate 205b and second layer polysilicon gate 208b), the second source region 212 and the second drain region 213.The grid curb wall 209 formed by insulating material is formed respectively in the both sides of the second layer polysilicon gate 208a of half floating-gate memory 401 and the second layer polysilicon gate 208b of nonvolatile memory 402.In the integrated circuit (IC) chip be made up of half floating-gate memory 401 and nonvolatile memory 402, also comprise passivation layer 311 and the metal electrode 312 of isolated electrode.
Integrated circuit (IC) chip of the present invention can be manufactured by multiple method, Fig. 4 to Fig. 9 describes the technological process of first embodiment of the manufacture method of integrated circuit (IC) chip of the present invention, wherein, illustrate only single half floating-gate memory and single nonvolatile memory in the drawings.
First, as shown in Figure 4, there is superficial growth one oxide layer 201 of Semiconductor substrate 200 of the first doping type, then deposit photoresist 301 form figure by photoetching process on oxide layer 201, then with photoresist 301 for mask etching oxide layer 301 is to expose Semiconductor substrate 200, then in Semiconductor substrate 200, form the dopant well 202 with the second doping type by the method for ion implantation.Wherein, the first doping type is N-shaped, and the second doping type is p-type, or correspondingly, the first doping type is p-type, and the second doping type is N-shaped.
Next, divest photoresist 301 and oxide layer 201, then at the superficial growth ground floor gate dielectric layer 203 of Semiconductor substrate 200, then deposit one deck photoresist 302 defined the position of the floating boom opening 204 of half floating-gate memory by photoetching process on ground floor gate dielectric layer 203, then be mask etching ground floor gate dielectric layer 203 with photoresist 302, a floating boom opening 204 is formed in ground floor gate dielectric layer 203, floating boom opening 204 be positioned at there is the second doping type dopant well 202 on, as shown in Figure 5.
Next, divest photoresist 302, then the structure deposit ground floor polysilicon 205 formed is covered, then the position of the fleet plough groove isolation structure for isolating device is defined by photoetching process, then be mask etching ground floor polysilicon 205 with photoresist, and continuation etches the ground floor gate dielectric layer 203 and Semiconductor substrate 200 that expose, shallow trench is formed in Semiconductor substrate 200, in shallow trench, form insulating barrier 300 afterwards, insulating barrier 300 makes the dopant well 202 with the second doping type only be positioned at the substrate region of half floating-gate memory.Then carry out ion doping, make the ground floor polysilicon 205 being positioned at half floating-gate memory region have the first doping type, and the ground floor polysilicon 205 being positioned at nonvolatile memory has the second doping type, as shown in Figure 6.
Next, by photoetching process and etching technics, etching of first layer polysilicon 205, form the ground floor polysilicon gate 205a of half floating-gate memory and the ground floor polysilicon gate 205b of nonvolatile memory respectively, wherein the ground floor polysilicon gate 205a of half floating-gate memory covers whole or part floating boom opening 204, and is connected with the dopant well 202 with the second doping type by floating boom opening 204.Wherein, ground floor polysilicon gate 205a covers the structure of whole floating boom opening 204 as shown in Figure 7a, and the structure of ground floor polysilicon gate 205a cover part floating boom opening 204 as shown in Figure 7b.
Next, for the structure shown in Fig. 7 a, etch away the ground floor gate dielectric layer 203 of exposure, then cover the structure formed and form second layer gate dielectric layer 207, and second layer polysilicon is formed on second layer gate dielectric layer 207, then by photoetching process and etching technics etching of second layer polysilicon, form the second layer polysilicon gate 208a of half floating-gate memory and the second layer polysilicon gate 208b of nonvolatile memory respectively, the second layer polysilicon gate 208a of half floating-gate memory at least extend to there is the second doping type dopant well 202 on.Wherein, the second layer polysilicon gate 208a of half floating-gate memory only extends on dopant well 202, only surround the structure of ground floor polysilicon gate 205a in the side of dopant well 202 as shown in Figure 8 a, the second layer polysilicon gate 208a of half floating-gate memory exceeds ground floor polysilicon gate 205a in ground floor polysilicon gate 205a both sides, surrounds the structure of ground floor polysilicon gate 205a as shown in Figure 8 b in its both sides.
All right integrated logical device simultaneously, as when the second layer polysilicon gate of formation half floating-gate memory and nonvolatile memory, can also form the grid 208c of logical device, as shown in Figure 8 c simultaneously.
Finally, grid curb wall 209 is formed respectively in the both sides of the second layer polysilicon gate 208a of half floating-gate memory and the second layer polysilicon gate 208b of nonvolatile memory, and along the edge etching of second layer gate dielectric layer 207 of grid curb wall 209 to expose Semiconductor substrate 200, then in the Semiconductor substrate 200 of the both sides of the second layer polysilicon gate 208a of half floating-gate memory, form the first source region 210 and the first drain region 211 of half floating-gate memory, and in the Semiconductor substrate 200 of the both sides of the second layer polysilicon gate 208b of nonvolatile memory, form the second source region 212 and the second drain region 213 of nonvolatile memory, last deposit passivation layer 311, and contact hole and metal electrode 312 is formed in passivation layer 311, as illustrated in fig. 9.Wherein, the structure of integrated logical device as shown in figure 9b, also comprises the 3rd source region 214 and the 3rd drain region 215 of logical device simultaneously in the chips.
Figure 10 to Figure 14 describes the technological process of second embodiment of the manufacture method of integrated circuit (IC) chip of the present invention, wherein, illustrate only single half floating-gate memory and single nonvolatile memory in the drawings.
First, as shown in Figure 10, in the Semiconductor substrate 200 with the first doping type, form the dopant well 202 with the second doping type.Wherein, the first doping type is N-shaped, and the second doping type is p-type, or correspondingly, the first doping type is p-type, and the second doping type is N-shaped.Then at the superficial growth ground floor gate dielectric layer 203 of Semiconductor substrate 200, then form a floating boom opening 204 at ground floor gate dielectric layer 203, floating boom opening 204 be positioned at there is the second doping type dopant well 202 on.Then the structure deposit ground floor polysilicon 205 formed is covered, and the position of the fleet plough groove isolation structure for isolating device is defined by photoetching process, then be mask etching ground floor polysilicon 205 with photoresist, and continuation etches the ground floor gate dielectric layer 203 and Semiconductor substrate 200 that expose, shallow trench is formed in Semiconductor substrate 200, in shallow trench, form insulating barrier 300 afterwards, insulating barrier 300 makes the dopant well 202 with the second doping type only be positioned at the substrate region of half floating-gate memory.Then carry out ion doping, make the ground floor polysilicon 205 being positioned at half floating-gate memory region have the first doping type, and the ground floor polysilicon 205 being positioned at nonvolatile memory has the second doping type.
Next, by photoetching process and etching technics, etch the ground floor polysilicon 205 be positioned on the dopant well 202 with the second doping type, ground floor polysilicon 205 after etching can be connected with the dopant well 202 with the second doping type by whole or part floating boom opening 204, wherein, the ground floor polysilicon 205 be positioned on dopant well 202 covers the structure of whole floating boom opening 204 as shown in fig. lla, is positioned at the structure of the ground floor polysilicon 205 cover part floating boom opening 204 on dopant well 202 as shown in figure lib.
Next, for the structure shown in Figure 11 b, etch away the ground floor gate dielectric layer 203 exposed, then cover the structure formed and form second layer gate dielectric layer 207, and second layer polysilicon is formed on second layer gate dielectric layer 207, then by photoetching process and etching technics etching of second layer polysilicon, the second layer polysilicon gate 208a of half floating-gate memory and the second layer polysilicon gate 208b of nonvolatile memory is formed respectively.Wherein, the second layer polysilicon gate 208a of half floating-gate memory extend to there is the second doping type dopant well 202 on, as shown in figure 12.
Next, along the edge of the second layer polysilicon gate 208b of the second layer polysilicon gate 208a of half floating-gate memory and nonvolatile memory, etch away the second layer gate dielectric layer 207 and ground floor polysilicon 205 that expose, the dopant well 202 now with the second doping type can be partially etched, after etching, remaining ground floor polysilicon forms the ground floor polysilicon gate 205a of half floating-gate memory and the ground floor polysilicon gate 205b of nonvolatile memory respectively, as shown in figure 13.
Finally, grid curb wall 209 is formed respectively in the both sides of the second layer polysilicon gate 208a of half floating-gate memory and the second layer polysilicon gate 208b of nonvolatile memory, and along the edge etching of second layer gate dielectric layer 207 of grid curb wall 209 to expose Semiconductor substrate 200, then in the Semiconductor substrate 200 of the both sides of the second layer polysilicon gate 208a of half floating-gate memory, form the first source region 210 and the first drain region 211 of half floating-gate memory, and in the Semiconductor substrate 200 of the both sides of the second layer polysilicon gate 208b of nonvolatile memory, form the second source region 212 and the second drain region 213 of nonvolatile memory, last deposit passivation layer 311, and contact hole and metal electrode 312 is formed in passivation layer 311, as shown in figure 14.
The present invention still has numerous embodiments, all employing equivalents or equivalent transformation and all technical schemes formed, and all drops within protection scope of the present invention.
Claims (7)
1. an integrated circuit (IC) chip, is characterized in that, comprising:
A Semiconductor substrate;
Half floating gate memory array formed on the semiconductor substrate and nonvolatile memory array;
For connecting the first input/output terminal and second input/output terminal of described half floating gate memory array and described nonvolatile memory array.
2. a kind of integrated circuit (IC) chip according to claim 1, is characterized in that: also comprise the data control circuit for controlling the transfer of data between described half floating gate memory array and described nonvolatile memory array.
3. a kind of integrated circuit (IC) chip according to claim 1, is characterized in that: described nonvolatile memory array is any one in nand memory array and NOR memory array.
4. a kind of integrated circuit (IC) chip according to claim 1, is characterized in that: isolated by fleet plough groove isolation structure between described half floating gate memory array and described nonvolatile memory array.
5. a manufacture method for integrated circuit (IC) chip according to claim 1, is characterized in that: comprise the following steps:
The dopant well with the second doping type is formed in the Semiconductor substrate with the first doping type;
At the superficial growth ground floor gate dielectric layer of Semiconductor substrate, and in described ground floor gate dielectric layer, form a floating boom opening by photoetching process and etching technics, on the dopant well described in described floating boom opening is positioned at the second doping type;
Cover the structure deposit ground floor polysilicon formed;
The position of the fleet plough groove isolation structure for isolating device is defined by photoetching process;
Take photoresist as ground floor polysilicon described in mask etching, and continue the described ground floor gate dielectric layer of etching and described Semiconductor substrate, shallow trench is formed in described Semiconductor substrate, in described shallow trench, form insulating barrier afterwards, described insulating barrier makes the dopant well with the second doping type only be positioned at the substrate region of half floating-gate memory;
Carry out ion doping, make the described ground floor polysilicon being positioned at half floating-gate memory region have the first doping type, the described ground floor polysilicon being positioned at nonvolatile memory has the second doping type;
By photoetching process and etching technics, etch described ground floor polysilicon, form the ground floor polysilicon gate of half floating-gate memory and nonvolatile memory respectively, the ground floor polysilicon gate of wherein said half floating-gate memory covers the whole or described floating boom opening of part, and is connected with the described dopant well with the second doping type by described floating boom opening;
Etch away the described ground floor gate dielectric layer exposed;
Cover the structure formed and form second layer gate dielectric layer, and second layer polysilicon is formed on second layer gate dielectric layer, then described second layer polysilicon is etched by photoetching process and etching technics, form the second layer polysilicon gate of half floating-gate memory and nonvolatile memory respectively, on the dopant well described in the second layer polysilicon gate of wherein said half floating-gate memory at least extends to the second doping type;
Form grid curb wall respectively in the both sides of the second layer polysilicon gate of described half floating-gate memory and nonvolatile memory, and etch described second layer gate dielectric layer, to expose described Semiconductor substrate along the edge of described grid curb wall;
Source region and the drain region of device is formed in the described Semiconductor substrate of the both sides of the second layer polysilicon gate of described half floating-gate memory and nonvolatile memory;
Deposit passivation layer, and contact hole and metal electrode is formed in described passivation layer.
6. a manufacture method for integrated circuit (IC) chip according to claim 1, is characterized in that, comprises the following steps:
The dopant well with the second doping type is formed in the Semiconductor substrate with the first doping type;
At the superficial growth ground floor gate dielectric layer of Semiconductor substrate, and in described ground floor gate dielectric layer, form a floating boom opening by photoetching process and etching technics, on the dopant well described in described floating boom opening is positioned at the second doping type;
Cover the structure deposit ground floor polysilicon formed;
The position of the fleet plough groove isolation structure for isolating device is defined by photoetching process;
Take photoresist as ground floor polysilicon described in mask etching, and continue the described ground floor gate dielectric layer of etching and described Semiconductor substrate, shallow trench is formed in described Semiconductor substrate, in described shallow trench, form insulating barrier afterwards, described insulating barrier makes the dopant well with the second doping type only be positioned at the substrate region of described half floating-gate memory;
Carry out ion doping, make the described ground floor polysilicon being positioned at half floating-gate memory region have the first doping type, the described ground floor polysilicon being positioned at nonvolatile memory has the second doping type;
By photoetching process and etching technics, etch the described ground floor polysilicon on the dopant well described in being positioned at the second doping type, the described ground floor polysilicon after etching can be connected with the described dopant well with the second doping type by whole or part described floating boom opening;
Etch away the described ground floor gate dielectric layer exposed;
Cover the structure formed and form second layer gate dielectric layer, and second layer polysilicon is formed on second layer gate dielectric layer, then described second layer polysilicon is etched by photoetching process and etching technics, form the second layer polysilicon gate of half floating-gate memory and nonvolatile memory respectively, on the dopant well described in the second layer polysilicon gate of wherein said half floating-gate memory extends to the second doping type;
Along the edge of the second layer polysilicon gate of described half floating-gate memory and nonvolatile memory, etch away the described second layer gate dielectric layer exposed, and continue to etch away the described ground floor polysilicon exposed, after etching, remaining described ground floor polysilicon forms the ground floor polysilicon gate of half floating-gate memory and nonvolatile memory respectively, and the dopant well now with the second doping type is partially etched;
Form grid curb wall respectively in the both sides of the second layer polysilicon gate of described half floating-gate memory and nonvolatile memory, and etch away the described second layer gate dielectric layer exposed, to expose described Semiconductor substrate along the edge of described grid curb wall;
Source region and the drain region of device is formed in the described Semiconductor substrate of the both sides of the second layer polysilicon gate of described half floating-gate memory and nonvolatile memory;
Deposit passivation layer, and contact hole and metal electrode is formed in described passivation layer.
7. the manufacture method of any one integrated circuit (IC) chip according to claim 5 or 6, is characterized in that: the first doping type described is N-shaped, and described the second doping type is p-type; Or the first doping type described is p-type, described the second doping type is N-shaped.
Priority Applications (1)
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