CN104701316A - Double-groove shaped structural semi-floating gate device and manufacturing method thereof - Google Patents
Double-groove shaped structural semi-floating gate device and manufacturing method thereof Download PDFInfo
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Abstract
The invention provides a double-groove shaped structural semi-floating gate device and a manufacturing method thereof. The device comprises an active area, a field oxygen area, a light doping area arranged in the active area, a first groove-shaped area, a dispersing area below a floating gate opening, a second groove-shaped area in a light doping leaking area, a second insulating layer which covers the structure, a control gate on the second insulating layer, a heavy doping source area and a narrow gap heavy doping leakage area, wherein the active area and the field oxygen area are positioned in a semiconductor substrate; two sides of the active area is divided into the light doping leakage and a light doping source area through the first groove-shaped area; a first insulating layer with a floating gate opening, and a floating gate which covers the first groove-shaped area and the floating gate opening are formed in the light doping leakage area; the heavy doping source area and the narrow inhibiting band heavy doping leakage area are arranged at two sides of the sidewall of the control gate. According to the device, the double-gate channel is adopted, so that the space for the device is reduced, and the integrity is improved; with the adoption of the narrow gap material of the leakage electrode, the band-to-band tunneling occurring is increased, and the reading-writing speed of the semi-floating gate device can be increased.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing process technology field, particularly relate to half floating-gate device and the manufacture method thereof of a kind of pair of bathtub construction.
Background technology
Semiconductor memory is used to various electronic applications.Wherein, non-volatility memorizer (Nonvolatile Memory, NVM) can preserve data in the event of a power failure for a long time.Floating transistor (Floating Gate Transistor, FGT) is the predominate architecture of the numerous mutation of non-volatility memorizer.
FGT and mos field effect transistor (Metal Oxide Semiconductor Field EffectTransistor, MOSFET) structural similarity, can regard individual layer gate dielectric layer in MOSFET as and change into " sandwich " grid embedding a charge storage layer (charge storage layer) in dielectric layers (insulator).Wherein, charge storage layer due to by insulating barrier around, be therefore called as floating boom.Stored charge quantity in floating boom can regulate the size of transistor threshold voltage, namely corresponds to " 0 " and " 1 " of logic.Charge injection in floating boom has two kinds of modes: tunnelling (Fowler-Nordheim) and hot carrier in jection.These two kinds of modes all need higher operating voltage, and the injection efficiency of charge carrier is lower, therefore there is power consumption and speed issue.
In order to improve the performance of non-volatility memorizer further, propose half floating transistor (Semi Floating GateTransistor, SFGT) concept, namely the insulating barrier place of drain region and floating transistor opens a window, the discharge and recharge to floating boom is realized by the plane tunneling field-effect transistor (Tunneling Field Effect Transistor, TFET) embedding drain region.Half floating transistor adopts interband tunneling mechanism, greatly reduces the operating voltage of device, and improves the operating rate of device.
Half floating-gate device, as a kind of novel memory device, can be applied and different integrated circuits.It can replace a part of static random access memory (SRAM), improves high speed processor performance; Also can be applied to dynamic random access memory (DRAM) field, improve calculator memory function.
Floating transistor has good application prospect in the high-speed cache (Cache) of CPU, the field such as DRAM and cmos image sensor, and with the obvious advantage.The high-speed cache of such as CPU, usually adopt now 6 MOS transistor to form a memory cell (SRAM), integrated level is low, and area occupied is large.In 28nm Intel XeonCPU, about the area of half is forced to give buffer memory and takies, and greatly wastes resource.Therefore, the sram cell area be made up of half floating transistor (SFGT) is less, and density compares traditional SRAM approximately can improve 10 times.Half floating transistor can also be applied to dynamic random access memory (DRAM) field.Its elementary cell is made up of 1T1C, and namely transistor adds the structure of an electric capacity.Because its electric capacity needs to keep certain quantity of electric charge effectively to store information, minification cannot be continued as MOSFET.Industry manufactures special construction usually electric capacity by digging means such as " deep trouths " reduces its area taken, but along with storage density lifting, technical difficulty and the cost of electric capacity processing increase substantially.Therefore, industry is finding the capacitorless part technology that may be used for manufacturing DRAM always, and the DRAM that half floating transistor is formed just can realize traditional DRAM repertoire without the need to capacitor, and not only cost significantly reduces, and integrated level is higher, and read or write speed is faster.
Fig. 1 is the semiconductor memory of a kind of planar channeling of prior art, comprise: in Semiconductor substrate 100, form source region 102 and the drain region 103 with Semiconductor substrate opposite dopant type, Semiconductor substrate 100 can be monocrystalline silicon, polysilicon or isolate supports.In Semiconductor substrate 100, between source region 102 and drain region 103, be formed with the planar channeling district 116 of device, planar channeling district 116 is inversion layers of this semiconductor memory formation when carrying out work.In source region 102 and drain region 103, also form doped region 111 and the doped region 112 of high-dopant concentration respectively, doped region 111 and doped region 112 have identical doping type with source region and drain region.
Ground floor insulating barrier 104 is formed on source region 102, channel region 116 and drain region 103, and on drain region 103, form ground floor insulating barrier 104 and floating boom opening 105 forms a floating boom 107 as charge-storage node, floating boom 107 has the doping type contrary with drain region 103, and impurity can be diffused in drain region 103 by floating boom opening 105 and forms diffusion region 106 in floating boom 107, thus between floating boom 107 and drain region 103, form a PN junction diode by floating boom opening 105.
Cover floating boom 107 and described PN junction diode structure be formed second layer insulating barrier 108 on second layer insulating barrier 108, cover and surround the control gate 109 that floating boom 107 is formed with device.Side wall 110 is also formed in the both sides of control gate 109.This semiconductor memory also comprise formed by electric conducting material the contact 113 for source region that source region 102, control gate 109, drain region 103, Semiconductor substrate 100 are connected with outer electrode, the contact 114 of control gate, drain contact 115 and substrate contact 116.
For N-type half floating-gate device, when control gate 109 applies back bias voltage and drain region 103 applies positive bias, diffusion region 106, drain region 103 form an embedded plane tunneling field-effect transistor (TFET) with doped region, drain region 112, now embed TFET raceway groove and form P type raceway groove, and interband tunnelling is there is between drain region 103 and drain diffusion regions 112, now electric current flows among half floating boom 107 by doped region, drain region 112 through raceway groove, electric charge in half floating boom increases, and this process is write logical one; When control gate 109 applies positive bias and drain region 103 applies back bias voltage, the PN junction diode positively biased that diffusion region 106 and drain region 103 are formed, make the electric charge release stored in half floating boom 107, the electric charge in half floating boom reduces, and this process is the process of write logical zero.Such charge injection and dispose procedure are different from conventional floating gate devices function pattern, and the operating voltage of device is reduced greatly, and storage speed improves.
But half floating transistor SFGT of prior art as shown in Figure 1 has following defect:
1, device is planar channeling device, needs to occupy more Substrate Area and causes the integration density of chip to reduce.
2, the tunneling field-effect transistor TFET embedded is planar structure, and chip area increase causes integrated level to reduce; Under generation tunnelling, leak electricity higher.
The higher incidence of interband tunnelling that causes of tunneling field-effect transistor TFET energy gap of the silicon materials 3, embedded is not high, causes device storage speed to reduce.
Summary of the invention
The object of the invention is to make up above-mentioned the deficiencies in the prior art, provide half floating-gate device and the manufacture method thereof of a kind of pair of bathtub construction, device area occupied is less, and interband tunnelling incidence is larger, also effectively can prevent element leakage.
For achieving the above object, the invention provides half floating-gate device of a kind of pair of bathtub construction, it comprises:
There is the Semiconductor substrate of the first doping type;
The Chang Yang district for device isolation formed in described Semiconductor substrate, Chang Yang is formed with source region between district;
The light dope source region with the second doping type formed in described Semiconductor substrate active area and lightly doped drain;
The first channel region formed between described light dope source region and lightly doped drain, for the formation of flute profile raceway groove, the degree of depth of described first channel region is greater than the degree of depth of described light dope source region, lightly doped drain;
Cover the first insulating barrier that described light dope source region, lightly doped drain and flute profile raceway groove are formed;
Near the floating boom opening that the first insulating barrier place of flute profile raceway groove is formed above described lightly doped drain;
Cover the floating boom of the first doping type of described first insulating barrier and the formation of floating boom opening;
The diffusion region with the first doping type formed in lightly doped drain below described floating boom opening;
The second channel region formed in the lightly doped drain do not covered by described floating boom, the degree of depth of described second channel region is less than the described lightly doped drain degree of depth;
Cover the second insulating barrier that described light dope source region, lightly doped drain, floating boom and the second channel region surface are formed;
Cover the control gate of the second doping type and the side wall of both sides thereof of described second insulating barrier formation;
The heavy doping source region formed in the light dope source region and lightly doped drain of described control gate both sides and heavy doping drain region, described heavy doping drain region is small gap material, and described second channel region is between described diffusion region and heavy doping drain region;
And described heavy doping source region, heavy doping drain region, control gate and Semiconductor substrate extraction pole.
Further, described small gap material is SiGe.
Further, the first doping type described is N-type, and described the second doping type is P type; Or the first doping type described is P type, described the second doping type is N-type.The impurity of the first doping type described can be boron, boron difluoride or indium.
Further, described first insulating barrier and the second insulating barrier are silicon dioxide, silicon nitride, silicon oxynitride or high dielectric constant material, described floating boom is the polysilicon of the first doping type doping, and described control gate is polysilicon, the metal or alloy of the doping of the second doping type.
Further, described floating boom to be connected with described lightly doped drain by described floating boom opening and to form PN junction diode, described PN junction diode, the second insulating barrier and control gate form the gate control diode using control gate as grid, the anode of described gate control diode is connected with described floating boom, and the negative electrode of described gate control diode is connected with described lightly doped drain.
The present invention also provides a kind of manufacture method of half floating-gate device of above-mentioned pair of bathtub construction, and it comprises the following steps:
Step S01, in the Semiconductor substrate with the first doping type, form the Chang Yang district for device isolation, Chang Yang is formed with source region between district;
Step S02, forms the light doping section with the second doping type in described active area;
Step S03, the first channel region is formed by photoetching and etching technics in described light doping section, for the formation of flute profile raceway groove, the degree of depth of described first channel region is greater than the degree of depth of described light doping section, and forms light dope source region and lightly doped drain in described flute profile raceway groove both sides;
Step S04, the first insulating barrier is grown at described semiconductor substrate surface, described first insulating barrier covers described light dope source region, lightly doped drain and flute profile raceway groove, and the first insulating barrier place etching near flute profile raceway groove above described lightly doped drain forms floating boom opening to expose lightly doped drain;
Step S05, there is in described semiconductor substrate surface deposit the first conductive layer of the first doping type, and the floating boom of device is defined by chemical wet etching, described floating boom covers described first insulating barrier and floating boom opening, and forms the diffusion region with the first doping type in lightly doped drain below described floating boom opening;
Step S06, forms the second channel region by photoetching and etching technics in the lightly doped drain do not covered by described floating boom, and the degree of depth of described second channel region is less than the described lightly doped drain degree of depth;
Step S07, grows the second insulating barrier at described semiconductor substrate surface, and described second insulating barrier covers described light dope source region, lightly doped drain, floating boom and the second channel region;
Step S08, deposit second conductive layer on described second insulating barrier, and the control gate of device is defined by chemical wet etching, and form side wall in described control gate both sides;
Step S09, carries out the ion implantation of the second doping type, forms heavy doping source region and heavy doping drain region to described control gate and the light dope source region do not covered by control gate, lightly doped drain;
Step S10, is not formed drain recesses by the heavy doping drain region that control gate covers by photoetching and etching technics etching;
Step S11, grows small gap material in described drain recesses, and carries out the ion implantation of the second doping type, forms the low energy gap heavy doping drain region with the second doping type;
Step S12, forms the extraction pole of described heavy doping source region, heavy doping drain region, control gate and Semiconductor substrate.
Further, described small gap material is SiGe.
Further, the first doping type described is N-type, and described the second doping type is P type; Or the first doping type described is P type, described the second doping type is N-type.
Further, described first insulating barrier and the second insulating barrier are silicon dioxide, silicon nitride, silicon oxynitride or high dielectric constant material, described floating boom is the polysilicon of the first doping type doping, and described control gate is polysilicon, the metal or alloy of the doping of the second doping type.
Half floating-gate device of provided by the invention pair of bathtub construction and manufacture method thereof, have following technique effect:
1. have flute profile raceway groove, device area occupied is less, and integrated level improves, and is applicable to below 45nm technique.
2. the tunneling field-effect transistor TFET area occupied that the flute profile formed by the second channel region embeds is little, reduces device area, provides the integration density of chip, leak electricity less.
3. preferably adopt SiGe heavy doping drain region, less compared with silicon materials energy gap, the incidence of interband tunnelling is larger, improves the read or write speed of half floating-gate device.
4., owing to adopting SiGe small gap material that electric leakage may be made to increase in preferred embodiment, electric leakage can be reduced by embedding flute profile TFET simultaneously.
Accompanying drawing explanation
For can clearer understanding objects, features and advantages of the present invention, below with reference to accompanying drawing, preferred embodiment of the present invention be described in detail, wherein:
Fig. 1 is the cross-sectional view of half floating transistor of prior art;
The cross-sectional view of Fig. 2 the present invention half floating-gate device;
Fig. 3 is the schematic flow sheet of the present invention half floating-gate device manufacture method;
Fig. 4 to Figure 16 is each step structural representation of the present invention half floating-gate device manufacture method.
Embodiment
For making content of the present invention clearly understandable, below in conjunction with Figure of description, content of the present invention is described further.Certain the present invention is not limited to this specific embodiment, and the general replacement known by those skilled in the art is also encompassed in protection scope of the present invention.
It should be noted that, in following embodiment, when describing embodiments of the present invention in detail, in order to clearly represent structure of the present invention so that explanation, special to the structure in accompanying drawing not according to general scale, and carried out partial enlargement, distortion and simplify processes, shown structure size does not represent actual size.Meanwhile, accompanying drawing is the schematic diagram of idealized embodiments of the present invention, and illustrated embodiment should not be considered to the given shape being only limitted to region shown in figure, but comprises obtained shape, the deviation etc. caused in such as manufacturing.Such as, etch the curve obtained and there is bending or mellow and full feature usually, but in an embodiment of the present invention, for convenience of description, all represent with rectangle.Therefore, should avoid being understood in this, as limitation of the invention.
Refer to Fig. 2, half floating-gate device of two bathtub constructions of the present embodiment, it comprises:
There is the Semiconductor substrate 200 of the first doping type;
Source region is formed between the district of Chang Yang district 201, Chang Yang 201 for device isolation formed in Semiconductor substrate 200;
The light dope source region 202 with the second doping type formed in Semiconductor substrate 200 active area and lightly doped drain 203;
The first channel region formed between light dope source region 202 and lightly doped drain 203, the first channel region is for the formation of flute profile raceway groove 204, and its degree of depth is greater than the degree of depth of light dope source region 202, lightly doped drain 203;
The first insulating barrier 205, first insulating barrier 205 that covering light dope source region 202, lightly doped drain 203 and flute profile raceway groove 204 are formed covers bottom surface and the sidewall of flute profile raceway groove 204;
Near the floating boom opening 206 that the first insulating barrier 205 place of flute profile raceway groove 204 is formed above lightly doped drain 203;
Cover the floating boom 207 of the first doping type of the first insulating barrier 205 and floating boom opening 206 formation, floating boom 207 all fills flute profile raceway groove 204;
The diffusion region 208 with the first doping type formed in lightly doped drain below floating boom opening 206;
The second channel region 209 formed in the lightly doped drain 203 do not covered by floating boom 207, for the formation of embedding TFET channel region, the degree of depth of the second channel region 209 is less than the degree of depth of lightly doped drain 203;
Cover the second insulating barrier 210 that light dope source region 202, lightly doped drain 203, floating boom 207 and the second channel region 209 surface are formed;
Cover the control gate 211 of the second doping type and the side wall 212 of both sides thereof of the second insulating barrier 210 formation;
The heavy doping source region 213 formed in light dope source region, control gate 211 both sides 202 and lightly doped drain 203 and heavy doping drain region, wherein, heavy doping drain region is that low energy gap heavy doping drain region 214 ', the second channel region 209 is positioned between diffusion region 208 and low energy gap heavy doping drain region 214 ';
And heavy doping source region 213, low energy gap heavy doping drain region 214 ', control gate 211 and Semiconductor substrate 200 extraction pole: source electrode 231, drain electrode 232, control gate 233 and underlayer electrode 234.
Double flute shape half floating-gate device of the present embodiment has flute profile raceway groove, and device area occupied is less, and integrated level improves, and is applicable to below 45nm technique; Form embedding flute profile tunneling field-effect transistor TFET area occupied by the second channel region little, reduce device area, the integration density of chip is provided, leaks electricity less.
Wherein, in the present embodiment, low-gap semiconductor material is preferably selected in heavy doping drain region, as SiGe etc.Owing to adopting SiGe etc. as heavy doping drain region, less compared with silicon materials energy gap, the incidence of interband tunnelling is larger, improves the read or write speed of half floating-gate device.But, owing to adopting the small gap materials such as SiGe that electric leakage may be made to increase, electric leakage can be reduced by the embedding flute profile TFET of the present embodiment simultaneously.
In the present embodiment, Semiconductor substrate can be monocrystalline silicon, polysilicon or isolate supports.The first doping type of the present embodiment is P type, and the second doping type is N-type; In other embodiments, the first doping type is N-type, and the second doping type is P type.Preferably, the impurity of the first doping type can be boron, boron difluoride or indium.
First insulating barrier of the present embodiment and the second insulating barrier can be silicon dioxide, silicon nitride, silicon oxynitride or high dielectric constant material, floating boom can be the polysilicon of the first doping type doping, and control gate can be polysilicon, the metal or alloy of the second doping type doping.
In the present embodiment, floating boom 207 to be connected with lightly doped drain 203 by floating boom opening 206 and to form PN junction diode, impurity in floating boom 207 can by floating boom opening 206 by forming the diffusion region 208 of the first doping type in High temperature diffusion to lightly doped drain 203, thus make diffusion region 208 and lightly doped drain 203 form a PN junction diode.PN junction diode, the second insulating barrier and control gate form the gate control diode using control gate as grid, and the anode of gate control diode is connected with described floating boom, and the negative electrode of gate control diode is connected with described lightly doped drain.
Please ask to read Fig. 3 and combine and consult Fig. 4 to 16, the manufacture method embodiment of above-mentioned half floating-gate device comprises the following steps:
Step S01, as shown in Figure 4, by being formed with source region between the district of Chang Yang district 201, Chang Yang 201 of shallow trench isolation STI technique formation for device isolation in the Semiconductor substrate 200 with the doping of P type, wherein Semiconductor substrate can be monocrystalline silicon, polysilicon or isolate supports;
Step S02, as shown in Figure 5, forms the light doping section with N-type doping in the active area of Semiconductor substrate 200 by photoetching process and ion implantation technology;
Particularly, this step is included in Semiconductor substrate 200 surface and forms one deck hard mask layer and photoresist layer successively; Through photoetching and etching technics, in photoresist layer and hard mask layer, form light dope source region and lightly doped drain pattern; With photoresist and hard mask layer for mask, in active area, inject N-type Doped ions, thus in active area, form the lightly doped source region 202 of N-type and lightly doped drain 203; The lightly doped source region 202 of N-type and lightly doped drain 203 are respectively near the Chang Yang district 201 of Semiconductor substrate both sides; Finally, photoresist layer and hard mask layer is removed;
Step S03, as shown in Figure 6, at Semiconductor substrate 200 surface deposition one deck hard mask layer and photoresist, the hard mask layer of exposure is etched away by mask, and be the method that mask is combined by wet etching and dry etching with hard mask layer, the first channel region that the substrate exposed forms groove is etched in light doping section, for the formation of flute profile raceway groove 204, and form two parts in flute profile raceway groove 204 both sides, as light dope source region 202 and the lightly doped drain 203 of device, wherein, the degree of depth of flute profile raceway groove must be greater than the degree of depth of light doping section;
Step S04, as shown in Figure 7, after stripping photoresist also etching residue hard mask layer, at Semiconductor substrate 200 superficial growth first insulating barrier 205, first insulating barrier 205 covers light dope source region 202, lightly doped drain 203 and flute profile raceway groove 204, subsequently, as shown in Figure 8, the first insulating barrier 205 place etching near flute profile raceway groove 204 above lightly doped drain 203 forms floating boom opening 206 to expose lightly doped drain 203, it is specifically included in deposit one deck photoresist on the first insulating barrier 205 and passes through photoetching, developing process defines, the position of floating boom opening, then be the first insulating barrier 205 that mask etching falls to expose with photoresist, to form floating boom opening 206, finally peel off photoresist, wherein, the first insulating barrier can be the insulating material of the high-ks such as silica, silicon nitride, silicon oxynitride, and thickness is 1-40 nanometer,
Step S05, as shown in Figure 9, there is the polysilicon of P type doping as the first conductive layer at Semiconductor substrate 200 surface deposition, and the floating boom 207 of device is defined by chemical wet etching first conductive layer, floating boom 207 covers the first insulating barrier 205 and floating boom opening 206, and form diffusion region 208 in lightly doped drain below floating boom opening 206, it comprises particularly: depositing polysilicon fills whole flute profile raceway groove 204 and floating boom opening 206, then deposit photoresist defined the position of floating boom by photoetching process on the polysilicon, be the floating boom 207 that mask etching falls that unnecessary polysilicon forms device again with photoresist, in floating boom 207, impurity can pass through floating boom opening 206 High temperature diffusion to lightly doped drain 203 to form p type diffusion region 208, as shown in Figure 9, and between floating boom 207 and lightly doped drain 203, form a PN junction diode by floating boom opening 206,
Step S06, as shown in Figure 10, continue to click the hard mask of one deck and photoresist at semiconductor substrate surface, the second channel region 209 in the lightly doped drain exposed do not covered by floating boom 207 is defined by photoetching and etching technics, wherein, the degree of depth of the second channel region 209 must be less than the degree of depth of light doping section (herein lightly doped drain), for the formation of embedding TFET channel region;
Step S07, as shown in figure 11, covers light dope source region 202, lightly doped drain 203, floating boom 207 and the second channel region 209 at Semiconductor substrate 200 superficial growth second insulating barrier 210, second insulating barrier 210; Wherein, the second insulating barrier can be the insulating material of the high-ks such as silica, silicon nitride, silicon oxynitride, and thickness is 1-40 nanometer;
Step S08, as shown in figure 12, on the second insulating barrier 210, the polysilicon of deposit N-type doping is as the second conductive layer, and the control gate 211 of device is defined by chemical wet etching, then etch away and be exposed to outer polysilicon, wherein, control gate 211 should be greater than floating boom 207 in orientation, cover completely and surround floating boom 207, and forming side wall 212 in control gate 211 both sides; Particularly, deposit the 3rd insulating barrier on semiconductor substrate 200, deposit one deck photoresist on the 3rd insulating barrier also forms figure by photoetching process, then the 3rd insulating barrier exposed is etched away, and continue to etch away the second layer insulating barrier exposed, after etching, remaining 3rd insulating barrier forms side wall 212 in control gate 211 both sides, as shown in figure 13, wherein, the 3rd insulating barrier can be silica or silicon nitride;
Step S09, as shown in figure 13, control gate 211 and the light dope source region 202 do not covered by control gate, lightly doped drain 203 are carried out to the ion implantation of N-type doping, form heavy doping source region 213 and the heavy doping drain region 214 of high concentration in light dope source region 202 and lightly doped drain 203;
Step S10, as shown in figure 14, forming body structure surface deposit one deck silicon nitride hard mask and photoresist, by photoetching and etching technics, etches away the heavy doping drain region do not covered by control gate 211, forms drain recesses 220;
Step S11, as shown in figure 15, by selective epitaxial process in drain recesses 220, growth SiGe, carries out the ion implantation of N-type doping subsequently, forms low energy gap heavy doping drain region 214 ';
Step S12, as shown in figure 16, with electric conducting material by metallization process respectively in heavy doping source region, heavy doping drain region, control gate form with Semiconductor substrate the extraction pole be connected with external electrode, i.e. source electrode 231, drain electrode 232, control gate 233 and underlayer electrode 234.
Although the present invention discloses as above with preferred embodiment; right described embodiment is citing for convenience of explanation only; and be not used to limit the present invention; those skilled in the art can do some changes and retouching without departing from the spirit and scope of the present invention, and the protection range that the present invention advocates should be as the criterion with described in claims.
Claims (10)
1. half floating-gate device of two bathtub construction, it is characterized in that, it comprises:
There is the Semiconductor substrate of the first doping type;
The Chang Yang district for device isolation formed in described Semiconductor substrate, Chang Yang is formed with source region between district;
The light dope source region with the second doping type formed in described Semiconductor substrate active area, lightly doped drain;
The first channel region formed between described light dope source region and lightly doped drain, for the formation of flute profile raceway groove, the degree of depth of described first channel region is greater than the degree of depth of described light dope source region, lightly doped drain;
Cover the first insulating barrier that described light dope source region, lightly doped drain and flute profile raceway groove are formed;
Near the floating boom opening that the first insulating barrier place of flute profile raceway groove is formed above described lightly doped drain;
Cover the floating boom of the first doping type of described first insulating barrier and the formation of floating boom opening;
The diffusion region with the first doping type formed in lightly doped drain below described floating boom opening;
The second channel region formed in the lightly doped drain do not covered by described floating boom, the degree of depth of described second channel region is less than the described lightly doped drain degree of depth;
Cover the second insulating barrier that described light dope source region, lightly doped drain, floating boom and the second channel region surface are formed;
Cover the control gate of the second doping type and the side wall of both sides thereof of described second insulating barrier formation;
The heavy doping source region formed in the light dope source region and lightly doped drain of described control gate both sides and heavy doping drain region, described heavy doping drain region is small gap material, and described second channel region is between described diffusion region and heavy doping drain region;
And described heavy doping source region, heavy doping drain region, control gate and Semiconductor substrate extraction pole.
2. half floating-gate device according to claim 1, is characterized in that: described small gap material is SiGe.
3. half floating-gate device according to claim 2, it is characterized in that: described first insulating barrier and the second insulating barrier are silicon dioxide, silicon nitride, silicon oxynitride or high dielectric constant material, described floating boom is the polysilicon of the first doping type doping, and described control gate is polysilicon, the metal or alloy of the doping of the second doping type.
4. half floating-gate device according to claim 2, it is characterized in that: described floating boom to be connected with described lightly doped drain by described floating boom opening and to form PN junction diode, described PN junction diode, the second insulating barrier and control gate form the gate control diode using control gate as grid, the anode of described gate control diode is connected with described floating boom, and the negative electrode of described gate control diode is connected with described lightly doped drain.
5. half floating-gate device according to any one of Claims 1-4, is characterized in that: the first doping type described is N-type, and described the second doping type is P type; Or the first doping type described is P type, described the second doping type is N-type.
6. a manufacture method for half floating-gate device of two bathtub construction described in claim 1, it is characterized in that, it comprises the following steps:
Step S01, in the Semiconductor substrate with the first doping type, form the Chang Yang district for device isolation, Chang Yang is formed with source region between district;
Step S02, forms the light doping section with the second doping type in described active area;
Step S03, the first channel region is formed by photoetching and etching technics in described light doping section, for the formation of flute profile raceway groove, the degree of depth of described first channel region is greater than the degree of depth of described light doping section, and forms light dope source region and lightly doped drain in described flute profile raceway groove both sides;
Step S04, the first insulating barrier is grown at described semiconductor substrate surface, described first insulating barrier covers described light dope source region, lightly doped drain and flute profile raceway groove, and the first insulating barrier place etching near flute profile raceway groove above described lightly doped drain forms floating boom opening to expose lightly doped drain;
Step S05, there is in described semiconductor substrate surface deposit the first conductive layer of the first doping type, and the floating boom of device is defined by chemical wet etching, described floating boom covers described first insulating barrier and floating boom opening, and forms the diffusion region with the first doping type in lightly doped drain below described floating boom opening;
Step S06, forms the second channel region by photoetching and etching technics in the lightly doped drain do not covered by described floating boom, and the degree of depth of described second channel region is less than the described lightly doped drain degree of depth;
Step S07, grows the second insulating barrier at described semiconductor substrate surface, and described second insulating barrier covers described light dope source region, lightly doped drain, floating boom and the second channel region;
Step S08, deposit second conductive layer on described second insulating barrier, and the control gate of device is defined by chemical wet etching, and form side wall in described control gate both sides;
Step S09, carries out the ion implantation of the second doping type, forms heavy doping source region and heavy doping drain region to described control gate and the light dope source region do not covered by control gate, lightly doped drain;
Step S10, is not formed drain recesses by the heavy doping drain region that control gate covers by photoetching and etching technics etching;
Step S11, grows small gap material in described drain recesses, and carries out the ion implantation of the second doping type, forms the low energy gap heavy doping drain region with the second doping type;
Step S12, forms the extraction pole of described heavy doping source region, heavy doping drain region, control gate and Semiconductor substrate.
7. half floating-gate device manufacture method according to claim 6, is characterized in that: described small gap material is SiGe.
8. half floating-gate device manufacture method according to claim 7, is characterized in that: described first insulating barrier and the second insulating barrier are silicon dioxide, silicon nitride, silicon oxynitride or high dielectric constant material.
9. half floating-gate device manufacture method according to claim 7, is characterized in that: described floating boom is the polysilicon of the first doping type doping, and described control gate is polysilicon, the metal or alloy of the doping of the second doping type.
10. half floating-gate device manufacture method according to any one of claim 6 to 9, is characterized in that: the first doping type described is N-type, and described the second doping type is P type; Or the first doping type described is P type, described the second doping type is N-type.
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