CN114220741A - Semi-floating gate transistor with split-gate structure and preparation method thereof - Google Patents

Semi-floating gate transistor with split-gate structure and preparation method thereof Download PDF

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Publication number
CN114220741A
CN114220741A CN202111414300.0A CN202111414300A CN114220741A CN 114220741 A CN114220741 A CN 114220741A CN 202111414300 A CN202111414300 A CN 202111414300A CN 114220741 A CN114220741 A CN 114220741A
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gate
well region
semi
layer
region
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晁鑫
王晨
陈琳
孙清清
张卫
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Fudan University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42328—Gate electrodes for transistors with a floating gate with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42336—Gate electrodes for transistors with a floating gate with one gate at least partly formed in a trench
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate

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Abstract

The invention discloses a semi-floating gate transistor with a split gate structure and a preparation method thereof. The semi-floating gate transistor with the split gate structure comprises a substrate, wherein a P well region, an N well region and a U-shaped groove are formed in the substrate, the N well region is positioned above the P well region, and the U-shaped groove penetrates through the N well region; the first gate oxide layer is formed on the surface of the U-shaped groove, extends to cover part of the surface of the N well region, and is provided with a window on one side; the semi-floating gate covers the first gate oxide layer, completely fills the U-shaped groove, and is contacted with the N well region at the window; the control gate dielectric layer covers the semi-floating gate, and the control gate and the mask layer are sequentially formed on the control gate dielectric layer; the isolation gate dielectric layer is formed on the surface of the N well region and extends to cover part of the surface of the mask layer, and the isolation gate covers the isolation gate dielectric layer and fills the isolation gate region; and the source region and the drain region are respectively formed on two sides of the control gate and the separation gate and in the N well region.

Description

Semi-floating gate transistor with split-gate structure and preparation method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semi-floating gate transistor with a split gate structure and a preparation method thereof.
Background
The semi-floating gate transistor is used as a novel storage device, an embedded tunneling transistor (TFET) is integrated in a CMOS process, the charge writing in a semi-floating gate region is completed by band-band tunneling of carriers when the TFET is started, the charge erasing is completed by forward bias of PN junctions formed by a floating gate window and an N well region, all functions of the DRAM with the traditional 1T1C structure can be realized without capacitance in the erasing process, the cost is greatly reduced, the reading and writing speed is higher, and the semi-floating gate transistor is one of devices with strong competitiveness in the field of the DRAM in the future.
However, for the conventional semi-floating gate transistor structure and the operating voltage thereof, the negative pressure difference between the control gate and the drain terminal in the holding state causes a weak programming process during holding, so that the conventional semi-floating gate transistor cannot be held for a long time. The good retention characteristics mean that the device can have lower power consumption, so how to improve the structure of the device to eliminate the weak programming process of the retention state from the structure of the device, and greatly improving the charge retention capability of the semi-floating gate transistor is an important and practical research subject.
Disclosure of Invention
The invention discloses a preparation method of a semi-floating gate transistor with a split gate structure, which comprises the following steps: injecting ions into the substrate to form a P well region and an N well region, wherein the N well region is formed above the P well region and etched to form a U-shaped groove which penetrates through the N well region; forming a first gate oxide layer and a semi-floating gate, wherein the first gate oxide layer covers the surface of the U-shaped groove and part of the surface of the N well region, and a window is formed on the surface of the N well region outside the U-shaped groove; the semi-floating gate covers the first gate oxide layer and is in surface contact with the N well region at the window; depositing a second gate oxide layer, a second polysilicon layer and a mask layer, carrying out edge etching, and etching a control gate region and a separation gate region; depositing a separation gate dielectric layer to cover the surface of the device, depositing a third polysilicon layer to cover the separation gate dielectric layer and completely fill the separation gate region, and performing edge etching and middle etching to form a control gate, a separation gate and a source drain region; and forming a side wall, performing source-drain ion implantation, and simultaneously realizing N-type ion doping on the third polycrystalline silicon layer and the first polycrystalline silicon layer to form the semi-floating gate transistor with the split gate structure.
The invention discloses a preparation method of a semi-floating gate transistor with a split-gate structure, preferably, the steps of forming a first gate oxide layer and a semi-floating gate comprise: depositing a first gate oxide layer and a first polysilicon layer in the semi-floating gate region; etching to remove part of the first gate oxide layer on the outer side of the U-shaped groove, so that part of the surface of the N well region is exposed to form a window; and then backfilling part of the first polycrystalline silicon layer, carrying out ion implantation of the semi-floating gate region, and carrying out chemical mechanical polishing on the first polycrystalline silicon layer to form the semi-floating gate.
The invention also discloses a semi-floating gate transistor with a split gate structure, which comprises: the semiconductor device comprises a substrate, a first substrate and a second substrate, wherein a P well region, an N well region and a U-shaped groove are formed in the substrate, the N well region is located above the P well region, and the U-shaped groove penetrates through the N well region; the first gate oxide layer is formed on the surface of the U-shaped groove, extends to cover part of the surface of the N well region, and is provided with a window on one side; the semi-floating gate covers the first gate oxide layer, completely fills the U-shaped groove, and is contacted with the N well region at the window; the control gate dielectric layer covers the semi-floating gate, and the control gate and the mask layer are sequentially formed on the control gate dielectric layer; the isolation gate dielectric layer is formed on the surface of the N well region and extends to cover part of the surface of the mask layer, and the isolation gate covers the isolation gate dielectric layer and fills the isolation gate region; and the source region and the drain region are respectively formed on two sides of the control gate and the separation gate and in the N well region.
In the semi-floating gate transistor with the split-gate structure, preferably, the separation gate dielectric layer is silicon nitride, and the separation gate is polysilicon.
In the semi-floating gate transistor with the split-gate structure, preferably, the separation gate dielectric layer is a high-K dielectric, and the separation gate is made of metal.
According to the invention, the traditional single control gate is divided into a control gate and a unique separation gate, so that the weak programming process in a holding state can be effectively eliminated, the holding characteristics of devices at normal temperature and high temperature are greatly improved, and lower power consumption and good storage characteristics are realized. .
Drawings
Fig. 1 is a flow chart of a method for manufacturing a semi-floating gate transistor with a split-gate structure.
Fig. 2 to fig. 11 are schematic diagrams of the staged structures of the steps of the method for manufacturing the semi-floating gate transistor with the split-gate structure.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clearly and completely understood, the technical solutions in the embodiments of the present invention will be described below with reference to the accompanying drawings in the embodiments of the present invention, and it should be understood that the specific embodiments described herein are only for explaining the present invention and are not intended to limit the present invention. The described embodiments are only some embodiments of the invention, not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "upper", "lower", "vertical", "horizontal", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Furthermore, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described below in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details. Unless otherwise specified below, each part in the device may be formed of a material known to those skilled in the art, or a material having a similar function developed in the future may be used.
Fig. 1 is a flow chart of a method for manufacturing a semi-floating gate transistor with a split-gate structure. As shown in fig. 1, the method for manufacturing a semi-floating gate transistor with a split-gate structure comprises the following steps:
step S1, after completing the basic Shallow Trench Isolation (STI) process on the substrate, depositing a pad oxide layer 101, and ion-implanting to form a P-well region 100 and an N-well region 102, where the N-well region 102 is formed above the P-well region 100, and the resulting structure is shown in fig. 2. Then, a first silicon nitride layer is deposited to form a hard mask, etching is performed on the U-shaped groove, the formed U-shaped groove penetrates through the N-well region 102, and then the hard mask is removed, so that the structure is shown in fig. 3.
Step S2, depositing the first gate oxide layer 103 and the first polysilicon layer 104 in the semi-floating gate region, so that the first polysilicon layer 104 covers the first gate oxide layer 103 and completely fills the U-shaped groove. And then, etching the semi-floating gate window, and removing part of the first polysilicon layer 104 and the first gate oxide layer 103 outside the U-shaped groove by etching to expose part of the surface of the N well region to form a window, wherein the obtained structure is shown in FIG. 4. Then, a portion of the first polysilicon layer is backfilled, ion implantation of the semi-floating gate region is performed, and Chemical Mechanical Polishing (CMP) is performed on the first polysilicon layer 104 to a certain height to form a semi-floating gate, and the resulting structure is shown in fig. 5.
Step S3, as shown in fig. 6 and 7, after the formation of the semi-floating gate region, deposits the second gate oxide layer 105 and the second polysilicon layer 106, and then deposits the second silicon nitride layer 107 as a mask layer for etching the second polysilicon layer 106. And etching the edge to remove the mask layer at the edge, the second polysilicon layer 106, the second gate oxide layer 105, the first polysilicon layer 104 and the first gate oxide layer 103, and etching out a control gate region and a separation gate region.
Step S4, depositing a separate gate dielectric layer, depositing a third silicon oxide layer 108 with a certain thickness, and depositing a third silicon nitride layer 109 to form a separate gate dielectric layer. After the separation gate dielectric layer is formed, the third polysilicon layer 110 is filled to cover the separation gate dielectric layer and fill the separation gate region, and the resulting structure is shown in fig. 8. As shown in fig. 9 and 10, edge etching and middle etching are performed to form independent control gate, separate gate and source/drain regions. Specifically, edge etching is performed first, and the third polysilicon layer 110 and the split gate dielectric layer at the edge are removed, so that the source and drain regions at the two sides are exposed. And simultaneously, the third polysilicon layer 110 and the separation gate dielectric layer in the middle region are etched and removed, so that part of the surface of the second silicon nitride layer 107 is exposed. And then, continuing to perform second intermediate etching to remove part of the second silicon nitride layer 107, the second polysilicon layer 106, the second gate oxide layer 105, the first polysilicon layer 104 and the first gate oxide layer 103 in the intermediate region, so that part of the surface of the N well region 102 in the intermediate region is exposed. Then, silicon oxide and silicon nitride are deposited isotropically, and the spacers 111 are formed by anisotropic etching.
Step S5, performing source-drain ion implantation to form source regions 112 and 113 at the outer side of the split gate, i.e., the edge region, and a drain region 114 between the control gates, i.e., the middle region, while implementing N-type ion doping on the second polysilicon layer and the third polysilicon layer, and finally forming a semi-floating gate transistor with a split gate structure, where the resulting structure is shown in fig. 11.
The above description has been made by taking polysilicon as an example of the separation gate, but the present invention is not limited thereto, and the separation gate dielectric layer may also be a high-K dielectric, and the separation gate may be made of metal.
As shown in fig. 11, the semi-floating gate transistor of the split-gate structure includes: the semiconductor device comprises a substrate, a first semiconductor layer, a second semiconductor layer and a third semiconductor layer, wherein a P well region 100, an N well region 102 and a U-shaped groove are formed in the substrate, the N well region 102 is located above the P well region 100, and the U-shaped groove penetrates through the N well region 102; the first gate oxide layer 103 is formed on the surface of the U-shaped groove, extends to cover part of the surface of the N well region 102, and is provided with a window on one side; a semi-floating gate 104 which covers the first gate oxide layer 103 and completely fills the U-shaped groove, and is contacted with the N well region 102 at the window; a second gate oxide layer 105 (i.e., a control gate dielectric layer), a second polysilicon layer 106 (i.e., a control gate), and a second silicon nitride layer 107 (i.e., a mask layer), wherein the second gate oxide layer 105 covers the semi-floating gate 104, and the second gate polysilicon layer 106 and the second silicon nitride layer 107 are sequentially formed on the second gate oxide layer 105; the separation gate dielectric layer comprises a third silicon oxide layer 108 and a third silicon nitride layer 109, is formed on the surface of the N well region 102 and extends to cover part of the surface of the second silicon nitride layer 107, and the separation gate 110 covers the separation gate dielectric layer and fills the separation gate region; and source regions 112,113 and drain regions 114 formed in the nwell region 102 on either side of the control gate and the split gate, respectively.
According to the invention, the traditional single control gate is divided into a control gate and a unique separation gate, and through proper operation voltage setting, a weak programming process in a holding state is eliminated, the holding characteristics of devices at normal temperature and high temperature are greatly improved, and lower power consumption and good storage characteristics are realized. .
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.

Claims (5)

1. A method for preparing a semi-floating gate transistor with a split-gate structure is characterized in that,
the method comprises the following steps:
injecting ions into the substrate to form a P well region and an N well region, wherein the N well region is formed above the P well region and etched to form a U-shaped groove which penetrates through the N well region;
forming a first gate oxide layer and a semi-floating gate, wherein the first gate oxide layer covers the surface of the U-shaped groove and part of the surface of the N well region, and a window is formed on the surface of the N well region outside the U-shaped groove; the semi-floating gate covers the first gate oxide layer and is in surface contact with the N well region at the window;
depositing a second gate oxide layer, a second polysilicon layer and a mask layer, carrying out edge etching, removing the mask layer, the second polysilicon layer, the second gate oxide layer, the first polysilicon layer and the first gate oxide layer at the edge, and etching a control gate region and a separation gate region;
depositing a separation gate dielectric layer to cover the surface of the device, depositing a third polysilicon layer to cover the separation gate dielectric layer and completely fill the separation gate region, and performing edge etching and middle etching to form a control gate, a separation gate and a source drain region;
and forming a side wall, performing source-drain ion implantation, and simultaneously realizing N-type ion doping on the third polycrystalline silicon layer and the first polycrystalline silicon layer to form the semi-floating gate transistor with the split gate structure.
2. The method for manufacturing a semi-floating gate transistor with a split-gate structure according to claim 1,
the step of forming the first gate oxide layer and the semi-floating gate comprises the following steps:
depositing a first gate oxide layer and a first polysilicon layer in the semi-floating gate region;
etching to remove part of the first gate oxide layer on the outer side of the U-shaped groove, so that part of the surface of the N well region is exposed to form a window;
and then backfilling part of the first polycrystalline silicon layer, carrying out ion implantation of the semi-floating gate region, and carrying out chemical mechanical polishing on the first polycrystalline silicon layer to form the semi-floating gate.
3. A semi-floating gate transistor with a split-gate structure,
the method comprises the following steps:
the semiconductor device comprises a substrate, a first substrate and a second substrate, wherein a P well region, an N well region and a U-shaped groove are formed in the substrate, the N well region is located above the P well region, and the U-shaped groove penetrates through the N well region;
the first gate oxide layer is formed on the surface of the U-shaped groove, extends to cover part of the surface of the N well region, and is provided with a window on one side; the semi-floating gate covers the first gate oxide layer, completely fills the U-shaped groove, and is contacted with the N well region at the window;
the control gate dielectric layer covers the semi-floating gate, and the control gate and the mask layer are sequentially formed on the control gate dielectric layer;
the isolation gate dielectric layer is formed on the surface of the N well region and extends to cover part of the surface of the mask layer, and the isolation gate covers the isolation gate dielectric layer and fills the isolation gate region;
and the source region and the drain region are respectively formed on two sides of the control gate and the separation gate and in the N well region.
4. The split-gate structure semi-floating gate transistor according to claim 3,
the separation gate dielectric layer is silicon nitride, and the separation gate is polysilicon.
5. The split-gate structure semi-floating gate transistor according to claim 3,
the separation gate dielectric layer is a high-K dielectric, and the separation gate is made of metal.
CN202111414300.0A 2021-11-25 2021-11-25 Semi-floating gate transistor with split-gate structure and preparation method thereof Pending CN114220741A (en)

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