CN104599969A - Method for reducing electric leakage of trench gate structure semi-floating gate device - Google Patents
Method for reducing electric leakage of trench gate structure semi-floating gate device Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 79
- 238000007667 floating Methods 0.000 title claims abstract description 49
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 27
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 27
- 239000010703 silicon Substances 0.000 claims abstract description 27
- 238000005530 etching Methods 0.000 claims abstract description 24
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 21
- 230000003647 oxidation Effects 0.000 claims abstract description 18
- 230000004888 barrier function Effects 0.000 claims description 42
- 239000000758 substrate Substances 0.000 claims description 31
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 16
- 229920005591 polysilicon Polymers 0.000 claims description 16
- 238000001259 photo etching Methods 0.000 claims description 13
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 239000002019 doping agent Substances 0.000 claims description 5
- 238000002955 isolation Methods 0.000 claims description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 5
- 239000011810 insulating material Substances 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 4
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 4
- 239000004065 semiconductor Substances 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- 238000009792 diffusion process Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000005465 channeling Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42336—Gate electrodes for transistors with a floating gate with one gate at least partly formed in a trench
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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Abstract
The invention discloses a method for reducing electric leakage of a trench gate structure semi-floating gate device. The method includes the step of performing oxidation treatment on silicon remaining at the position close to a field oxide layer side wall in a trench gate channel region during trench etching to form a side wall sacrificial oxide layer with an insulating effect, thereby preventing the current from flowing in the direction of the silicon remaining in the side wall, enabling the current to flow in the direction of a trench-shaped channel of the device and reducing the phenomenon of electric leakage between a source region and a drain region. The method for reducing electric leakage of the trench gate structure semi-floating gate device can be integrated with existing processes and is controllable in cost.
Description
Technical field
The present invention relates to semiconductor memory technologies field, more specifically, relate to a kind of method adopting mode of oxidizing to reduce the electric leakage of groove grid (Trench Gate) structure half floating-gate device.
Background technology
Memory, as one of the basal core chip of electronic product, is widely used in comprising in each electronic product of mobile phone, ambulatory handheld product etc.Wherein, half floating-gate device, as a kind of novel memory device, can be applied to different integrated circuits.
Half floating-gate memory can replace the static random access memory (SRAM) of a part.Tradition SRAM need could form a memory cell with 6 mosfet transistors, and its integrated level is lower, and area occupied is large.Half floating transistor then can form a memory cell by single transistor, and its storage speed is close to traditional SRAM memory cell be made up of 6 transistors.Therefore, the sram cell area be made up of half floating transistor is less, and density compares traditional SRAM approximately can improve 10 times.
Half floating transistor can also be applied to dynamic random access memory (DRAM) field.The elementary cell of tradition DRAM is made up of 1T1C, and namely transistor adds the structure of an electric capacity.Because its electric capacity needs to keep certain quantity of electric charge effectively to store information, thus cannot as MOSFET minification sustainably.Industry manufactures special construction usually electric capacity by digging the means such as " deep trouth " reduces its area taken, but along with the lifting of storage density, technical difficulty and the cost of electric capacity processing increase substantially.Therefore, industry is finding the capacitorless part technology that may be used for manufacturing DRAM always.And the DRAM be made up of half floating transistor just can realize the repertoire of traditional DRAM without the need to capacitor, cost not only can be made significantly to reduce, and integrated level is higher, read or write speed is faster.
In order to ensure the performance of semiconductor memory, what the DRAM that existing half floating transistor is formed adopted is planar channeling structure, but the DRAM with planar channeling structure needs longer channel length, make the cellar area of DRAM comparatively large, thus reduce chip density.
Semiconductor device and the manufacture method thereof of a kind of U-shaped of Chinese invention patent application raceway groove of publication number CN 104103640 A propose a kind of half floating-gate device with U-shaped raceway groove, this U-shaped channel structure is than half floating-gate device of conventional planar channel structure, information is stored with floating boom, and carry out charge or discharge by grid-control p-n junction diode pair floating boom, the cellar area of semiconductor memory can be reduced, improve chip density.
; half floating-gate device in foregoing invention patent application; although increase channel length by U-shaped raceway groove; reduce cellar area, improve chip density, but because this structure is in formation U-lag process; can cause in field oxide sidewall residual silicon; this can cause portion of electrical current in device to flow along the direction of residual lower silicon between sidewall, thus causes device when not applying gate electrode, between source region and drain region, produce leaky.
Summary of the invention
The object of the invention is to the above-mentioned defect overcoming prior art existence, a kind of method reducing the electric leakage of slot grid structure half floating-gate device is provided, by high-temperature oxydation mode, oxidation processes is carried out near the silicon that field oxide side-walls is residual to being formed in groove process middle slot gate groove region in etching, form sidewall sacrificial oxide layer, make electric current along the flowing of groove type channel direction, thus reduce the phenomenon producing electric leakage between source region and drain region.
For achieving the above object, technical scheme of the present invention is as follows:
Reduce a method for slot grid structure half floating-gate device electric leakage, comprise the following steps:
S01: semi-conductive substrate is provided, described substrate is have the monocrystalline silicon of the first doping type, polysilicon or isolate supports, is formed as the field oxide of device isolation, the light dope source region with the second doping type and drain region in described substrate;
S02: by photoetching and etching technics, form groove between source region and drain region, to form groove type groove gate groove region;
S03: carry out high temperature oxidation process near the substrate silicon that field oxide side-walls is residual to being formed in groove process middle slot gate groove region in etching, to form sidewall sacrificial oxide layer, and after high temperature oxidation process, the sacrificial oxide layer simultaneously formed in the bottom portion of groove region in groove gate groove direction is removed;
S04: deposit first insulating barrier, and be positioned at above drain region, near the first insulating barrier formation floating boom open area of groove;
S05: deposit has the first conductive layer of the first doping type, fills up to major general's groove and floating boom open area, and forms half floating boom by photoetching and etching technics;
S06: deposit second insulating barrier, the second conductive layer, then by photoetching and etching technics formation control grid;
S07: deposit the 3rd insulating barrier, the side wall of formation control grid is anti-carved by etching technics, then the ion implantation of the second doping type is carried out, to control gate with do not adulterated by the substrate surface that control gate covers, to form the dopant profiles in device source region and drain region.
Preferably, in step S03, produce technique by situ steam, high temperature oxidation process is carried out, to form sidewall sacrificial oxide layer to residual silicon.
Preferably, the temperature that situ steam produces technique is 900 ~ 1100 DEG C, and the time is 10 ~ 120s.
Preferably, situ steam generation technique is carried out under the pressure of 1 ~ 10torr.
Preferably, described first insulating barrier or the second insulating barrier are formed by silica, silicon nitride, silicon oxynitride or other high dielectric constant insulating materials.
Preferably, the thickness of described first insulating barrier or the second insulating barrier is 20 ~ 80 dusts.
Preferably, described 3rd insulating barrier is formed by silica or silicon nitride.
Preferably, described first conductive layer is formed by the polysilicon of the first doping type; Described second conductive layer is formed by the polysilicon of the second doping type, metal or alloy.
Preferably, the first doping type described is N-type or P type, and described the second doping type is P type or N-type.
Preferably, the degree of depth of described groove is greater than the degree of depth in light dope source region and drain region.
As can be seen from technique scheme, the present invention is by high-temperature oxydation mode, oxidation processes is carried out near the silicon that field oxide side-walls is residual to being formed in groove process middle slot gate groove region in etching, form the sidewall sacrificial oxide layer with insulation effect, avoid electric current to flow along the direction of lower silicon residual between sidewall, electric current can be flowed along device recesses shape channel direction, thus reduce the phenomenon producing electric leakage between source region and drain region.Method of the present invention can be mutually integrated with existing technique, and cost is controlled.
Accompanying drawing explanation
Fig. 1 is a kind of flow chart reducing the method for slot grid structure half floating-gate device electric leakage of the present invention;
Fig. 2 ~ Figure 10 is the structural representation forming slot grid structure half floating-gate device according to the method for Fig. 1;
Figure 11 is the basic structure vertical view of slot grid structure half floating boom;
Figure 12 is the profile in A-A direction in Figure 11;
Figure 13 is the profile in B-B direction in Figure 11.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in further detail.
It should be noted that, in following embodiment, when describing embodiments of the present invention in detail, in order to clearly represent structure of the present invention so that explanation, special to the structure in accompanying drawing not according to general scale, and carried out partial enlargement, distortion and simplify processes, shown structure size does not represent actual size.Meanwhile, accompanying drawing is the schematic diagram of idealized embodiments of the present invention, and illustrated embodiment should not be considered to the given shape being only limitted to region shown in figure, but comprises obtained shape, the deviation etc. caused in such as manufacturing.Such as, etch the curve obtained and there is bending or mellow and full feature usually, but in an embodiment of the present invention, for convenience of description, all represent with rectangle.Therefore, should avoid being understood in this, as limitation of the invention.
First, the reason of slot grid structure half floating-gate device generation leaky is described.First refer to Figure 10, slot grid structure half floating-gate device that the method that its display reduces the electric leakage of slot grid structure half floating-gate device according to the present invention is formed is along the section of structure in device channel length direction.As shown in Figure 10, half floating-gate device comprise be formed at field oxide 102 in Semiconductor substrate 101 and with the source region 106 of Semiconductor substrate opposite doping concentrations, drain region 107.Semiconductor substrate 101 can be monocrystalline silicon, polysilicon or isolate supports.Groove type groove gate groove district 108 is also formed in Semiconductor substrate 101.Cover whole groove type channel region 108 and be formed with the first insulating barrier 111, first insulating barrier 111 be formed with a floating boom open area 112 above drain region, near groove top outside left on substrate 101, source region 106, drain region 107.Be formed with the floating boom 113 of the first doping type at the first insulating barrier 111 and floating boom open area 112, floating boom 113 is at least all positioned at groove near side, source region 106, exceeds trough-like area and all cover floating boom open area 112 near side, drain region 107.Impurity in floating boom 113 can pass through floating boom open area 112 by High temperature diffusion in drain region 107, and forms the diffusion region 114 of the first doping content, thus forms a PN junction diode between diffusion region 114 and drain region 107.Cover source region 106, floating gate region 113 and PN junction diode structure and be formed with the second insulating barrier 115, be control gate 116 on the second insulating barrier 115, and control gate 116 covers and surrounds floating boom 113.Grid curb wall 117 is also formed in control gate 116 both sides.Heavy doping source region 118 and heavy doping drain region 119 is also form respectively in source region 106 and drain region 107.
In the ideal situation, in slot grid structure half floating-gate device shown in Figure 10, electric current will flow along groove type (as dotted arrow direction indication in figure).Like this, between source region 106 and drain region 107, leaky would not be produced in theory.
Please then consult Figure 11 ~ Figure 13, Figure 11 is the vertical view of slot grid structure half floating boom basic structure, the basic structure of half floating boom 113 in its display Figure 10 after formation first insulating barrier 111 and floating boom open area 112; Figure 12 is the profile in A-A direction in Figure 11; Figure 13 is the profile in B-B direction in Figure 11.Established field oxide 102, source region 106, drain region 107, first insulating barrier 111, floating boom 113 and floating boom open area 112 is schematically demonstrated in figure.As can be seen from Figure 12, after over etching, formed in the process of groove type structure between substrate 101 and field oxide 102, in groove gate groove region, in the groove type structure of both sides field oxide 102 side-walls, all can remain lower unnecessary silicon 109-1 all the time.The silicon 109-1 that left behind can cause electric current be not according in Figure 10 shown in dotted arrow along the flowing of groove type channel direction, but flow in the direction remaining lower silicon along field oxide as shown in dotted arrow in Figure 13.Device will being caused like this when not applying gate electrode, between source region 106 and drain region 107, producing leaky.
In order to solve the problem, the present invention proposes by high-temperature oxydation mode, oxidation processes is carried out near the silicon that field oxide side-walls is residual to being formed in groove process middle slot gate groove region in etching, form sidewall sacrificial oxide layer, electric current can be flowed along groove type channel direction, thus reduce the phenomenon producing electric leakage between source region and drain region.
In following the specific embodiment of the present invention, refer to Fig. 1, Fig. 1 is a kind of flow chart reducing the method for slot grid structure half floating-gate device electric leakage of the present invention.Meanwhile, refer to Fig. 2 ~ Figure 10, Fig. 2 ~ Figure 10 is the structural representation forming slot grid structure half floating-gate device according to the method for Fig. 1.As shown in Figure 1, a kind of method reducing the electric leakage of slot grid structure half floating-gate device of the present invention, comprises the following steps:
As shown in frame 1, S01: semi-conductive substrate is provided, described substrate is have the monocrystalline silicon of the first doping type, polysilicon or isolate supports, is formed as the field oxide of device isolation, the light dope source region with the second doping type and drain region in described substrate.
Refer to Fig. 2.The field oxide 102 as device isolation is formed by shallow-trench isolation (STI) technique in the Semiconductor substrate 101 with the first doping type.Described substrate 101 can be monocrystalline silicon, polysilicon or isolate supports.
Refer to Fig. 3.Then, the light doping section 103 with the second doping type is formed in the substrate 101 by ion implantation technology (as shown by arrow indication).
In above-mentioned doping type, the first doping type described is N-type, and described the second doping type is P type; Or the first doping type described is P type, described the second doping type is N-type (lower same).In the specific embodiment of the present invention and specific embodiment, adopt that the first doping type is P type, the second doping type is N-type.Namely adopt the substrate 101 with the doping of P type, form the light doping section 103 with N-type doping.
As shown in frame 2, S02: by photoetching and etching technics, form groove between source region and drain region, to form groove type groove gate groove region.
Refer to Fig. 4.Next, at substrate 101 surface deposition one deck hard mask layer 104, and on hard mask layer 104 deposit one deck photoresist 105.Then, the position in the groove gate groove region of device is defined by mask plate, photoetching process, the hard mask layer 104 of exposure is etched away by mask plate, and with hard mask layer 104 for mask, pass through dry etching method, etch the substrate 101 exposed, thus in Semiconductor substrate 101, form the groove of upward opening, form the groove gate groove region 108 with groove type.N-type light doping section 103 is isolated into two parts in diagram left and right by groove, respectively as source region 106 and the drain region 107 of device.Further, the degree of depth of this groove is greater than the degree of depth (namely illustrating the degree of depth in source region 106 and drain region 107) of light doping section 103.
As shown in frame 3, S03: carry out high temperature oxidation process near the substrate silicon that field oxide side-walls is residual to being formed in groove process middle slot gate groove region in etching, to form sidewall sacrificial oxide layer, and after high temperature oxidation process, the sacrificial oxide layer simultaneously formed in the bottom portion of groove region in groove gate groove direction is removed.
Refer to Fig. 5.In aforesaid Figure 12, formed in the process of groove type structure after over etching, in the groove type structure of both sides field oxide 102 side-walls, lower unnecessary substrate silicon 109-1 all can be remained all the time in groove gate groove region, causing device when not applying gate electrode, between source region and drain region, producing leaky.In order to solve this problem, by carrying out high temperature oxidation process to being formed in groove process middle slot gate groove region in etching near the silicon that field oxide 102 side-walls is residual, make silicon change the silica of insulation into, form sidewall sacrificial oxide layer 109 in field oxide 102 side-walls of groove.After high temperature oxidation process, form the sidewall sacrificial oxide layer 109 with insulation effect, can direction as shown in dotted arrow in Figure 10, electric current is flowed along the groove type channel direction of device, avoid direction flowing possible of electric current along lower silicon residual between sidewall, thus reduce the phenomenon producing electric leakage between source region and drain region.
In an alternate embodiment of the present invention, situ steam can be adopted to produce (In-situ steamgeneration, ISSG) technique, high temperature oxidation process is carried out, to form sidewall sacrificial oxide layer 109 to residual silicon.Preferably, the temperature of ISSG technique is 900 ~ 1100 DEG C, and the time is 10 ~ 120s.Further, ISSG technique can be carried out under the pressure of 1 ~ 10torr.
After high temperature oxidation process ISSG technique as escribed above, the sacrificial oxide layer 110 simultaneously formed in the bottom portion of groove region in groove gate groove direction is etched and removes and clean, in order to avoid stable the having a negative impact of the first insulating barrier 111 (see Fig. 6) size to subsequent deposition.
As shown in frame 4, S04: deposit first insulating barrier, and be positioned at above drain region, near the first insulating barrier formation floating boom open area of groove.
Refer to Fig. 6.Then, stripping photoresist 105, and etch remaining hard mask layer 104.After cleaning, at surface deposition first insulating barrier 111 of Semiconductor substrate 101.Then, deposit one deck photoresist again on the first insulating barrier 111, and the position of floating boom open area is defined by photoetching, developing process.Then, be mask with photoresist, etch away the first insulating barrier 111 exposed, thus position forms floating boom open area 112 above the drain region 107 of side above groove.Afterwards, photoresist is peeled off.In an alternate embodiment of the present invention, the first insulating barrier 111 can be silica, silicon nitride, silicon oxynitride or other high dielectric constant insulating materials, and preferably, its thickness is 20 ~ 80 dusts (A).
As shown in frame 5, S05: deposit has the first conductive layer of the first doping type, fills up to major general's groove and floating boom open area, and forms half floating boom by photoetching and etching technics.
Refer to Fig. 7.Next, on the surface that semiconductor exposes, deposit one deck has the first conductive layer of the first doping type, and in the specific embodiment of the invention, the first conductive layer is the polysilicon with P type doping type.This polysilicon needs groove gate region and the floating boom open area of filling up whole groove, ensures that recess region does not have cavity.Then, deposit one deck photoresist on formed polysilicon first conductive layer, and the position of floating boom is defined by photoetching process.Then, be mask with photoresist, etch away remaining polysilicon, form half floating boom 113 of device.Impurity in floating boom 113 by floating boom open area 112 High temperature diffusion to drain region 107, can be formed p type diffusion region 114, and by floating boom open area 112, forms a PN junction diode between floating boom 113 and drain region 107.On the one hand, half floating-gate device of slot grid structure of the present invention, owing to being connected by PN junction diode between the floating boom 113 of its slot grid structure and drain region 107, makes floating boom 113 present " half is floating " state; On the other hand, because floating boom 113 covers on the first insulating barrier 111, can opening of channel region electric current be controlled by Electric Field Modulated and close.Afterwards, stripping photoresist.
As shown in frame 6, S06: deposit second insulating barrier, the second conductive layer, then by photoetching and etching technics formation control grid.
Refer to Fig. 8.Next, etch away the first insulating barrier 111 exposed, and deposit forms the second insulating barrier 115 on the exposed surface forming structure.In an alternate embodiment of the present invention, the second insulating barrier 115 can be silica, silicon nitride, silicon oxynitride or other high dielectric constant insulating materials.Further, its thickness is 20 ~ 80 dusts (A).
Refer to Fig. 9.Next, second conductive layer 116 of deposit the second doping type on the second insulating barrier 115, in an alternate embodiment of the present invention, described second conductive layer with N-type doping type is formed by polysilicon, metal or alloy.The specific embodiment of the invention adopts polysilicon as the second conductive layer.Then, deposit one deck photoresist on the second conductive layer 116, and the position of device control gate is defined by photoetching process.Then, be mask with photoresist, etch away and be exposed to the second outer conductive layer, after etching, remaining second conductive layer forms the control gate 116 of device.Control gate 116 should be greater than floating boom 113 in orientation, and covers completely and surround floating boom 113.Afterwards, stripping photoresist.It should be noted that, the thickness of described control gate 116 needs to carry out THICKNESS CONTROL according to the operating voltage of device periphery circuit.
As shown in frame 7, S07: deposit the 3rd insulating barrier, is anti-carved the side wall of formation control grid, then carry out the ion implantation of the second doping type by etching technics, to control gate with do not adulterated by the substrate surface that control gate covers, to form the dopant profiles in device source region and drain region.
Refer to Figure 10.Next, on the exposed surface forming structure, deposit the 3rd insulating barrier, anti-carves technique to the 3rd insulating barrier, forms side wall 117 in the both sides of control gate 116.In an alternate embodiment of the present invention, the 3rd insulating barrier can be silica or silicon nitride.Then, have employed N-type impurity in the specific embodiment of the invention to inject, to control gate 116 with do not adulterated by the substrate surface that control gate covers.Finally, adopt rapid thermal anneal process, to form the dopant profiles in device source region and drain region, form the polysilicon control grid 116 with N-type doping, and form high-concentration dopant district 118 and 119 respectively in source region 106 and drain region 107.
In sum, the present invention is by high temperature oxidation process mode, oxidation processes is carried out near the silicon that field oxide side-walls is residual to being formed in groove process middle slot gate groove region in etching, form the sidewall sacrificial oxide layer with insulation effect, avoid electric current to flow along the direction of lower silicon residual between sidewall, electric current can be flowed along device recesses shape channel direction, thus reduce the phenomenon producing electric leakage between source region and drain region.Method of the present invention improves the performance of slot grid structure half floating-gate device by process means, reduce electric leakage, make slot grid structure half floating-gate device can be used for the application of high-speed low-power consumption, and can be mutually integrated with existing technique, and cost is controlled, be in the industry cycle suitable for promoting the use of.
Above-describedly be only the preferred embodiments of the present invention; described embodiment is also not used to limit scope of patent protection of the present invention; therefore the equivalent structure that every utilization specification of the present invention and accompanying drawing content are done changes, and in like manner all should be included in protection scope of the present invention.
Claims (10)
1. reduce a method for slot grid structure half floating-gate device electric leakage, it is characterized in that, comprise the following steps:
S01: semi-conductive substrate is provided, described substrate is have the monocrystalline silicon of the first doping type, polysilicon or isolate supports, is formed as the field oxide of device isolation, the light dope source region with the second doping type and drain region in described substrate;
S02: by photoetching and etching technics, form groove between source region and drain region, to form groove type groove gate groove region;
S03: carry out high temperature oxidation process near the substrate silicon that field oxide side-walls is residual to being formed in groove process middle slot gate groove region in etching, to form sidewall sacrificial oxide layer, and after high temperature oxidation process, the sacrificial oxide layer simultaneously formed in the bottom portion of groove region in groove gate groove direction is removed;
S04: deposit first insulating barrier, and be positioned at above drain region, near the first insulating barrier formation floating boom open area of groove;
S05: deposit has the first conductive layer of the first doping type, fills up to major general's groove and floating boom open area, and forms half floating boom by photoetching and etching technics;
S06: deposit second insulating barrier, the second conductive layer, then by photoetching and etching technics formation control grid;
S07: deposit the 3rd insulating barrier, the side wall of formation control grid is anti-carved by etching technics, then the ion implantation of the second doping type is carried out, to control gate with do not adulterated by the substrate surface that control gate covers, to form the dopant profiles in device source region and drain region.
2. the method for reduction slot grid structure half floating-gate device electric leakage according to claim 1, is characterized in that, in step S03, produce technique by situ steam, carry out high temperature oxidation process, to form sidewall sacrificial oxide layer to residual silicon.
3. the method for reduction slot grid structure half floating-gate device electric leakage according to claim 2, it is characterized in that, the temperature that situ steam produces technique is 900 ~ 1100 DEG C, and the time is 10 ~ 120s.
4. the method for the reduction slot grid structure half floating-gate device electric leakage according to Claims 2 or 3, is characterized in that, situ steam produces technique and carries out under the pressure of 1 ~ 10torr.
5. the method for reduction slot grid structure half floating-gate device electric leakage according to claim 1, it is characterized in that, described first insulating barrier or the second insulating barrier are formed by silica, silicon nitride, silicon oxynitride or other high dielectric constant insulating materials.
6. the method for reduction slot grid structure half floating-gate device electric leakage according to claim 5, it is characterized in that, the thickness of described first insulating barrier or the second insulating barrier is 20 ~ 80 dusts.
7. the method for reduction slot grid structure half floating-gate device electric leakage according to claim 1, it is characterized in that, described 3rd insulating barrier is formed by silica or silicon nitride.
8. the method for reduction slot grid structure half floating-gate device electric leakage according to claim 1, it is characterized in that, described first conductive layer is formed by the polysilicon of the first doping type; Described second conductive layer is formed by the polysilicon of the second doping type, metal or alloy.
9. the method for the reduction slot grid structure half floating-gate device electric leakage according to claim 1 or 8, it is characterized in that, the first doping type described is N-type or P type, and described the second doping type is P type or N-type.
10. the method for reduction slot grid structure half floating-gate device electric leakage according to claim 1, it is characterized in that, the degree of depth of described groove is greater than the degree of depth in light dope source region and drain region.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510052373.8A CN104599969A (en) | 2015-02-02 | 2015-02-02 | Method for reducing electric leakage of trench gate structure semi-floating gate device |
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| CN106601750A (en) * | 2016-12-30 | 2017-04-26 | 上海集成电路研发中心有限公司 | Semi-floating gate memory device with U-shaped groove and preparation method thereof |
| CN112151616A (en) * | 2020-08-20 | 2020-12-29 | 中国科学院微电子研究所 | Stacked MOS device and preparation method thereof |
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