CN114284285B - NOR type semiconductor memory device and manufacturing method thereof - Google Patents
NOR type semiconductor memory device and manufacturing method thereof Download PDFInfo
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- CN114284285B CN114284285B CN202110616290.2A CN202110616290A CN114284285B CN 114284285 B CN114284285 B CN 114284285B CN 202110616290 A CN202110616290 A CN 202110616290A CN 114284285 B CN114284285 B CN 114284285B
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Abstract
The invention provides a NOR type semiconductor memory device and a manufacturing method thereof, wherein the semiconductor memory device comprises: a two-dimensional semiconductor memory structure (Periphery Under Cell, PUC) located on the peripheral circuit; and a contact layer over the two-dimensional semiconductor memory structure. According to the scheme, the two-dimensional semiconductor storage structure is combined with the PUC technology to form the three-dimensional NOR gate semiconductor storage device (3D NOR Flash memory), so that the consumption of a PUC circuit to the space of a chip is reduced, the space utilization rate of the NOR gate flash memory device is improved, the storage density is improved, and the cost is reduced.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a three-dimensional NOT gate (3D NOR Flash memory) semiconductor memory device and a manufacturing method thereof.
Background
Flash Memory (Flash Memory) is a non-volatile Memory, and data is not lost even when power failure occurs. Flash memory typically stores information in an array of memory cells made of floating gate transistors. For example, in a single layer cell (Single Level Cell, SLC) device, each cell stores only 1bit of information. In the case of a Multi-Level Cell (MLC) device containing Three Levels of Cells (TLC), each Cell can store more than one 1bit of information.
In a flash memory, one end of each memory cell is directly grounded, and the other end is directly connected to a bit line; when a word line (control gate CG connected to the memory cell) is connected to a high level, the corresponding memory cell will pull the bit line output low. Since such a Flash memory operates in a manner similar to that of a NOR gate, such a Flash memory is also called a NOR gate Flash memory (NOR Flash memory). For some devices that require embedded non-volatile storage, nor gate flash is typically selected as the device for which it is stored. Furthermore, due to the low read delay characteristics of nor gate memory devices, code execution and data storage can be performed directly in a stand-alone memory product.
With the development of flash memory technology, 3D flash memory technology is gradually reflected in human eyes. By employing new technologies such as 3D NAND, the die is enabled to be stacked in a three-dimensional manner, thereby solving the limitation that the available capacity of a single die cannot be further expanded due to physical limitations. For example, based on a three-dimensional stack of multiple layers of oxide/nitride along the vertical direction, in combination with a large-ratio cell array transistor (Terabit Cell Array Transistor, TCAT) technology, charge trap memory cells are obtained, thereby forming a 3D junction-free cylindrical channel charge trap NAND semiconductor memory device.
However, there is little research on the control and expansion of NOR Flash memory (NOR Flash memory).
Disclosure of Invention
The scheme aims to provide a three-dimensional NOR gate semiconductor memory device (3D NOR Flash memory) and a manufacturing method thereof, so as to solve the problems of low space utilization rate, limited storage density and the like of a NOR gate flash memory device in the prior art.
In order to achieve the above purpose, the present solution adopts the following technical scheme:
in a first aspect, the present invention provides a semiconductor memory device comprising:
a two-dimensional semiconductor memory structure located on the PUC (Periphery Under Cell) circuit;
and a contact layer over the two-dimensional semiconductor memory structure.
In a preferred embodiment, the PUC circuit includes: a plurality of semiconductor structures having wiring layers on the insulating layer; the conductivity types of adjacent two semiconductor structures are different and are isolated by trenches.
In a preferred embodiment, the semiconductor structure comprises:
a first region having a first conductivity type on the insulating layer;
a first well region and a second well region of a second conductivity type located within the first region, the first well region and the second well region being spaced apart by the first region;
a source region located within the first well region and a drain region located within the second well region;
and a second region with the first conductivity type positioned on one side of the first well region close to the second well region, and a second region with the first conductivity type positioned on one side of the second well region close to the first well region.
In a preferred embodiment, the first conductivity type is P-type and the second conductivity type is N-type; or the first conductivity type is N type, and the second conductivity type is P type.
In a preferred embodiment, the semiconductor structure further comprises: and a gate structure located on the first region.
In a preferred embodiment, the gate structure comprises: a gate insulating layer on the first region, a gate on the gate insulating layer, and a spacer on a side of the gate.
In a preferred embodiment, the wiring layer includes: a first dielectric layer overlying the semiconductor structure and a plurality of peripheral lines within the first dielectric layer;
the peripheral lines are correspondingly connected with a source electrode, a drain electrode and a gate electrode in the semiconductor device.
In a preferred embodiment, the two-dimensional semiconductor memory structure includes:
a first separation layer, a channel layer and a bit line array sequentially located on the PUC circuit;
a second dielectric layer covering the first spacer layer, channel layer and bit line array;
a first contact line vertically passing through the second dielectric layer and coupled to the channel layer; word lines vertically coupled to the bit line array through the second dielectric layer; wherein the first contact lines on even columns are used for connecting with the ground electrode.
In a preferred embodiment, the contact layer comprises:
a second separation layer and a third dielectric layer which are sequentially covered on the second dielectric layer;
a second contact line vertically passing through the third dielectric layer and the second separation layer; wherein the first contact line located on the odd columns is coupled to the second contact line.
In a preferred embodiment, the first and/or second separation layer is a nitrogen doped copper oxycarbide layer; and/or the number of the groups of groups,
the channel layer is a polysilicon layer; and/or the number of the groups of groups,
the bit line array is formed by adopting an ONO three-layer composite structure dielectric layer based on an etching process; and/or the number of the groups of groups,
the first dielectric layer and/or the second dielectric layer are/is made of ultra-low k dielectric material and are formed based on chemical mechanical polishing process
In a second aspect, the present invention provides a method for manufacturing a semiconductor memory device, the method comprising the steps of:
taking the PUC circuit as a substrate;
forming a two-dimensional semiconductor memory structure on the substrate;
and forming a contact layer on the two-dimensional semiconductor storage structure.
In a preferred embodiment, the manufacturing steps of the PUC circuit 1 comprise:
providing an insulating layer;
forming a plurality of semiconductor structures having wiring layers on the insulating layer;
forming a trench between adjacent semiconductor structures;
wherein the conductivity types of adjacent two semiconductor structures are different.
In a preferred embodiment, the manufacturing steps of the semiconductor structure include:
forming a first region having a first conductivity type on the insulating layer;
forming a first well region and a second well region of a second conductivity type within the first region, the first well region and the second well region being separated by the first region;
forming a source region in the first well region and forming a drain region in the second well region;
and forming a second region with the first conductivity type on one side of the first well region close to the second well region, and forming a second region with the first conductivity type on one side of the second well region close to the first well region.
In a preferred embodiment, the first conductivity type is P-type and the second conductivity type is N-type; or the first conductivity type is N type, and the second conductivity type is P type.
In a preferred embodiment, the step of manufacturing the semiconductor structure further comprises: and forming a gate structure on the first region.
In a preferred embodiment, the gate structure comprises: a gate insulating layer on the first region, a gate electrode on the gate insulating layer, and a spacer on a side of the gate electrode; wherein a portion of the gate and a portion of the spacer are located over the isolation structure.
In a preferred embodiment, the step of manufacturing the contact layer further comprises:
forming a first dielectric layer on the semiconductor structure;
forming a plurality of contact holes in the first dielectric layer, and filling peripheral circuits in the contact holes; wherein, the peripheral circuit is correspondingly connected with the source electrode, the drain electrode and the grid electrode.
In a preferred embodiment, the two-dimensional semiconductor memory structure is manufactured by the steps of: sequentially forming a first separation layer, a channel layer and a bit line array on the PUC circuit;
forming a second dielectric layer on the first separation layer, the channel layer and the bit line array;
forming a first contact hole vertically penetrating through the second dielectric layer, and arranging a first contact line in the first contact hole to be connected with the channel layer;
forming a word line hole vertically penetrating through the second dielectric layer, and arranging word lines in the word line hole to be connected with the bit line array;
wherein the first contact lines on even columns are used for connecting with the ground electrode.
In a preferred embodiment, the step of manufacturing the contact layer comprises:
sequentially forming a second separation layer and a third dielectric layer on the second dielectric layer;
forming a second contact hole vertically penetrating through the third dielectric layer, and arranging a second contact line in the second contact line; wherein the first contact line located on the odd columns is coupled to the second contact line.
In a preferred embodiment, the first and/or second separation layer is a nitrogen doped copper oxycarbide layer; and/or the number of the groups of groups,
the channel layer is a polysilicon layer; and/or the number of the groups of groups,
the bit line array is formed by adopting an ONO three-layer composite structure dielectric layer based on an etching process; and/or the number of the groups of groups,
the first dielectric layer and/or the second dielectric layer are/is formed by adopting an ultralow-k dielectric material based on a chemical mechanical polishing process.
Advantageous effects
According to the scheme, the two-dimensional semiconductor storage structure is combined with PUC (Periphery Under Cell) circuit technology to form the three-dimensional NOR gate semiconductor storage device (3D NOR Flash memory), so that the consumption of the PUC circuit to the space of a chip is reduced, the space utilization rate of the NOR gate flash memory device is improved, the storage density is improved, and the cost is reduced.
Drawings
Fig. 1 shows a schematic structural diagram of a semiconductor device according to the present embodiment.
Fig. 2 shows a schematic diagram of a method for manufacturing a semiconductor device according to the present embodiment.
Fig. 3 is a structural cross-sectional view showing a stage in the manufacturing process of the semiconductor memory device according to one embodiment of the present invention.
Fig. 4 is a structural cross-sectional view showing a stage in the manufacturing process of the semiconductor memory device according to one embodiment of the present invention.
Fig. 5 is a structural cross-sectional view showing a stage in the manufacturing process of the semiconductor memory device according to one embodiment of the present invention.
Fig. 6 shows a schematic diagram of a word line and bit line arrangement in the semiconductor device according to the present embodiment.
Description of the reference numerals
1. A PUC circuit; 101. an insulating layer; 102. a groove; 103. a first region; 104. a first well region; 105. a second well region; 106. a source region; 107. a drain region; 108. a second region; 109. a gate structure; 110. a first dielectric layer; 111. a peripheral circuit;
2. a two-dimensional semiconductor memory structure; 201. a first separation layer; 202. a channel layer; 203. a bit line array; 204. a second dielectric layer; 205. a word line; 206. a first contact line;
3. a contact layer; 301. a second separation layer; 302. a third dielectric layer; 303. a second contact line.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
It should be noted that, the illustrations provided in the present embodiment only illustrate the basic concept of the present invention by way of illustration, but only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number, positional relationship and proportion of each component in actual implementation may be changed at will on the premise of implementing the present technical solution, and the layout of the components may be more complex. Thus, variations in the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be considered limited to the particular shapes of the regions illustrated in the figures, but may also include deviations in shapes that result, for example, from manufacturing processes. In the drawings, the length and size of certain layers and regions may be exaggerated for clarity. Like reference numerals in the drawings denote like parts. It will also be understood that when a layer is referred to as being "on" another layer or spacer, the layer can be directly on the other layer or spacer, or intervening layers may also be present.
Through research and analysis, the problems of setting up the PUC circuit 1 of the NOR gate flash memory, expanding the storage density and the like in the prior art have no good solution. For the expansion technology for 3D NAND, it is not applicable to nor gate flash. Therefore, the scheme aims to provide the three-dimensional nor gate semiconductor memory device (3D NOR Flash memory) and the manufacturing method thereof, and provides a solution for the problems of setting the PUC circuit 1, expanding the storage density and the like of the nor gate flash memory at present, so that the space utilization rate of the nor gate flash memory device is improved, the storage density is improved, and the cost is reduced.
In order to make the above objects, features and advantages of the present solution more comprehensible, specific embodiments accompanied with figures are described in detail below.
As shown in fig. 1, a schematic diagram of an embodiment of a semiconductor memory device according to the present embodiment is shown. The semiconductor memory device includes: a two-dimensional semiconductor memory structure 2 located on the PUC circuit 1; and a contact layer 3 positioned above the two-dimensional semiconductor memory structure 2. According to the scheme, the two-dimensional NOR gate flash memory (2D NOR Flash Memory) is combined with the PUC circuit 1 (PUC, peri underwriter Cell), a circuit for driving a storage unit is stacked below a unit array for storing data, the limitation of the existing two-dimensional NOR gate flash memory is broken through, and a novel three-dimensional NOR gate semiconductor storage device (3D NOR Flash memory) is formed. The three-dimensional nor gate semiconductor memory device can be used as an embedded nor gate flash memory, and can also form a standard independent nor gate memory product.
In this embodiment, the PUC circuit 1 may employ a plurality of planar semiconductor structures having wiring layers formed on the insulating layer 101. The conductivity types of adjacent two semiconductor structures are different and are isolated by trench 102.
Specifically, the semiconductor structure includes: a first region 103 having a first conductivity type on the insulating layer 101; a first well region 104 and a second well region 105 having a second conductivity type located within the first region 103, the first well region 104 and the second well region 105 being spaced apart by the first region 103; a source region 106 located within the first well region 104, and a drain region 107 located within the second well region; a second region 108 of the first conductivity type located on a side of the first well region 104 adjacent to the second well region 105, and a second region 108 of the first conductivity type located on a side of the second well region 105 adjacent to the first well region 104.
In this embodiment, the insulating layer 101 is used as a process platform for forming semiconductor structures in the PUC circuit 1. Wherein, the insulating layer 101 may be a glass substrate.
In this embodiment, the first region 103 is a substrate of a semiconductor structure, and the substrate is used as a base for forming the semiconductor structure. Wherein, the substrate can be a silicon substrate.
In other embodiments, the substrate material may also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate may also be a silicon-on-insulator substrate, a germanium-on-insulator substrate, or a group III-V compound substrate (e.g., gallium nitride base or gallium arsenide substrate, etc.).
When the semiconductor structure is a P-type semiconductor device, the substrate is doped with N-type material; when the semiconductor structure is an N-type semiconductor device, the substrate is doped with P-type material. In one embodiment, the conductivity types of the adjacent two semiconductor structures are opposite, so if the conductivity type of the semiconductor structure to the left of the trench 102 is N-type, the substrate of the left semiconductor structure is doped with P-type impurity ions, the conductivity type of the semiconductor structure to the right of the trench 102 is P-type, and the substrate of the right semiconductor structure is doped with N-type impurity ions.
In this scheme, the first well region 104 and the second well region 105 have the same conductivity type, and the first well region 104 and the second well region 105 are separated by a first region. The conductivity type of the two well regions is opposite to the conductivity type of the substrate. In one embodiment, the substrate is P-doped, and then the first well region 104 and the second well region 105 are both N-wells. In another embodiment, the substrate is N-doped, and the first well region 104 and the second well region 105 are P-wells.
In this embodiment, a source region 106 is formed in the first well region 104, and a drain region 107 is formed in the second well region 105. The conductivity type of the source region 106 and the drain region 107 is the same and opposite to the conductivity type of the first well region 104 and the second well region 105. In one embodiment, the first well region 104 and the second well region 105 are N-wells, and the source region 106 and the drain region 107 are P-type conductivity. In another embodiment, the first well region 104 and the second well region 105 are P-wells, and the source region 106 and the drain region 107 are of N-type conductivity.
In this embodiment, the second region 108 with the first conductivity type is located on a side of the first well region 104 near the second well region 105, and the second region 108 with the first conductivity type is located on a side of the second well region 105 near the first well region 104. In one embodiment, the first well region 104 and the second well region 105 are N-wells, and the second region 108 is of P-type conductivity. In another embodiment, the first well region 104 and the second well region 105 are P-wells, and the second region 108 is of N-type conductivity.
In this embodiment, the isolation of the trench 102 between adjacent semiconductor structures in the PUC circuit 1 may be shallow trench isolation (Shallow Trench Isolation, STI). Wherein the trench 102 is filled with an insulator (e.g., silicon dioxide).
In this scheme, a gate structure 109 is formed over the first region 103. The gate structure 109 is used to control the turning on and off of the semiconductor mechanism. The gate structure 109 includes: a gate insulating layer on the first region 103, a gate on the gate insulating layer, and a spacer on a side of the gate; a portion of the gate and a portion of the spacer are located over the well region. Wherein, the grid insulating layer can be silicon oxide; the grid electrode can be made of other materials such as polysilicon, silicon carbide, silicon carbonitride oxide or amorphous carbon; the spacers may be silicon oxide or silicon nitride. In one embodiment, the gate structure 109 includes: silicon dioxide on the first region 103, polysilicon on the silicon dioxide, and silicon nitride on the sides of the polysilicon.
In other embodiments, the gate structure 109 may also be a metal gate (metal gate) structure, and accordingly, the gate insulating layer is a high-k gate dielectric layer, and the gate is a gate electrode. The material of the high-k gate dielectric layer is a high-k dielectric material, and the high-k dielectric material refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide, for example: hfO (HfO) 2 、ZrO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO or Al 2 O 3 Etc.; the material of the gate is a conductive material, for example: w, al, cu, ag, au, pt, ni or Ti, etc.
In other embodiments, the material of the spacer may be one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, boron nitride and boron carbonitride, and the sidewall may have a single-layer structure or a stacked-layer structure.
In this scheme, the wiring layer includes: a first dielectric layer 110 overlying the semiconductor structure and a plurality of peripheral lines 111 within the first dielectric layer 110; the peripheral lines 111 are correspondingly connected with the source, drain and gate electrodes in the semiconductor device. Wherein the first dielectric layer 110 is formed on the semiconductor structure by a deposition process using an ultra low k dielectric material. Through a mask process, contact holes are etched in positions corresponding to the source electrode, the drain electrode and the gate electrode on the first dielectric layer 110, and peripheral circuits 111 are filled in the contact holes, so that wiring is achieved.
Furthermore, the PUC circuit of the present scheme may include any suitable digital, analog, and/or mixed signal PUC circuit devices for facilitating operation of the 3D nor gate flash memory device. For example, the PUC circuit 1 may include one or more of a data buffer (e.g., a bit line page buffer), a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), a charge pump, a current or voltage reference, or any active or passive component of a circuit (e.g., a transistor, diode, resistor, or capacitor).
In this embodiment, the two-dimensional semiconductor memory structure 2 is a two-dimensional nor gate flash memory device, which is formed on the PUC circuit 1 through deposition, etching, grinding, polishing, and other processes.
Specifically, the two-dimensional semiconductor memory structure 2 includes: a first separation layer 201, a channel layer 202, and a bit line array 203 located in this order on the PUC circuit 1; a second dielectric layer 204 covering the first spacer layer 201, the channel layer 202, and the bit line array 203; a first contact line 206 coupled to the channel layer 202 vertically through the second dielectric layer 204; word lines 205 coupled to the bit line array 203 vertically through the second dielectric layer 204; wherein the first contact line 206 on the even columns is used for connection to the ground.
In this embodiment, the first separation layer 201 is formed as a layer structure separating the PUC circuit 1 and the memory structure, which may be formed over the PUC circuit 1 by a nitrogen-doped carbon metal oxide deposition process. The metal oxide may be an oxide of one or more metals, such as Cu, co, al, nickel (Ni), titanium (Ti), W, or other suitable metals. The first separator layer 201 can be formed from one or more thin film deposition processes including, but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. In one embodiment, a layer of nitrogen-doped carbon copper oxide is deposited over the PUC circuit 1.
In this embodiment, a channel layer 202 is formed over the first separation layer 201. The material of the channel layer 202 may be amorphous silicon or polysilicon. The channel layer 202 may be formed by one or more thin film deposition processes including, but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. In one embodiment, a polysilicon layer is formed by deposition on the first spacer layer 201.
In this scheme, bit line array 203 is formed on a polysilicon layer. Specifically, a silicon dioxide tunnel dielectric layer is deposited, then a silicon nitride charge trap is deposited, and then an aluminum oxide high-k gate dielectric is deposited, so that an ONO three-layer composite structure dielectric layer is formed. After the deposition of the medium layer of the ONO three-layer composite structure is finished, etching is performed on the ONO layer by using a mask process, so as to form the bit line array 203.
In this embodiment, the second dielectric layer 204 is covered on the first separation layer 201, the channel layer 202 and the bit line array 203 by a deposition process. The second dielectric layer 204 may be formed using an ultra-low k dielectric material based on a chemical mechanical polishing process. Subsequently, a contact hole is formed vertically through the second dielectric layer 204 by a mask process and an etching process, and a contact line is filled in the contact hole. A contact line filled in a contact hole corresponding to the channel layer 202 is connected with the channel layer 202 to form a first contact line 206; the contact lines filled in the contact holes corresponding to the bit line array 203 are connected to the bit line array 203 to form word lines 205. Wherein the first contact line 206 on the even columns is used for connection to the ground.
In this embodiment, a contact layer 3 is further formed on the two-dimensional semiconductor memory structure 2 to form a bit line connection. Specifically, the contact layer 3 includes: a second separation layer 301 and a third dielectric layer 302 sequentially overlying the second dielectric layer 204; a second contact line 303 passing vertically through the third dielectric layer 302 and the second separation layer 301; wherein the first contact line 206 located on the odd columns is coupled with the second contact line 303 to form a word line 205.
In this embodiment, the second separation layer 301, which is a layer structure separating the memory structure and the contact layer 3, may be formed over the PUC circuit 1 by a nitrogen-doped carbon metal oxide deposition process. The metal oxide may be an oxide of one or more metals, such as Cu, co, al, nickel (Ni), titanium (Ti), W, or other suitable metals. The first separator layer 201 can be formed from one or more thin film deposition processes including, but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. In one embodiment, a layer of nitrogen-doped carbon copper oxide is deposited over the PUC circuit 1.
In this embodiment, a third dielectric layer 302 is formed over the second separation layer 301. The third dielectric layer 302 may be formed using an ultra-low k dielectric material based on a chemical mechanical polishing process. Subsequently, a contact hole is formed vertically through the third dielectric layer 302 by a mask process and an etching process, and a contact line is filled in the contact hole to form a second contact line 303. The first contact line 206 located on the odd columns is coupled to the second contact line 303 to form a bit line connection.
As shown in fig. 6, the data storage unit in the two-dimensional semiconductor memory structure on the PUC circuit in this scheme can operate bit lines (bit-lines) and word-lines (word-lines) through the peripheral circuits. In one embodiment, the circuit connection may be accomplished through configuration and routing (place and routing, P & R).
Compared with a two-dimensional NOR gate flash memory (2D NOR Flash Memory) in the prior art, which is formed by placing the PUC circuit below the two-dimensional semiconductor memory structure, the three-dimensional NOR gate semiconductor memory device (3D NOR Flash memory) formed by placing the PUC circuit below the two-dimensional semiconductor memory structure has the advantages that the chip area is reduced by about 15-20%, the reading speed is improved by 20-30%, and the writing speed is improved by 20-25%.
In summary, according to the three-dimensional nor gate semiconductor memory device (3D NOR Flash memory) of the present disclosure, consumption of the chip space by the PUC circuit can be reduced, space utilization of the nor gate flash memory device can be improved, storage density can be increased, and cost can be reduced.
Correspondingly, the scheme also provides a manufacturing method of the semiconductor memory device. Fig. 2 to 5 are schematic structural diagrams illustrating an embodiment of a method for forming a semiconductor device according to the present invention and corresponding steps. In particular, the method comprises the steps of,
as shown in fig. 2, a flow chart of a method for manufacturing a semiconductor device according to the present embodiment is shown. The method comprises the following steps:
step S1, taking the PUC circuit 1 as a substrate;
step S2, forming a two-dimensional semiconductor storage structure 2 on the substrate;
step S3, forming a contact layer 3 on the two-dimensional semiconductor memory structure 2.
Next, a detailed description will be given of a specific process of the semiconductor device forming method according to the present embodiment with reference to fig. 3 to 5.
In this embodiment, the selected PUC circuit 1 can be used as a substrate, and the two-dimensional semiconductor memory structure 2 can be manufactured thereon. The PUC circuit 1 may also be manufactured first according to the selected PUC circuit 1 structure. In one embodiment, the PUC circuit 1 is a MOS device, and the manufacturing of the PUC circuit 1 is performed first, which includes the steps of: providing an insulating layer 101; forming a plurality of semiconductor structures having wiring layers on the insulating layer 101; forming trenches 102 between adjacent semiconductor structures; wherein the conductivity types of adjacent two semiconductor structures are different.
In this embodiment, the insulating layer 101 mainly provides a process platform for the semiconductor structure in the PUC circuit 1. In one embodiment, the insulating layer 101 may be a glass substrate.
A plurality of semiconductor structures having wiring layers are formed on the insulating layer 101 of the glass substrate. In particular, the method comprises the steps of,
as shown in fig. 3, a first region 103 having a first conductivity type is formed on the insulating layer 101 as a substrate structure. For example, doping may be performed on the silicon substrate to form the first region 103. The first conductivity type may be P-type or N-type. In other embodiments, the substrate material may also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate may also be a silicon-on-insulator substrate, a germanium-on-insulator substrate, a glass base, or a III-V compound substrate (e.g., gallium nitride base, gallium arsenide substrate, etc.). In one embodiment, when the conductivity type of the semiconductor device is N-type, the silicon substrate is P-doped to form a P-type substrate. Wherein, the P-type impurity can be one or more of boron ions, gallium ions and indium ions.
As shown in fig. 3, a first well region 104 and a second well region 105 are formed in the first region 103. The process of forming the first well region 104 and the second well region 105 may be a diffusion process or an ion implantation process. In one embodiment, the process of forming the first well region 104 and the second well region 105 in the first region 103 is: a first pattern layer (not shown) is formed on the surface of the first region 103, and the first pattern layer has an opening exposing a portion of the first region 103, and ion implantation is performed along the opening into the exposed first region 103 by using the first pattern layer as a mask, so as to form a first well region 104 and a second well region 105.
In one embodiment, the conductivity type of the first well region 104 and the second well region 105 is opposite to the conductivity type of the first region 103, i.e. the type of ions implanted in the first well region 104 and the second well region 105 is opposite to the type of doping ions in the first region 103. If the first region 103 is doped with P-type, the first well region 104 and the second well region 105 are ion-implanted with N-type impurity ions, wherein the N-type impurity ions are one or more of phosphorus ions, arsenic ions and antimony ions.
In one embodiment, the material of the first pattern layer is a photoresist material. After forming the first well region 104 and the second well region 105, the first pattern layer is removed using a wet photoresist removal or ashing process.
As shown in fig. 3, next, a source region 106 may be formed in the first well region 104 by a doping process, and a drain region 107 may be formed in the first well region 104. The source region 106 and the drain region 107 may be formed using an ion implantation process. In one embodiment, the process of forming the source region 106 and the drain region 107 in the first well region 104 and the second well region 105 respectively includes: first, a second pattern layer (not shown) is formed on the surface of the first region 103, the second pattern layer has an opening exposing a portion of the first well region 104 and a portion of the second well region 105, and ion implantation is performed into the exposed first well region 104 and second well region 105 along the opening, respectively, using the second pattern layer as a mask, to form a source region 1069 in the first well region 104, and a drain region 10711 in the second well region 105. After forming the source region 106 and the drain region 107, the second pattern layer is removed. The material of the second pattern layer may be a photoresist material, and the process of removing the photoresist material is as described above, which is not described herein.
In one embodiment, the first well region 104 and the second well region 105 are both N-wells, and in the process of forming the source region 106 and the drain region 107, the type of the ion implanted ions in the source region 106 and the drain region 107 is P-type impurity ions, where the P-type impurity may be one or several of boron ions, gallium ions, and indium ions.
As shown in fig. 3, a second region 108 having the first conductivity type is formed at a side of the first well region 104 adjacent to the second well region 105, and a second region 108 having the first conductivity type is formed at a side of the second well region 105 adjacent to the first well region 104. The second region 108 may be formed by an ion implantation process to form a buried layer. In one embodiment, the conductivity type of the first well region 104 and the second well region 105 is N type, and the type of ion implantation of the second region 108 is P type impurity ions, and the P type impurity may be one or several of boron ions, gallium ions, and indium ions.
As shown in fig. 3, a gate structure 109 is formed over the first region 103, the gate structure 109 may include: a gate insulating layer on the first region 103, a gate electrode on the gate insulating layer, and a spacer on a side of the gate electrode; a portion of the gate and a portion of the spacer are located over the first well region 104 and the second well region 105.
Specifically, the process of forming the gate structure 109 includes: spacers on both sides of the gate structure 109 are formed by deposition and etching processes; forming a gate insulating layer on the second region 108 between the spacers at both sides by using a chemical vapor deposition or physical vapor deposition process; after the gate insulating layer is formed, a semiconductor layer is formed on the gate insulating layer, and the semiconductor layer is planarized by chemical mechanical polishing or the like to form a gate electrode between the spacers on both sides.
As shown in fig. 3, the step of manufacturing the PUC circuit 1 further includes: forming a first dielectric layer 110 on the semiconductor structure, and covering photoresist on the first dielectric layer after the treatment by using a Chemical Mechanical Polishing (CMP) process, wherein the photoresist is provided with an opening exposing part of the first dielectric layer 110, and the openings respectively correspond to the positions of the source region 106, the grid electrode and the drain region 107; etching is performed along the openings respectively, so as to form contact holes communicated with the source region 106, the grid electrode and the drain region 107. After the contact hole is formed, the photoresist is removed. In one embodiment, only a portion of the semiconductor structure of the PUC circuit 1 is in communication with the contact hole over the source region 106 and routed. For example, only the source regions 106 of the semiconductor structures in the first column are connected with metal lines.
As shown in fig. 3, trench 102 isolation is formed between adjacent semiconductor structures. The trench 102 isolation may be formed by an etching process to form shallow trench 102 isolation (Shallow Trench Isolation, STI). Wherein the trench 102 is filled with silicon dioxide.
The step of forming a two-dimensional semiconductor memory structure 2 on the substrate comprises:
as shown in fig. 4, a first separation layer 201 is formed by forming a layer of nitrogen-doped carbon copper oxide over the PUC circuit 1 using a deposition process. The metal oxide employed for the first spacer layer 201 may be an oxide of one or more metals, such as Cu, co, al, nickel (Ni), titanium (Ti), W, or other suitable metals. The first separator layer 201 can be formed from one or more thin film deposition processes including, but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof.
A channel layer 202 is formed over the first separation layer 201 by a deposition process. The material of the channel layer 202 may be amorphous silicon or polysilicon. The channel layer 202 may be formed by one or more thin film deposition processes including, but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof.
As shown in fig. 4, an ONO triple layer composite dielectric layer is formed over channel layer 202. Specifically, first, a silicon dioxide tunnel dielectric layer is deposited on the channel layer 202; then, depositing a layer of silicon nitride charge traps on the silicon dioxide tunnel dielectric layer; finally, an alumina high-k gate dielectric layer is deposited on the silicon nitride through ALD or CVD process, so that the ONO three-layer composite structure dielectric layer is formed.
And covering photoresist on the ONO three-layer composite structure dielectric layer, wherein the photoresist is provided with an opening exposing part of the ONO three-layer composite structure dielectric layer, photoetching and etching are carried out along the ONO three-layer composite structure dielectric layer exposed by the opening until the channel layer 202 is stopped, and a row of bit lines is formed.
As shown in fig. 5, a second dielectric layer 204 is formed on the first spacer 201, the channel layer 202 and the bit line array 203 by using an ultra-low k dielectric material through a deposition process, and after being processed by using a CMP process, a photoresist is covered thereon, the photoresist has an opening exposing a portion of the second dielectric layer 204, the opening corresponding to the positions of the bit line array 203 and the channel layer 202, or corresponding to the positions of the bit line array 203, the channel layer 202 and the first spacer 201, respectively; and respectively carrying out photoetching and etching along the opening to form a contact hole. After the contact hole is formed, the photoresist is removed. In one embodiment, a contact line is filled in a contact hole in communication with the bit line array 203 to form a word line 205; a contact line is filled in a contact hole communicating with the channel layer 202 or the first separation layer 201, and a first contact line 206 is formed. Wherein the first contact line 206 on the even columns is used for connection to the ground.
As shown in fig. 1, the step of forming the contact layer 3 on the two-dimensional semiconductor memory structure 2 includes:
a layer of nitrogen doped carbon copper oxide is formed over the second dielectric layer 204 using a deposition process to form a second spacer layer 301. The metal oxide employed for the second separation layer 301 may be an oxide of one or more metals, such as Cu, co, al, nickel (Ni), titanium (Ti), W, or other suitable metals. The second separation layer 301 may be formed from one or more thin film deposition processes including, but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof.
And forming a third dielectric layer 302 above the second separation layer 301 by using an ultra-low k dielectric material through a deposition process, and covering photoresist above the third dielectric layer 302 after being treated by using a Chemical Mechanical Polishing (CMP) process, wherein the photoresist is provided with an opening exposing part of the third dielectric layer 302, and photoetching and etching are performed along the opening at the position of the first contact hole to form a contact hole. After the contact hole is formed, the photoresist is removed. In one embodiment, the contact hole in the third dielectric layer 302 is filled with a contact line to form a second contact line 303; the second contact line 303 is coupled to the first contact line 206 located on the odd columns to form a bit line contact.
The method further comprises a wiring configuration step of the data storage unit. As shown in fig. 6, the data storage unit in the two-dimensional semiconductor memory structure on the PUC circuit in this scheme can operate bit lines (bit-lines) and word-lines (word-lines) through the peripheral circuits. In one embodiment, the circuit connection may be accomplished through configuration and routing (place and routing, P & R).
By using the method for manufacturing the semiconductor memory device, a NOR gate flash memory structure such as a two-dimensional charge trap junction-free field effect transistor flash memory (Junctionless Charge Trap Transistor Flash) structure and a PUC circuit (Peri underwell) structure can be combined to form a novel 3D NOR gate memory device. The 3D NOR gate memory device stacks the circuit for driving the memory cells below the cell array for storing data, breaks through the limitation of the existing two-dimensional NOR gate flash memory, thereby reducing the consumption of the PUC circuit on the space of a chip, improving the space utilization rate of the NOR gate flash memory device, improving the storage density and reducing the cost. The 3D NOR gate memory device can be used as an embedded NOR gate flash memory and can also form a standard independent NOR gate memory product.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (14)
1. A NOR-type semiconductor memory device, comprising:
a two-dimensional semiconductor memory structure located on a PUC circuit, the two-dimensional semiconductor memory structure comprising: a first separation layer, a channel layer and a bit line array sequentially located on the PUC circuit; a second dielectric layer covering the first spacer layer, channel layer and bit line array; a first contact line vertically passing through the second dielectric layer and coupled to the channel layer; word lines vertically coupled to the bit line array through the second dielectric layer; wherein the first contact lines on even columns are used for connecting wires with the ground electrode;
the PUC circuit includes: a plurality of semiconductor structures having wiring layers on the insulating layer; the conductivity types of two adjacent semiconductor structures are different and are isolated by a groove; the wiring layer includes: a first dielectric layer overlying the semiconductor structure and a plurality of peripheral lines within the first dielectric layer; the peripheral circuit is correspondingly connected with a source electrode, a drain electrode and a grid electrode in the semiconductor device;
and a contact layer over the two-dimensional semiconductor memory structure.
2. The semiconductor memory device of claim 1, the semiconductor structure comprising:
a first region having a first conductivity type on the insulating layer;
a first well region and a second well region of a second conductivity type located within the first region, the first well region and the second well region being spaced apart by the first region;
the source region is positioned in the first well region, and the drain region is positioned in the second well region;
and a second region with the first conductivity type positioned on one side of the first well region close to the second well region, and a second region with the first conductivity type positioned on one side of the second well region close to the first well region.
3. The semiconductor memory device according to claim 2, wherein the first conductivity type is P-type and the second conductivity type is N-type; or the first conductivity type is N type, and the second conductivity type is P type.
4. The semiconductor memory device of claim 2, wherein the semiconductor structure further comprises: and a gate structure located on the first region.
5. The semiconductor memory device according to claim 4, wherein the gate structure comprises: a gate insulating layer on the first region, a gate on the gate insulating layer, and a spacer on a side of the gate.
6. The semiconductor memory device according to claim 1, wherein the contact layer comprises:
a second separation layer and a third dielectric layer which are sequentially covered on the second dielectric layer;
a second contact line vertically passing through the third dielectric layer and the second separation layer; wherein the first contact line located on the odd columns is coupled to the second contact line.
7. The semiconductor memory device according to claim 6, wherein the first separation layer and/or the second separation layer is a nitrogen-doped copper oxycarbide layer; and/or the number of the groups of groups,
the channel layer is a polysilicon layer; and/or the number of the groups of groups,
the bit line array is formed by adopting an ONO three-layer composite structure dielectric layer based on an etching process; and/or the number of the groups of groups,
the second dielectric layer is formed by adopting an ultralow-k dielectric material and based on a chemical mechanical polishing process.
8. A method of manufacturing a NOR-type semiconductor memory device, the method comprising the steps of:
forming a PUC circuit and taking the PUC circuit as a substrate; the manufacturing steps of the PUC circuit comprise: providing an insulating layer; forming a plurality of semiconductor structures having wiring layers on the insulating layer; forming a trench between adjacent semiconductor structures; wherein the conductivity types of two adjacent semiconductor structures are different; forming a two-dimensional semiconductor memory structure on the substrate, the two-dimensional semiconductor memory structure comprising: a first separation layer, a channel layer and a bit line array sequentially located on the PUC circuit; a second dielectric layer covering the first spacer layer, channel layer and bit line array; a first contact line vertically passing through the second dielectric layer and coupled to the channel layer; word lines vertically coupled to the bit line array through the second dielectric layer; wherein the first contact lines on even columns are used for connecting wires with the ground electrode; forming a contact layer on the two-dimensional semiconductor memory structure, the contact layer manufacturing step further comprising: forming a first dielectric layer on the semiconductor structure; forming a plurality of contact holes in the first dielectric layer, and filling peripheral circuits in the contact holes; wherein, the peripheral circuit is correspondingly connected with the source electrode, the drain electrode and the grid electrode.
9. The method of claim 8, wherein the step of fabricating the semiconductor structure comprises:
forming a first region having a first conductivity type on the insulating layer;
forming a first well region and a second well region of a second conductivity type within the first region, the first well region and the second well region being separated by the first region;
forming a source region in the first well region and forming a drain region in the second well region;
and forming a second region with the first conductivity type on one side of the first well region close to the second well region, and forming a second region with the first conductivity type on one side of the second well region close to the first well region.
10. The method of claim 9, wherein the first conductivity type is P-type and the second conductivity type is N-type; or the first conductivity type is N type, and the second conductivity type is P type.
11. The method of claim 9, wherein the step of fabricating the semiconductor structure further comprises: and forming a gate structure on the first region.
12. The method of claim 11, wherein the gate structure comprises: a gate insulating layer on the first region, a gate electrode on the gate insulating layer, and a spacer on a side of the gate electrode; wherein a portion of the gate and a portion of the spacer are located over the first well region and the second well region.
13. The method of claim 8, wherein the step of fabricating the contact layer comprises:
sequentially forming a second separation layer and a third dielectric layer on the second dielectric layer;
forming a second contact hole vertically penetrating through the third dielectric layer, and arranging a second contact line in the second contact line; wherein the first contact line located on the odd columns is coupled to the second contact line.
14. The method of claim 13, wherein the first and/or second separation layer is a nitrogen doped copper oxycarbide layer; and/or the number of the groups of groups,
the channel layer is a polysilicon layer; and/or the number of the groups of groups,
the bit line array is formed by adopting an ONO three-layer composite structure dielectric layer based on an etching process; and/or the number of the groups of groups,
the second dielectric layer is formed by adopting an ultralow-k dielectric material and based on a chemical mechanical polishing process.
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