JP4651461B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a flash memory having an auxiliary gate electrode configuration (hereinafter referred to as an auxiliary gate electrode type flash memory) and a technique effective when applied to the manufacturing technique.

An auxiliary gate electrode type flash memory is disclosed in, for example, Japanese Patent Laid-Open No. 2005-85903 (Patent Document 1). A plurality of auxiliary gate electrodes extending in a predetermined direction are arranged adjacent to each other on a semiconductor substrate in the memory area of the flash memory. On each auxiliary gate electrode, a cap insulating film made of, for example, silicon nitride is formed. In the upper layer of the plurality of auxiliary gate electrodes, a plurality of word lines extending in a direction perpendicular to the extending direction of the auxiliary gate electrodes are arranged adjacent to each other. A floating gate electrode is arranged between each of the plurality of auxiliary gate electrodes and between each of the word lines and the semiconductor substrate in a state of being electrically separated from other members. . The floating gate electrode is formed so that the height of the upper surface is higher than the height of the upper surface of the auxiliary gate electrode.
JP 2005-85903 A

  However, the present inventor has found that the auxiliary gate electrode type flash memory has the following problems.

  That is, there is a problem that the information (“0” or “1”) stored in the memory cell is garbled as a result of the threshold voltage of the memory cell changing due to the parasitic capacitance between adjacent bits. In particular, until the 0.13 μm process generation, since the space between adjacent bits is wide, the parasitic capacitance between adjacent bits is small and the problem has not been revealed. However, in the 90 nm process generation with advanced miniaturization, the threshold voltage fluctuates. This becomes a big problem.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a technique capable of improving the reliability of a semiconductor device having an auxiliary gate electrode type flash memory.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  That is, according to the present invention, in the cap insulating film mainly composed of silicon nitride formed on the auxiliary gate electrode, the thickness of the cap insulating film between adjacent word lines is set to the cap between the word line and the auxiliary gate electrode. It is made thinner than the thickness of the insulating film.

  According to the present invention, in the step of patterning the word line, a part of the cap insulating film mainly composed of silicon nitride on the auxiliary gate electrode between adjacent word lines is etched.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  That is, in the cap insulating film mainly composed of silicon nitride formed on the auxiliary gate electrode, the thickness of the cap insulating film between adjacent word lines is set to the thickness of the cap insulating film between the word line and the auxiliary gate electrode. By making the thickness smaller than this, the parasitic capacitance between the adjacent bits in the oblique direction can be reduced, so that fluctuations in the threshold voltage of the memory cell can be suppressed or prevented. Therefore, the reliability of the semiconductor device having the auxiliary gate electrode type flash memory can be improved.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges. Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted as much as possible. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  First, the problem will be described. FIG. 22 is a perspective view showing the main part of the memory area of the flash memory examined by the present inventors. The symbol Y indicates the extending direction of the local data line in the first direction, and the symbol X indicates the extending direction of the word line WL in the second direction orthogonal to the first direction.

  A plurality of auxiliary gate lines AGL extend along the first direction Y on the semiconductor substrate. A cap insulating film 51 made of, for example, silicon nitride is formed on the plurality of auxiliary gate lines AGL. Between the adjacent auxiliary gate lines AGL, the floating gate electrode FGE is disposed in a state of being electrically isolated from other members. Here, a floating gate electrode FGE for 4 bits is illustrated.

  In the flash memory having such a configuration, as a result of the threshold voltage of the bit Bt selected by the capacitances CA, CB, CC between the bits Bt changing, the information (“0” or “1”) stored in the memory cell is changed. ) Has become a problem. In particular, until the 0.13 μm process generation, since the space between adjacent bits is wide, the parasitic capacitance between adjacent bits is small and the problem has not been revealed. However, the 90 nm process generation (for example, the bit Bt indicated by the capacitance CC) has been miniaturized. In the case of products having an interval of 90 nm or less), the threshold voltage fluctuates and becomes a serious problem. Further, according to the study by the inventors, the capacitance CB between the bits Bt adjacent in the oblique direction is greatly influenced by the cap insulating film 51 having a high dielectric constant. Therefore, the present embodiment provides a technique for reducing the capacitance CB between the bits Bt adjacent in the oblique direction. Hereinafter, a specific example of the semiconductor device of this embodiment will be described.

  The semiconductor device of the present embodiment is, for example, a 4 Gb (Gigabit) AND type flash memory. This flash memory is used as a storage medium for various portable devices such as portable personal computers, digital still cameras, portable music players, digital video cameras, PDAs (Personal Digital Assistants), cellular phones, etc., information devices or communication devices. used.

  FIG. 1 schematically shows a circuit diagram of a main part of the memory cell region M1 of the flash memory according to the present embodiment. The arrow Y indicates the first direction, and the arrow X orthogonal to the first direction Y indicates the second direction.

  In the memory cell region M1, a plurality of auxiliary gate lines (first gate electrodes) AGL extending in the first direction Y are arranged along the second direction X. In the memory cell region M1, a plurality of word lines WL extending in the second direction X are arranged side by side along the first direction Y. Further, in the memory cell region M1, nonvolatile memory cells (hereinafter referred to as memory cells) MC are arranged in the vicinity of the intersections of the plurality of auxiliary gate lines AGL and the plurality of word lines WL.

  Each memory cell MC is connected in parallel between adjacent local data lines BL (drain line DL and source line SL). However, the drain line DL and the source line SL are not formed on a semiconductor substrate (hereinafter referred to as a substrate) from the beginning, and a desired voltage is applied to the auxiliary gate wiring AGL when information is written or read as described later. Is applied to form an inversion layer generated in the substrate portion facing the auxiliary gate line AGL.

  Each memory cell MC has a memory MIS • FETQm that contributes to information storage. The memory MIS • FETQm has a floating gate electrode (second gate electrode) and a control gate electrode (third gate electrode). The floating gate electrode of the memory MIS • FETQm is an electrode in which charges contributing to information storage are accumulated. The control gate electrode of the memory MIS • FETQm is formed by a part of the word line WL. The control gate electrodes of the plurality of memories MIS • FETs Qm arranged along the second direction X are electrically connected to each word line WL. The width (short dimension, first dimension Y dimension) of the word line WL is, for example, 90 nm.

  2 is a plan view of the main part of the memory cell region M1 in FIG. 1, FIG. 3 is a sectional view taken along line X1-X1 in FIG. 2, FIG. 4 is a sectional view taken along line X2-X2 in FIG. 2 is a cross-sectional view taken along line Y1-Y1 in FIG. 2, and FIG. 6 is a cross-sectional view taken along line Y2-Y2 in FIG. Although FIG. 2 is a plan view, the junction element isolation region (active region) is hatched in order to make the drawing easy to see. Further, in FIG. 2, some members are omitted for easy understanding of the drawing.

The memory cell region M1 of the flash memory according to the present embodiment is a so-called contactless type array having no contact hole for each memory cell MC. The substrate 1 is made of, for example, p-type silicon (Si) single crystal. The symbol DNW indicates an n-type buried region, and the symbol PWL indicates a p-well. The p-well PWL is surrounded by the underlying n-type buried region DNW. On the main surface of the substrate 1, a gate insulating film (first gate insulating film) 2a made of, for example, silicon oxide (SiO ₂ or the like, having a dielectric constant of 3.8) is interposed in the first direction of FIG. A plurality of strip-like auxiliary gate lines AGL extending in Y are arranged side by side in the second direction X so as to be along each other. Each auxiliary gate line AGL is made of, for example, low-resistance polysilicon, and a cap insulating film 3 is formed on the upper surface of each auxiliary gate line AGL. The cap insulating film 3 is made of, for example, silicon nitride (Si ₃ N ₄ or the like, the dielectric constant is 7 to 8 for example), and the thickness thereof is, for example, about 50 nm. Further, side walls (side wall insulating films) 4 made of, for example, silicon oxide are formed on the side surfaces of each auxiliary gate wiring AGL and the cap insulating film 3.

  N-type semiconductor regions for the drain line DL and the source line SL are not formed on the substrate 1. By applying a desired voltage to the auxiliary gate line AGL during the write and read operations of the flash memory, an n-type inversion layer is formed on the main surface portion (p well PWL) of the substrate 1 facing the auxiliary gate line AGL. Thus, the drain line DL (drain region) and the source line SL (source region) are formed. That is, since the inversion layer is used as the local data line BL, a diffusion layer is not required in the memory array, and the data line pitch can be reduced. In addition, since the trench isolation part is not formed in the memory array, the area of the memory array can be reduced. Further, since the drain line DL and the source line SL of the adjacent memory cells MC are shared, the area occupied by the memory array can be reduced.

Above the auxiliary gate wiring AGL, a plurality of strip-like word lines WL extending in the second direction X of FIG. 2 through the cap insulating film 3 and the interlayer insulating film (interlayer insulating film) 5 They are arranged side by side in the first direction Y of FIG. 2 so as to be parallel to each other. The insulating film 5 is formed of a laminated film in which, for example, a silicon oxide film, a silicon nitride (Si ₃ N ₄ or the like), and a silicon oxide film are sequentially deposited from the lower layer. Each word line WL is formed of, for example, a laminated film of low-resistance polysilicon and tungsten silicide (WSi _x ) thereon, and a part of the word line WL serves as the control gate electrode CGE. On each word line WL, an insulating film 6 made of, for example, silicon oxide is formed.

  The floating gate electrode FGE of the memory MIS • FETQm is adjacent to the auxiliary gate wiring AGL and is located in a position where the word line WL overlaps in plane, that is, between the opposing surfaces of the control gate electrode CGE and the substrate 1. Is formed in a state of being insulated from other portions. The floating gate electrode FGE is made of, for example, low-resistance polysilicon, and is formed on the main surface (third main surface portion) of the substrate 1 via a gate insulating film (second gate insulating film) 2b made of, for example, a silicon oxide film. Has been. The floating gate electrode FGE is insulated from the auxiliary gate line AGL by the sidewall 4 and insulated from the word line WL by the insulating film 5. The floating gate electrode FGE is formed such that the height from the main surface of the substrate 1 to the upper surface of the floating gate electrode FGE is higher than the height from the main surface of the substrate 1 to the upper surface of the auxiliary gate wiring AGL. Yes. That is, the floating gate electrode FGE is formed in a convex shape in cross section. An adjacent interval between the floating gate electrodes FGE adjacent along the second direction X is, for example, about 90 nm.

  Here, in the configuration in which the floating gate electrode having a concave cross section is formed between the adjacent auxiliary gate lines AGL, when the memory cell MC is reduced, the adjacent interval between the auxiliary gate lines AGL is also narrowed, and therefore the floating gate electrode FGE. Therefore, it is necessary to reduce the thickness of the conductor film for forming the floating gate electrode, which makes it difficult to process the floating gate electrode. On the other hand, when the floating gate electrode FGE has a convex cross section, the processing of the floating gate electrode FGE can be facilitated even if the memory cell MC is reduced. Therefore, the miniaturization of the memory cell MC is promoted. it can. Further, since the capacitors of the floating gate electrode FGE and the control gate electrode CGE are formed on the convex sidewall surface and the convex upper surface of the floating gate electrode FGE, even if the minimum processing dimension is further reduced, the floating gate electrode FGE By increasing the height, the facing area between the floating gate electrode FGE and the control gate electrode CGE can be increased. That is, since the capacitance of the capacitor can be increased without increasing the area occupied by the memory cell MC, the coupling ratio between the floating gate electrode FGE and the control gate electrode CGE can be improved. Therefore, the controllability of the voltage control of the floating gate electrode FGE by the control gate electrode CGE can be improved, so that the writing and erasing speed of the flash memory can be improved even at a low voltage, and the operating voltage of the flash memory can be increased. The voltage can be lowered. That is, both miniaturization and low voltage of the flash memory can be realized.

  On the main surface of the substrate 1, insulating films 7a and 7b made of, for example, silicon oxide are sequentially deposited from below. The insulating film 7a is buried between the word lines WL adjacent to each other in the first direction Y and between the floating gate electrodes FGE adjacent to each other in the first direction Y. By the insulating film 7a, the insulating films 7a are mutually connected in the first direction Y. The adjacent word lines WL and the floating gate electrodes FGE adjacent to each other in the first direction Y are insulated and separated. In the present embodiment, the main surface portion of the substrate 1 facing the floating gate electrode FGE is slightly shaved by the etching damage layer removal process described later, and the height of the main surface portion is determined by the auxiliary gate wiring. The AGL is slightly lower than the height of the main surface portion of the substrate 1 facing the AGL.

  Here, in the present embodiment, as shown in FIG. 5, the height of the cap insulating film 3 between the adjacent word lines WL is equal to that of the cap insulating film 3 between the word line WL and the auxiliary gate wiring AGL. It is lower than the height by a dimension D1. That is, the cap insulating film 3 between adjacent word lines WL is formed thinner than the cap insulating film 3 between the word line WL and the auxiliary gate wiring AGL. As a result, the parasitic capacitance between the bits (memory cells MC) adjacent in the oblique direction can be reduced, so that fluctuations in the threshold voltage of the memory cells MC (memory MIS • FETQm) can be suppressed or prevented. Therefore, the reliability of the flash memory can be improved.

  The thickness D2 of the cap insulating film 3 between the adjacent word lines WL is set to about half or less of the thickness D of the cap insulating film 3 between the word line WL and the auxiliary gate wiring AGL. Of course, the cap insulating film 3 may not be provided between adjacent word lines WL. Rather, when only the viewpoint of reducing the parasitic capacitance is considered, it is preferable that the cap insulating film 3 is not provided between the word lines WL. However, if etching is performed to completely eliminate the cap insulating film 3 between adjacent word lines WL, damage or the like is caused on the lower auxiliary gate wiring AGL, and the electrical characteristics (resistance, etc.) of the auxiliary gate wiring AGL are reduced. May fluctuate. Therefore, in this embodiment, the cap insulating film 3 is left adjacent to the word line WL. The thickness D2 of the cap insulating film 3 left between the adjacent word lines WL is, for example, about 10 nm to 20 nm. That is, the thickness of the cap insulating film 3 left between adjacent word lines WL is set to about 20% to 40% of the thickness of the cap insulating film 3 between the word line WL and the auxiliary gate wiring AGL. . As a result, the parasitic capacitance between the bits (memory cells MC) adjacent in the oblique direction can be reduced without causing a change in the electrical characteristics of the auxiliary gate line AGL.

  Next, an example of the operation of the flash memory according to the present embodiment will be described with reference to FIGS.

  FIG. 7 is a principal circuit diagram of the memory cell region M1 during the read operation, and FIG. 8 is a cross-sectional view taken along line X1-X1 of FIG. 2 during the read operation.

  In the data read operation, for example, about 2 to 5 V is applied to the word line WL0 to which the control gate electrode CGE of the memory MIS • FETQm0 of the selected memory cell MC is connected to determine the threshold value of the selected memory MIS • FETQm0. . Further, a negative voltage of, for example, about 0V or −2V is applied to the other word lines WL to turn off the unselected memory MIS • FETQm. Further, by applying, for example, about 5 V to the auxiliary gate lines AGLs and AGLd for forming the source and drain of the selected memory MIS • FETQm0, the source lines are respectively formed on the main surface portions of the substrate 1 facing the auxiliary gate lines AGLs and AGLd. An n-type inversion layer IL1 for SL and drain line DL is formed. Further, for example, 0 V is applied to the other auxiliary gate lines AGL so that an inversion layer is not formed on the main surface portion of the substrate 1 opposed to the auxiliary gate lines AGL, and the selected memory MIS • FETQm0 and Isolation with the non-selected memory MIS • FETQm is performed. Here, for example, about 1V is applied to the global data line to which the n-type inversion layer IL1 for the source line SL of the selected memory MIS • FETQm0 is connected, and for example, 0V is applied to the other global data lines. In this state, a voltage of about 0 V applied to the common drain wiring is supplied to the drain of the selected memory MIS • FETQm0 through the n-type inversion layer IL1 for the drain line DL. In this way, data is read from the selected memory MIS • FET Qm0 so that a read current IR flows from the global data line toward the common drain line. At this time, the threshold voltage of the selection memory MIS • FETQm0 changes depending on the state of the charge stored in the floating gate electrode FGE. Therefore, in the state of the current flowing between the source and drain of the selection memory MIS • FETQm0, the selection memory MIS • FETQm0. Can be determined. Here, according to the present embodiment, the thickness of the cap insulating film 3 between the adjacent word lines WL is made thinner than the thickness of the cap insulating film 3 between the word lines WL and the auxiliary gate wiring AGL. As a result, the parasitic capacitance between the bits (memory cells MC) adjacent in the oblique direction can be reduced, so that fluctuations in the threshold voltage of the memory cells MC (memory MIS • FETQm) can be suppressed or prevented. Therefore, the reliability of the flash memory can be improved.

  Next, FIG. 9 is a main circuit diagram of the memory cell region M1 during the write operation, and FIG. 10 is a cross-sectional view taken along the line X1-X1 of FIG. 2 during the write operation.

  Data writing is premised on a source side hot electron injection method by source side selection and constant charge injection. Thus, efficient data writing can be performed at high speed with low current. In the data write operation, for example, about 13V to 15V is applied to the word line WL0 to which the control gate electrode CGE of the memory MIS • FETQm0 of the selected memory cell MC is connected, for example, 0V is applied to other word lines WL and the like. Further, for example, about 2V is applied to the auxiliary gate wiring AGLs for forming the source of the selected memory MIS • FETQm0, and about 7V is applied to the auxiliary gate wiring AGLd for forming the drain of the selected memory MIS • FETQm0, for example. An n-type inversion layer IL1 for source formation is formed on the main surface portion of the substrate 1 facing the auxiliary gate wiring AGLs, and an n-type inversion for drain formation is formed on the main surface portion of the substrate 1 facing the auxiliary gate wiring AGLd. Layer IL1 is formed. For example, 0 V is applied to the other auxiliary gate lines AGL so that an inversion layer is not formed on the main surface portion of the substrate 1 facing the auxiliary gate lines AGL, and the selected memory MIS • FETQm0 and the non-selected memory MIS. -Isolation with the FET Qm. In this state, a voltage of about 4 V applied to the common drain wiring CD is supplied to the drain of the selected memory MIS • FETQm0 through the n-type inversion layer IL1 for the drain line DL. Further, for example, 0 V is applied to the global data line to which the n-type inversion layer IL1 for the source line SL of the selected memory MIS • FETQm0 is connected. Further, the p well PWL is held at 0V, for example. Then, a write current Iw flows from the drain to the source in the selected memory MIS • FETQm0, and at this time, the charge accumulated in the n-type inversion layer IL1 on the source side is used as a certain channel current to the gate insulating film 2b. Then, it is efficiently injected into the floating gate electrode FGE (constant charge injection method). As a result, data is written to the selected memory MIS • FETQm0 at high speed. On the other hand, the drain current does not flow from the drain to the source of the unselected memory MIS • FETQm0 so that data is not written. Note that an arrow e1 in FIG. 10 schematically shows a state of injection of data charges. In addition, multivalued data can be stored in each memory cell MC (memory MIS • FETQm). This multi-value storage is performed by changing the amount of hot electrons injected into the floating gate electrode FGE by changing the write time, for example, by making the write voltage of the word line WL constant, so that there are several kinds of threshold values. A memory cell MC having a level can be formed. That is, four or more values such as “00” / “01” / “10” / “11” can be stored. For this reason, the function for two memory cells MC can be realized by one memory cell MC. Therefore, it is possible to reduce the size of the flash memory.

  Next, in the data erasing operation, a negative voltage is applied to the word line WL to be selected, thereby performing FN (Fowler Nordheim) tunnel emission from the floating gate electrode FGE to the substrate 1. That is, for example, about −16 V is applied to the word line WL to be selected, while a positive voltage is applied to the substrate 1. For example, 0 V is applied to the auxiliary gate line AGL, and the n-type inversion layer IL1 is not formed. As a result, the charge for data stored in the floating gate electrode FGE is discharged to the substrate 1 through the gate insulating film 2b, and the data in the plurality of memory cells MC are erased collectively.

  Next, an example of a method for manufacturing the flash memory according to the present embodiment will be described with reference to FIGS. 11 to 21, X1-X1, X2-X2, Y1-Y1, and Y2-Y2 are the X1-X1, X2-X2, Y1-Y1, and Y2-lines in FIG. Sectional drawing of the location corresponded to Y2 line is shown.

  First, as shown in FIG. 11, a substrate 1 made of p-type silicon (Si) single crystal (planar substantially circular semiconductor plate called a semiconductor wafer at this stage) is prepared, and n-type embedded in this substrate 1. Region DNW and p well PWL are formed in this order. Subsequently, a gate insulating film 2a made of, for example, silicon oxide or the like and having a thickness of about 10 nm is formed on the p well PWL of the substrate 1 by a thermal oxidation method such as an ISSG (In-Situ Steam Generation) oxidation method. Subsequently, a conductor film (first conductor layer) 10 made of low resistance polysilicon doped with, for example, phosphorus (P) is deposited on the main surface of the substrate 1, and a cap insulating film made of, for example, silicon nitride is deposited thereon. A (first insulating film) 3 is deposited, and a dummy insulating film (second insulating film) 11 made of, for example, silicon oxide is further deposited thereon. The conductor film 10, the cap insulating film 3, and the dummy insulating film 11 are deposited by, for example, a CVD (Chemical Vapor Deposition) method. Thereafter, as shown in FIG. 12, the dummy insulating film 11, the cap insulating film 3, and the conductor film 10 are patterned by a dry etching process using an etching mask, thereby forming an auxiliary gate wiring AGL by the conductor film 10. The dummy insulating film 11, the cap insulating film 3, and the auxiliary gate wiring AGL at this stage have a strip-like pattern extending in the first direction Y and are arranged in stripes.

  Next, as shown in FIG. 13, the substrate 1 (semiconductor wafer) is subjected to a thermal oxidation process such as an ISSG oxidation method, and a high-quality insulating film made of, for example, silicon oxide on the side surfaces of the auxiliary gate wiring AGL and the like. Then, an insulating film 4A made of, for example, silicon oxide is deposited on the main surface of the substrate 1 by a CVD method using, for example, TEOS (Tetra Ethyl Ortho Silicate) gas. The insulating film 4A is deposited so as not to completely fill the adjacent portions of the stripe pattern formed by the dummy insulating film 11, the cap insulating film 3, and the auxiliary gate wiring AGL. Subsequently, the insulating film 4A is etched back to form sidewalls (sidewall insulating films) 4 on the side surfaces of the laminated pattern of the auxiliary gate wiring AGL, the cap insulating film 3 and the dummy insulating film 11, as shown in FIG. To do. At this time, the bottom gate insulating film 2a between adjacent stripe patterns formed by the dummy insulating film 11, the cap insulating film 3, and the auxiliary gate wiring AGL is also removed. As a result, the gate insulating film 2a remains only below the auxiliary gate wiring AGL and the sidewalls 4. Since this etching process is performed under the conditions for etching the silicon oxide film, the main surface of the substrate 1 in the space portion between the striped patterns formed extending in the first direction Y (see FIG. 2) is formed. An etching damage layer is formed. In order to remove the etching damage layer, the substrate 1 is further etched under conditions for etching silicon (etching damage removal process). As a result, the main surface of the substrate 1 in the space portion between the striped patterns formed extending in the first direction Y is approximately 10 nm lower than the main surface of the substrate 1 under the auxiliary gate wiring AGL. The etching damage layer may be removed by a method of removing the thermal oxide film by wet etching after the main surface of the substrate 1 is thermally oxidized. Thereafter, the substrate 1 is subjected to a thermal oxidation process such as an ISSG oxidation method to form an insulating film made of, for example, silicon oxide on the main surface of the substrate 1 as shown in FIG. By performing heat treatment (oxynitriding treatment) in a gas atmosphere containing nitrogen (N), nitrogen is segregated at the interface between the insulating film and the substrate 1 to form a gate insulating film 2b made of silicon oxynitride (SiON). Form. This gate insulating film 2b is a film functioning as a tunnel insulating film of the memory MIS • FETQm, and the thickness thereof is a silicon dioxide equivalent film thickness, for example, about 9 nm. The gate insulating film 2b may be formed by a CVD method.

  Next, as shown in FIG. 16, a floating gate electrode forming conductor film (second conductor layer) 12 made of, for example, low-resistance polysilicon is formed on the main surface of the substrate 1 (semiconductor wafer), and the dummy insulating film 11 is formed. Then, the film is deposited by CVD or the like so that the adjacent portion of the stripe pattern formed by the cap insulating film 3 and the auxiliary gate wiring AGL is completely filled. Subsequently, the conductor film 12 on the main surface of the substrate 1 is subjected to an etch-back process by an anisotropic dry etching method or a CMP (Chemical Mechanical Polishing) process, as shown in FIG. A conductive pattern (second conductive layer) 12a for forming a floating gate electrode is formed between adjacent stripe patterns formed by the insulating film 11, the cap insulating film 3, and the auxiliary gate wiring AGL. Subsequently, as shown in FIG. 18, the dummy insulating film 11 and the sidewalls 4 are etched by a dry etching method or a wet etching method. At this time, the etching selectivity between silicon oxide, silicon, and silicon nitride is increased so that silicon oxide is easier to remove than silicon and silicon nitride. Thereby, the cap insulating film 3 made of silicon nitride is caused to function as an etching stopper. Further, all of the dummy insulating film 11 made of silicon oxide is removed, but the upper portion of the side wall 4 made of silicon oxide is removed and left on the side surface of the auxiliary gate wiring AGL.

Next, as shown in FIG. 19, an interlayer insulating film (interlayer insulating film) 5 for electrically insulating the floating gate electrode and the control gate electrode is formed on the main surface of the substrate 1 (semiconductor wafer). As the insulating film 5 for the interlayer film, for example, a single film of silicon oxide film or a laminated film of silicon oxide film / silicon nitride film / silicon oxide film can be used. Subsequently, a conductor film (third conductor layer) 13 for forming a word line is deposited on the insulating film 5 in the main surface of the substrate 1 (semiconductor wafer). The conductor film 13 is formed by sequentially depositing, for example, a low resistance polysilicon film and a tungsten silicide film from the lower layer by the CVD method or the like. Thereafter, an insulating film 6 made of, for example, silicon oxide is deposited on the conductor film 13 in the main surface of the substrate 1 (semiconductor wafer) by, for example, a CVD method using a mixed gas of ozone (O ₃ ) gas and TEOS gas. To do. Thereafter, a cap film (masking layer) 15 made of, for example, polycrystalline silicon is deposited on the insulating film 6 in the main surface of the substrate 1 (semiconductor wafer) by a CVD method or the like. Further, a resist film 18 is applied on the cap film 15 in the main surface of the substrate 1 (semiconductor wafer) by a spin coating method or the like.

  Next, the resist film 18 is exposed and developed to form a resist pattern, and the resist film is used as an etching mask, and the cap film 15 exposed from the resist film 18 is selectively removed by dry etching or the like. Thereafter, the resist pattern is removed by an ashing method or the like. Thereby, as shown in FIG. 20, the cap pattern 15a is formed. A plurality of cap patterns (first masking patterns) 15a for forming word lines are formed in the memory cell region M1. The cap pattern 15a is a flat belt-like pattern extending in a direction perpendicular to the paper surface of FIG. A part of the surface of the insulating film 6 is exposed from between adjacent cap patterns 15a.

  Next, by using the cap pattern 15a as an etching mask, the insulating film 6 and the conductor film 13 exposed therefrom are removed by dry etching, thereby forming the word line WL made of the conductor film 13 as shown in FIG. . When the conductive film 13 is removed by etching, the cap pattern 15a is also removed. Subsequently, using the remaining pattern of the insulating film 6 as an etching mask, the insulating film 5 and the conductor pattern 12a exposed therefrom are removed by a dry etching method. Thereby, a plurality of floating gate electrodes FGE made of the conductor pattern 12a are formed in the memory region (the memory cell region M1 and the peripheral region of the memory cell). At this time, in this embodiment, the upper portion of the cap insulating film 3 exposed from between adjacent word lines WL is also etched. Thereby, the thickness of the cap insulating film 3 between the adjacent word lines WL is made thinner than the thickness of the cap insulating film 3 between the word lines WL and the auxiliary gate wiring AGL. In other words, in the present embodiment, without adding a series of lithography steps such as resist coating, exposure, and development for etching the cap insulating film 3 between the word lines WL, The cap insulating film 3 can be thinned. For this reason, the thinning of the cap insulating film 3 between the word lines WL does not increase the manufacturing process, the manufacturing time, and the manufacturing cost.

  In addition, after thinning the cap insulating film 3 between the word lines WL in this way, the cap insulating film 3 between the word lines WL may be selectively etched by, for example, a wet etching process using hot phosphoric acid or the like. Here, the cap insulating film 3 between the word lines WL may be etched to a thinner thickness or may be etched completely. If the cap insulating film 3 is removed from the beginning by the wet etching process, the cap insulating film 3 under the word line WL may also be removed by the side etching. Therefore, in the present embodiment, the cap insulating film 3 is non-selectively etched by dry etching to a position where damage or the like does not occur under the lower auxiliary gate wiring AGL, and then the remaining cap insulating film 3 is wet etched. To selectively etch. As a result, the cap insulating film 3 between the word lines WL can be further thinned or eliminated without causing large side etching and without damaging the underlying auxiliary gate wiring AGL.

  Next, the insulating film 7a is deposited on the main surface of the substrate 1 (semiconductor wafer) by a CVD method or the like. Thus, as shown in FIGS. 5 and 6, the insulating film 7a is buried between adjacent word lines WL, adjacent floating gate electrodes FGE, adjacent auxiliary gate lines AGL, and the like. Subsequently, after the insulating film 7b is deposited on the main surface of the substrate 1 (semiconductor wafer) by a CVD method or the like, the upper surface thereof is flattened by, for example, a CMP method or the like. Thereafter, although not shown in the drawing, a metal film is deposited on the main surface of the substrate 1 (semiconductor wafer) and then patterned to form wiring. In this way, a flash memory having memory cells MC was manufactured.

As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  In the above description, the case where the invention made mainly by the present inventor is applied to the method of manufacturing a flash memory which is the field of use that is the background of the invention has been described. The present invention can also be applied to a method for manufacturing a semiconductor device having a flash memory and a logic circuit such as a microprocessor on the same substrate.

  The present invention can be applied to the manufacturing industry of a semiconductor device having an auxiliary gate electrode type flash memory.

1 is a schematic circuit diagram of a main part of a memory cell region of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a plan view of a main part of a memory cell region in FIG. It is sectional drawing of the X1-X1 line | wire of FIG. It is sectional drawing of the X2-X2 line | wire of FIG. It is sectional drawing of the Y1-Y1 line | wire of FIG. It is sectional drawing of the Y2-Y2 line | wire of FIG. FIG. 5 is a circuit diagram of a main part of a memory cell region during a read operation. It is sectional drawing of the X1-X1 line | wire of FIG. 2 at the time of read-out operation | movement. FIG. 6 is a circuit diagram of a main part of a memory cell region during a write operation. It is sectional drawing of the X1-X1 line | wire of FIG. 2 at the time of write-in operation | movement. It is principal part sectional drawing of the memory area in the manufacturing process of the semiconductor device which is one embodiment of this invention. FIG. 12 is a fragmentary cross-sectional view of the memory region during the manufacturing process of the semiconductor device following that of FIG. 11; FIG. 13 is a fragmentary cross-sectional view of the memory region during the manufacturing process of the semiconductor device following that of FIG. 12; FIG. 14 is a fragmentary cross-sectional view of the memory region during the manufacturing process of the semiconductor device following that of FIG. 13; FIG. 15 is a fragmentary cross-sectional view of the memory region during the manufacturing process of the semiconductor device following that of FIG. 14; FIG. 16 is a fragmentary cross-sectional view of the memory region during the manufacturing process of the semiconductor device following that of FIG. 15; FIG. 17 is a fragmentary cross-sectional view of the memory region during the manufacturing process of the semiconductor device following that of FIG. 16; FIG. 18 is a fragmentary cross-sectional view of the memory region during the manufacturing process of the semiconductor device following that of FIG. 17; FIG. 19 is a fragmentary cross-sectional view of the memory region during the manufacturing process of the semiconductor device following that of FIG. 18; FIG. 20 is a fragmentary cross-sectional view of the memory region during the manufacturing process of the semiconductor device following that of FIG. 19; FIG. 21 is a fragmentary cross-sectional view of the memory region during the manufacturing process of the semiconductor device following that of FIG. 20; It is the principal part perspective view of the memory area of the flash memory which this inventor examined.

Explanation of symbols

1 Semiconductor substrate 2a Gate insulation film (first gate insulation film)
2b Gate insulating film (second gate insulating film)
3 Cap insulating film 4 Side wall (side wall insulating film)
4A Insulating film 5 Insulating film (interlayer insulating film)
6 Insulating film 7a, 7b Insulating film 8 Groove-type separation part 10 Conductor film (first conductor layer)
11 Dummy insulating film 12 Conductor film (second conductor layer)
12a Conductor pattern (second conductor layer)
13 Conductor film (third conductor layer)
15 Cap film 15a Cap pattern 18 Resist film 51 Cap insulating film M1 Memory cell region MC Non-volatile memory cell Qm Memory MIS • FET
AGL, AGLs, AGLd Auxiliary gate wiring (first gate electrode)
FGE floating gate electrode (second gate electrode)
CGE Control gate electrode (third gate electrode)
WL, WL0 Word line (third gate electrode)
BL Local data line SL Source line DL Drain line IL1 Inversion layer IR, Iw Current

Claims (7)

(A) a semiconductor substrate;
(B) a plurality of first gate electrodes formed on the main surface of the semiconductor substrate via a first gate insulating film and extending in a first direction along the main surface of the semiconductor substrate;
(C) a first insulating film mainly composed of silicon nitride formed on the first gate electrode;
(D) a sidewall insulating film formed on the sidewall of the first gate electrode;
(E) Between the adjacent first gate electrodes, the sidewall insulating film is formed in a state of being electrically insulated from the first gate electrode, and a second gate insulation is formed on the main surface of the semiconductor substrate. A second gate electrode formed through the film;
(F) an interlayer insulating film formed to cover the first insulating film and the second gate electrode;
(G) having a plurality of third gate electrodes formed on the interlayer insulating film so as to extend in a second direction intersecting the first direction;
The thickness of the first insulating film between adjacent ones of the plurality of third gate electrodes is such that the thickness of the first insulating film between each of the plurality of third gate electrodes and each of the plurality of first gate electrodes. A semiconductor device characterized by being thinner than a thickness.   2. The semiconductor device according to claim 1, wherein a height from the main surface of the semiconductor substrate to the upper surface of the second gate electrode is higher than a height from the main surface of the semiconductor substrate to the upper surface of the first gate electrode. A semiconductor device characterized by the above.   2. The semiconductor device according to claim 1, wherein a thickness of the first insulating film between adjacent ones of the plurality of third gate electrodes is set to be different from each of the plurality of third gate electrodes and each of the plurality of first gate electrodes. A semiconductor device, wherein the thickness is less than half of the thickness of the first insulating film. Manufacturing method of semiconductor device having the following steps:
(A) preparing a wafer;
(B) forming a first gate insulating film on the main surface of the semiconductor substrate of the wafer;
(C) depositing a first conductor layer which will later become a first gate electrode on the first gate insulating film;
(D) depositing a first insulating film mainly composed of silicon nitride on the first conductor layer;
(E) depositing a second insulating film on the first insulating film;
(F) By patterning the first conductor layer, the first insulating film, and the second insulating film, the plurality of first gate electrodes, the first insulating film, and the second extending in the first direction. Forming an insulating film pattern;
(G) forming a sidewall insulating film on a side surface of the pattern of the plurality of first gate electrodes, the first insulating film, and the second insulating film;
(H) After the step (g), removing the first gate insulating film portion exposed on the semiconductor substrate;
(I) forming a second gate insulating film on the main surface of the semiconductor substrate exposed after the step (h);
(J) The first gate electrode, the first insulating film, and the second insulating film are adjacent to each other on the second gate insulating film between the adjacent patterns and extend in the first direction. Forming a plurality of second conductor layers to be two gate electrodes;
(K) removing the second insulating film and the sidewall insulating film;
(L) depositing an interlayer insulating film so as to cover surfaces of the first insulating film and the plurality of second conductor layers;
(M) depositing a third conductor layer to be a third gate electrode later on the interlayer insulating film;
(N) The plurality of second gate electrodes separated in the first direction by patterning the third conductor layer, the interlayer insulating film, and the plurality of second conductor layers, and in the first direction Forming a plurality of said third gate electrodes extending in a second direction intersecting with each other;
And (o) etching a part of the first insulating film between adjacent ones of the plurality of third gate electrodes.   5. The method of manufacturing a semiconductor device according to claim 4, wherein in the step of patterning the third gate electrode, a part of the first insulating film between adjacent ones of the plurality of third gate electrodes is etched. A method for manufacturing a semiconductor device.   5. The method of manufacturing a semiconductor device according to claim 4, wherein a height from the main surface of the semiconductor substrate to the upper surface of the second gate electrode is higher than a height from the main surface of the semiconductor substrate to the upper surface of the first gate electrode. A method for manufacturing a semiconductor device, characterized by being high.   5. The method of manufacturing a semiconductor device according to claim 4, wherein a thickness of the first insulating film between adjacent ones of the plurality of third gate electrodes is set to each of the plurality of third gate electrodes and the plurality of first gate electrodes. A method of manufacturing a semiconductor device, wherein the thickness is less than half of the thickness of the first insulating film between each of the first and second insulating films.

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