CN109524407A - Memory and its manufacturing method - Google Patents
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- 239000000463 material Substances 0.000 claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 238000003475 lamination Methods 0.000 claims description 2
- 241000790917 Dioxys <bee> Species 0.000 claims 1
- 229910003978 SiClx Inorganic materials 0.000 claims 1
- 238000003860 storage Methods 0.000 abstract description 4
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- 238000000034 method Methods 0.000 description 33
- 229920002120 photoresistant polymer Polymers 0.000 description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 13
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 13
- 150000002500 ions Chemical class 0.000 description 11
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 6
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- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
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- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention discloses a kind of memory and its manufacturing methods, the manufacturing method of memory includes: providing a substrate, substrate includes external zones and device region, is formed with gate stack on device region, the first control gate film is formed on external zones and device region, the first control gate film covers gate stack；Etching stop layer is formed on the first control gate film；Etching stop layer in removal devices area；The second control gate film is formed on external zones and device region；Gate stack, the first and second control gate films in etched features area, to form dielectric layer and control gate between the floating grid being sequentially stacked on device region, grid；Removal is located at the second control gate film and etching stop layer on external zones；And the first control gate film of etching, to form selection grid on external zones, the height of selection grid is less than the height of control gate.The grid-control ability of selection grid can be improved in the present invention, and ensures the storage capacity and reliability of device.
Description
Technical field
The present invention relates to ic manufacturing technology field, in particular to a kind of memory and its manufacturing method.
Background technique
With the continuous improvement of electronic equipment performance requirement, (Multi-Time Programmable can be compiled repeatedly MTP
Journey) memory used as the memory device of each electronic equipment more and more widely.The executable repeatedly number of MTP memory
According to the movement such as deposit, reading and erasing, without constantly apply electric energy can storing data and storage data disconnected
It will not disappear after electricity, and can be achieved with the erasing of data by applying certain voltage.
The substrate of MTP memory is typically divided into the edge area (Periphery) and the area device (cell).The device region
It is formed with gate stack on (also referred to as cellular region), this gate stack includes tunnel oxide (tunnel OX), for storing
Dielectric layer and use between the floating grid of charge, silicon oxide/silicon nitride/silicon oxide (Oxide-Nitride-Oxide, ONO) grid
To control the control gate of data access.In the marginal zone, (also referred to as external zones) is formed with logic transistor, logic crystal
The grid of pipe is selection grid, and the selection grid is used for the unlatching of the switching device (such as metal-oxide-semiconductor) in logic control device area and closes
It closes.A gate oxide can be formed on area substrate surface generally before the marginal zone forms selection grid, later again in grid oxygen
Change and form selection grid on layer, gate oxide is earth silicon material.The performance of MOS transistor depends on the thickness of gate oxide.
The reduction of gate oxide thickness enhances the current driving ability of transistor, improves speed and power characteristic.Therefore in technique
Gate oxide thickness is reduced in reduction can effectively improve transistor performance, however thin oxide layer can aggravate electric current tunnel effect
It should and reduce oxide layer reliability.
The study found that the height of the selection grid on marginal zone directly affects the grid-control ability of its own, in gate oxidation thickness
Spend it is constant in the case where, selection grid height is higher, and the leakage current of logic transistor will increase, and device is more difficult to open, and influence device
The response efficiency of part.In order to solve this problem, it is common practice that directly reduce the polysilicon layer that selection grid is used to form on substrate
Deposition reduce the height of selection grid, and then promote the grid-control ability of the selection grid on marginal zone.Although this way work
Skill is relatively simple, and still, this can reduce the height of the control gate of device region accordingly, when carrying out ion implanting to device region,
Ion easily propagates through the too low control gate of height, damages dielectric layer and tunnel oxide between ONO grid, reduces the storage of device region
Ability and reliability.
Summary of the invention
The object of the present invention is to provide a kind of memory and its manufacturing methods, to promote the grid-control ability of device.
In order to achieve the goal above, the invention is realized by the following technical scheme:
A kind of manufacturing method of memory, comprising: provide a substrate, the substrate includes external zones and device region, described
Gate stack is formed on device region, the gate stack includes between the floating grid film being sequentially stacked on device region and grid
Dielectric film, is formed with the first control gate film on the external zones and device region, described in the first control gate film covering
Gate stack；Etching stop layer is formed on the first control gate film；Remove the etching stop layer on the device region；?
The second control gate film is formed on the external zones and device region；Etch gate stack, the first control gate on the device region
Film and the second control gate film, to form dielectric layer and control gate between the floating grid being sequentially stacked on device region, grid；It goes
Except the second control gate film and etching stop layer being located on the external zones；And first etched on the external zones is controlled
Grid film processed, to form selection grid on the external zones, the height of the selection grid is less than the height of control gate.
Optionally, the gate stack further includes the tunnelling oxygen between the device region surface and floating grid film
Change film.
Optionally, the material of the material of the first control gate film and the second control gate film is identical.
Optionally, the material of the material of the first control gate film and the second control gate film is DOPOS doped polycrystalline silicon.
Optionally, the material of the etching stop layer is silica.
Optionally, the step of removing the etching stop layer on the device region includes: the etch-stop on the external zones
The first mask layer is only formed on layer；Using first mask layer as exposure mask, etching removes the etching stop layer on the device region；
And removal first mask layer.
Optionally, floating grid is formed, dielectric layer and the step of control gate include: in the device region and external zones between grid
On the second control gate film on form the second mask layer；Using second mask layer as exposure mask, the device region is etched
On gate stack, the first control gate film and the second control gate film, to form dielectric layer and control between floating grid, grid
Grid；And removal second mask layer.
Optionally, removal be located at the external zones on the second control gate film and etching stop layer the step of include:
Third mask layer is formed on the device region；Using the third mask layer as exposure mask, etching removes second on the external zones
Control gate film and etching stop layer；And the removal third mask layer.
It optionally, include: to be formed on the device region and external zones the step of forming selection grid on the external zones
4th mask layer；Using the 4th mask layer as exposure mask, the first control gate film on the external zones is etched, described outer
It encloses and forms selection grid in area；And removal the 4th mask layer.
On the other hand, a kind of memory is formed using method as described above, and the memory includes: substrate, described
Substrate includes several memory cell areas, and each memory cell areas includes external zones and device region；Floating grid is located at the device region
On；Dielectric layer between grid is located on the floating grid；Control gate, between the grid on dielectric layer；Selection grid is located at described
On external zones；Wherein, the height of the selection grid is less than the height of the control gate.
The present invention is by stepped depositions the first control gate film and the second control gate film, i.e., thin in first control gate
Etching stop layer is formed on film；Remove the etching stop layer on the device region；Is formed on the external zones and device region
Two control gate films；Gate stack, the first control gate film and the second control gate film on the device region are etched, to be formed
It is sequentially stacked on the floating grid on device region, dielectric layer and control gate between grid；Removal is located at the second control on the external zones
Grid film and etching stop layer processed；And the first control gate film on the external zones is etched, with the shape on the external zones
At selection grid, the height of the finally formed selection grid be less than the height of control gate realize device region control gate height not
Under conditions of change, the purpose of external zones selection grid height is reduced.
By above-mentioned processing step, the height of the selection grid of external zones is reduced, reduces the consumption of the polysilicon of selection grid
It is most, and then the grid-control ability of the selection grid of external zones is promoted, increase the speed of response of device.Further, due to selection grid
Height be less than the height of control gate, when carrying out ion implanting to device region, ion does not pass through control gate, protection ONO and
Tunnel oxide will not improve the storage capacity and reliability of device region by the ion dam age.
Detailed description of the invention
Fig. 1 is the flow diagram of the manufacturing method of memory in the embodiment of the present invention；
Fig. 2 a~Fig. 2 h is the corresponding cross-section structure signal of each step in the manufacturing process of memory in the embodiment of the present invention
Figure.
Specific embodiment
A kind of memory of the invention and its manufacturing method are described in detail below in conjunction with attached drawing, wherein indicating
A preferably embodiment of the invention, it should be appreciated that those skilled in the art can modify invention described herein and still real
Existing advantageous effects of the invention.Therefore, following description should be understood as the widely known of those skilled in the art, and simultaneously
Not as limitation of the present invention.
In the following description, it is not described in detail well known function and structure, because they can make the present invention due to unnecessary
Details and it is chaotic.It will be understood that in the exploitation of any practical embodiments, it is necessary to make a large amount of implementation details to realize exploitation
The specific objective of person, such as according in relation to system or in relation to the limitation of business, another embodiment is changed by one embodiment.
Additionally, it should think that this development may be complicated and time-consuming, but to those skilled in the art only
It is only routine work.
It should be noted that attached drawing is all made of very simplified form and using non-accurate ratio, only to convenient, bright
The purpose of one embodiment of the invention is aided in illustrating clearly.
As shown in Figure 1, described method includes following steps the present embodiment provides a kind of manufacturing method of memory:
Step S1, a substrate is provided, the substrate includes external zones and device region, and it is folded that grid is formed on the device region
Layer, the gate stack includes dielectric film between the floating grid film being sequentially stacked on device region and grid, the external zones
Be formed with the first control gate film on device region, the first control gate film covers the gate stack.
Step S2, etching stop layer is formed on the first control gate film.
Step S3, the etching stop layer on the device region is removed.
Step S4, the second control gate film is formed on the external zones and device region.
Step S5, gate stack, the first control gate film and the second control gate film on the device region are etched, with shape
At the floating grid being sequentially stacked on device region, dielectric layer and control gate between grid.
Step S6, removal is located at the second control gate film and etching stop layer on the external zones.In the present embodiment,
The the second control gate film for being located at external zones can be removed by dry etch process.Position can be removed by wet-etching technology
In the etching stop layer of external zones.
Step S7, the first control gate film on the external zones, to form selection grid on the external zones, institute are etched
The height for stating selection grid is less than the height of control gate.
In the present embodiment, by manufacturing method stepped depositions the first control gate film of memory as described above and
Second control gate film, Lai Shixian reduce the height of external zones selection grid under conditions of device region control gate height is constant
Purpose, and then realize the purpose for promoting the grid-control ability of selection grid of external zones.
Referring specifically to Fig. 2 a~Fig. 2 h, each step in the manufacturing method of memory is shown in the embodiment of the present invention
Corresponding the schematic diagram of the section structure.
As shown in Figure 2 a, a substrate is provided, the material of the substrate can be silicon, germanium, SiGe or silicon carbide etc., can also be with
It is that silicon (SOI) perhaps germanium on insulator (geoi) (GOI) or can also be for other materials, such as GaAs etc. are covered on insulator
III, V compounds of group.In other embodiments, the substrate may include the various doping of the design requirement depending on memory
Region.It may include isolation structure (such as shallow trench isolation, STI) in the substrate each region is isolated and/or in the lining
The semiconductor devices formed on bottom.Substrate in the present embodiment is silicon substrate, further, be can be undoped or light
Spend the silicon substrate of p-type doping.
The substrate includes external zones (also referred to as marginal zone) 10 and device region (also referred to as cellular region) 20.Described
Gate stack 30 is formed on device region 20.The gate stack 30 is, for example, including being sequentially stacked on the device from the bottom to top
Dielectric film 33 between tunnel oxide film 31, floating grid film 32 and grid in area 20, tunnel oxide film 31, floating grid
Dielectric film 33 can modify additions and deletions according to actual device requirement and manufacture craft between film 32 and grid.
The tunnel oxide film 31 is used to form tunnel oxide, can use silica single layer structure, can also adopt
With oxide-nitride-oxide (ONO) structure.The forming method of the tunnel oxide film 31 includes low pressure chemical phase
Deposit (LPCVD), high density plasma chemical vapor deposition (HDPCVD), plasma enhanced chemical vapor deposition (PECVD),
The suitable technique such as thermal oxide.In the present embodiment, the tunnel oxide film 31 uses silica single layer structure, can be used
Thermal oxidation method is formed, and thickness is for example on the tens Izods right side.
Dielectric film 33 is used to form gate dielectric between the grid, the gate dielectric for be isolated floating grid with
Control gate.Dielectric film 33 can use oxide-nitride-oxide (ONO) structure between the grid.Dielectric is thin between the grid
The forming method of film 33 include low-pressure chemical vapor deposition (LPCVD), high density plasma chemical vapor deposition (HDPCVD), etc.
Gas ions enhance the suitable technique such as chemical vapor deposition (PECVD), thermal oxide.In the present embodiment, low pressure chemical can be first used
Gas-phase deposition forms one layer of silicon oxide layer on floating grid film 32, is then existed using low-pressure chemical vapor deposition process
One layer of silicon nitride layer is formed on silicon oxide layer, is then formed on silicon nitride layer using low-pressure chemical vapor deposition process again another
Layer silicon oxide layer, the overall thickness of dielectric film 33 is for example between tens angstroms to several hundred angstroms between the grid.
The first control gate film 40, the first control gate film 40 are formed on the external zones 10 and device region 20
Cover the gate stack 30.The forming method of the first control gate film 40 include low-pressure chemical vapor deposition (LPCVD),
The suitable technique such as high density plasma chemical vapor deposition (HDPCVD), plasma enhanced chemical vapor deposition (PECVD).
It generallys use Low Pressure Chemical Vapor Deposition technique and forms the first control gate film 40.Due on the device region 20
It is formed with gate stack 30, thus, after this step, the top surface of the first control gate film 40 on device region 20 is higher than external zones
The top surface of the first control gate film 40 on 10, to constitute a step in the intersection of device region 20 and external zones 10.At this
In embodiment, the thickness range of the first control gate film is
Then, as shown in Figure 2 b, etching stop layer 50 is formed on 40 surface of the first control gate film, that is, described
Etching stop layer 50 covers the first control gate film 40 on the external zones 10 and the first control gate film on device region 20
40.The forming method of the etching stop layer 50 includes low-pressure chemical vapor deposition (LPCVD), high-density plasma chemical gaseous phase
Deposit the suitable technique such as (HDPCVD), plasma enhanced chemical vapor deposition (PECVD).In the present embodiment, institute is formed
The material for stating etching stop layer 50 is preferably silica.
Then, the first mask layer (not shown) is formed on the etching stop layer 50 being located on external zones 10, it is described
First mask layer is, for example, patterned photoresist layer, and spin-coating method can be used and be coated with photoresist, and benefit on the etching stop layer 50
The photoresist is patterned with well known to a person skilled in the art the techniques such as exposure and imaging, to obtain described patterned
Photoresist layer.Then, using first mask layer as exposure mask, etching removal is located at the etching stopping in 20 region of device region
Layer 50, first mask layer can protect the etching stop layer 50 on external zones 10 to be not etched, so that on the external zones 10
Etching stop layer 50 be retained, (as shown in Figure 2 c).Then, the modes such as plasma ashing can be used and remove described first
Mask layer.
As shown in Figure 2 d, the second control gate film 41 is formed, the second control gate film 41 covers the external zones 10
On etching stop layer 50, and cover the first control gate film 40 on the device region 20.The second control gate film 41
Forming method include low-pressure chemical vapor deposition (LPCVD), high density plasma chemical vapor deposition (HDPCVD), plasma
Body enhances the suitable technique such as chemical vapor deposition (PECVD).Generally use Low Pressure Chemical Vapor Deposition technique formed it is described
Second control gate film 41.In the present embodiment, the thickness range of the second control gate film 41 is, for example,
Then, the second mask layer (not shown), the second mask layer example are formed on the second control gate film 41
Patterned photoresist layer in this way can be used spin-coating method and be coated with photoresist on the etching stop layer 50, and utilizes art technology
The techniques such as exposure and imaging well known to personnel are patterned the photoresist, to obtain the patterned photoresist layer.Then,
Using second mask layer as exposure mask, the second control gate film 41, the first control gate film 40 on the device region 20 are etched
With gate stack 30, floating grid 32 ' and the control gate 34 ' above the floating grid are formed on device region 20,
As shown in Figure 2 e.Then, the modes such as plasma ashing can be used and remove second mask layer.Specifically, it is carved using dry method
Etching technique, the second control gate film 41, the first control gate film 40 and the gate stack 30 being sequentially etched on the device region 20,
To form gate structure on the device region 20, the gate structure includes the tunnelling being sequentially stacked on above-mentioned device region 20
Oxide layer 31 ' (being obtained by etching tunnel oxide film 31), floating grid 32 ' (are obtained by etching floating grid film 32
To), dielectric layer 33 ' (being obtained by etching grid lamination 30) and control gate 34 ' (pass through the second control gate film 41 of etching between grid
It is obtained with the first control gate film 40).
Then, third mask layer (not shown) is formed on the device region 20, the third mask layer is, for example,
Patterned photoresist layer can be used spin-coating method and be coated with photoresist on the device region 20 and external zones 10, and utilizes this field skill
The techniques such as exposure and imaging well known to art personnel are patterned the photoresist, to obtain the patterned photoresist layer.It connects
, in conjunction with shown in 2f~2g, using the third mask layer as exposure mask, be located on external zones 10 second is removed by etching technics
Control gate film 41 and etching stop layer 50.It, can first using plasma dry etching work as a unrestricted example
Skill removes the second control gate film 41, is then removed etching stop layer 50 using wet-etching technology.Then, it can be used
The modes such as ion ashing remove the third mask layer.
Then, the 4th mask layer (not shown) is formed on the external zones 10 and device region 20, the described 4th covers
Film layer is, for example, patterned photoresist layer, and spin-coating method can be used and be coated with photoresist, and benefit on the device region 20 and external zones 10
The photoresist is patterned with well known to a person skilled in the art the techniques such as exposure and imaging, to obtain the 4th exposure mask
Layer.Then, using the 4th mask layer as exposure mask, the etching first control gate film 40 on external zones 10, thus
Selection grid 40 ' is formed on the external zones 10, as shown in fig. 2h.It is covered finally, the modes such as plasma ashing can be used and remove third
Film layer and the 4th mask layer.The height of thus obtained selection grid 40 ' is less than the height of the control gate 34 '.First control
The material of the material of grid film processed and the second control gate film is identical.In the present embodiment, the first control gate film is formed
40 and second the material of control gate film 41 be DOPOS doped polycrystalline silicon.
Another side according to the present invention also provides a kind of memory construction, which can use the above method
It is formed.In conjunction with shown in Fig. 2 a~Fig. 2 h, above-mentioned memory construction, comprising: substrate, the substrate include device region 20 and external zones
10；On the device region 20 and the tunnel oxide 31 ', the floating grid 32 ', dielectric layer 33 ' and control between grid that stack gradually
Grid 34 ' processed；The height of selection grid 40 ' on the external zones 10, the selection grid 40 ' is less than the control gate 34 '
Highly.The altitude range of the selection grid 40 ' is, for example,The altitude range example of the control gate 34 '
For example
Further, the memory construction further includes source-drain electrode (not shown), is located at 32 ' two sides of floating grid
In substrate.Form the tunnelling stacked gradually that the source-drain electrode is the selection grid 40 ' and device region on above-mentioned external zones 10
Dielectric layer 33 ' carries out source-drain electrode ion note to device region 20 with after control gate 34 ' between oxide layer 31 ', floating grid 32 ', grid
Enter processing step, and then forms the source-drain electrode.
The memory is, for example, floating gate type memory, e.g. flash memory (flash), Electrically Erasable Programmable Read-Only Memory
(EEPROM) etc..
In conclusion the present invention optimizes process sequence, in conjunction with certain etching work by considering from the angle of process integration
The selection grid and control gate is made in skill.It realizes under the premise of the height that guarantee is located at the control gate of device region is constant, passes through
The height of the selection grid of external zones is reduced, realizes and reduces exhausting for polysilicon, and then promote the grid-control energy of the selection grid of external zones
Power.Further, since the height of selection grid is less than the height of control gate, when carrying out source-drain electrode ion implanting to device region,
Ion does not pass through control gate, protects ONO and tunnel oxide will not be by the ion dam age.
Although the contents of the present invention are discussed in detail by the preferred embodiment, but it should be appreciated that described
Description is not considered as limitation of the present invention.After those skilled in the art have read the content, for of the invention
A variety of modifications and substitutions all will be apparent.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (10)
1. a kind of manufacturing method of memory characterized by comprising
A substrate is provided, the substrate includes external zones and device region, and gate stack, the grid are formed on the device region
Lamination includes dielectric film between the floating grid film being sequentially stacked on device region and grid, shape on the external zones and device region
At there is the first control gate film, the first control gate film covers the gate stack；
Etching stop layer is formed on the first control gate film；
Remove the etching stop layer on the device region；
The second control gate film is formed on the external zones and device region；
Gate stack, the first control gate film and the second control gate film on the device region are etched, is stacked gradually with being formed
Dielectric layer and control gate between floating grid, grid on device region；
Removal is located at the second control gate film and etching stop layer on the external zones；And
Etch the first control gate film on the external zones, to form selection grid on the external zones, the selection grid
Height is less than the height of control gate.
2. the manufacturing method of memory as described in claim 1, which is characterized in that the gate stack further includes positioned at described
Tunnel oxide film between device region surface and floating grid film.
3. the manufacturing method of memory as described in claim 1, which is characterized in that the material of the first control gate film and
The material of second control gate film is identical.
4. the manufacturing method of memory as claimed in claim 3, which is characterized in that the material of the first control gate film and
The material of second control gate film is DOPOS doped polycrystalline silicon.
5. the manufacturing method of memory as described in claim 1, which is characterized in that the material of the etching stop layer is dioxy
SiClx.
6. the manufacturing method of the memory as described in any one of claims 1 to 5, which is characterized in that remove the device region
On etching stop layer the step of include:
The first mask layer is formed on the etching stop layer on the external zones；
Using first mask layer as exposure mask, etching removes the etching stop layer on the device region；And removal described first
Mask layer.
7. the manufacturing method of the memory as described in any one of claims 1 to 5, which is characterized in that form floating grid, grid
Between dielectric layer and the step of control gate include:
The second mask layer is formed on the second control gate film on the device region and external zones；
Using second mask layer as exposure mask, gate stack, the first control gate film and the second control on the device region are etched
Grid film processed, to form dielectric layer and control gate between floating grid, grid；And removal second mask layer.
8. the manufacturing method of the memory as described in any one of claims 1 to 5, which is characterized in that removal is located at described outer
The step of enclosing the second control gate film and the etching stop layer in area include:
Third mask layer is formed on the device region；
Using the third mask layer as exposure mask, etching removes the second control gate film and etching stop layer on the external zones；
And
Remove the third mask layer.
9. the manufacturing method of the memory as described in any one of claims 1 to 5, which is characterized in that on the external zones
Formed selection grid the step of include:
The 4th mask layer is formed on the device region and external zones；
Using the 4th mask layer as exposure mask, the first control gate film on the external zones is etched, on the external zones
Form selection grid；And
Remove the 4th mask layer.
10. a kind of memory characterized by comprising
Substrate, the substrate include several memory cell areas, and each memory cell areas includes external zones and device region；
Floating grid is located on the device region；
Dielectric layer between grid is located on the floating grid；
Control gate, between the grid on dielectric layer；
Selection grid is located on the external zones；
Wherein, the height of the selection grid is less than the height of the control gate.
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| CN104752359A (en) * | 2013-12-30 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Memory device and forming method thereof |
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| CN104752359A (en) * | 2013-12-30 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Memory device and forming method thereof |
| US20150340375A1 (en) * | 2014-05-23 | 2015-11-26 | Semiconductor Manufacturing International (Shanghai) Corporation | Semiconductor device, related manufacturing method, and related electronic device |
| CN105575784A (en) * | 2014-10-09 | 2016-05-11 | 中芯国际集成电路制造(上海)有限公司 | Separate grid type flash memory manufacturing method and separate grid type flash memory |
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