JPH0661484A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0661484A JPH0661484A JP4107188A JP10718892A JPH0661484A JP H0661484 A JPH0661484 A JP H0661484A JP 4107188 A JP4107188 A JP 4107188A JP 10718892 A JP10718892 A JP 10718892A JP H0661484 A JPH0661484 A JP H0661484A
- Authority
- JP
- Japan
- Prior art keywords
- well
- oxide film
- semiconductor device
- leak current
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Element Separation (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体装置に関し、特に
耐放射線性を有するMOS型半導体装置のソース・ドレ
イン間のリーク電流の抑制を可能にするウェルの形状に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a well shape capable of suppressing a leak current between a source and a drain of a MOS type semiconductor device having radiation resistance.
【0002】[0002]
【従来の技術】特殊環境下、特に宇宙空間や原子力施設
内で用いられる半導体装置は通常のものに比べさまざま
な性能が要求される。例えば耐放射線性は重要な要素の
一つであり、人工衛星、ロケットなど宇宙用機器に利用
される半導体装置では特に重要である。2. Description of the Related Art Semiconductor devices used in special environments, especially in outer space and nuclear facilities, are required to have various performances as compared with ordinary semiconductor devices. For example, radiation resistance is one of the important factors, and is especially important in semiconductor devices used in space equipment such as artificial satellites and rockets.
【0003】従来の技術を説明する前に、放射線による
半導体装置の劣化メカニズムを簡単に説明する。図3は
半導体基板表面に形成された酸化膜13に、ガンマ線に
代表されるような放射線12が照射された場合の断面図
である。放射線の照射により酸化膜13中で電離が起こ
り、正電荷・負電荷からなる生成電荷14が形成され
る。両電荷の中、移動度の大きい負電荷(電子)はただ
ちに拡散および再結合し消滅する。しかし移動度の小さ
な正電荷は酸化膜13中に取り残されてしまう。この正
電荷は徐々に酸化膜13と基板との間にトラップされ固
定電荷となる。特にゲート電極8に正の電位が印加され
ていると、この現象が進行しやすい。この電荷により酸
化膜13下に反転層15が生じ寄生MOSトランジスタ
を形成する。しかもこの反転層15の形成は、フィール
ド酸化膜のような厚い酸化膜(700〜800nm程
度)の方が顕著であるため、この反転層を通るリーク電
流経路に沿って不要な電流がソース・ドレイン間に流れ
る。Before describing the conventional technique, a mechanism of deterioration of a semiconductor device due to radiation will be briefly described. FIG. 3 is a cross-sectional view when the oxide film 13 formed on the surface of the semiconductor substrate is irradiated with the radiation 12 represented by gamma rays. Ionization occurs in the oxide film 13 due to the irradiation of radiation, and a generated charge 14 composed of positive charges and negative charges is formed. Among the two charges, the negative charge (electron) having high mobility immediately diffuses and recombines and disappears. However, positive charges having low mobility are left in the oxide film 13. This positive charge is gradually trapped between the oxide film 13 and the substrate and becomes fixed charge. In particular, when a positive potential is applied to the gate electrode 8, this phenomenon easily progresses. This charge causes an inversion layer 15 to occur under the oxide film 13 to form a parasitic MOS transistor. Moreover, since the inversion layer 15 is formed more prominently in a thick oxide film (about 700 to 800 nm) such as a field oxide film, an unnecessary current is generated along the leak current path passing through the inversion layer. Flowing in between.
【0004】図4(a)〜(c)は、このソース・ドレ
イン間のリーク電流を防ぐための従来の半導体装置の平
面図、A−A線及びB−B線断面図であり、特に平面図
ではフィールド酸化膜5を除いてある。すなわち、N型
シリコン基板1にPウェル2を設け、このPウェル2内
にソース・ドレインのN+ 型拡散層9を設け、更にソー
ス・ドレイン拡散領域の両端のゲート酸化膜6の下に高
濃度のP+ 拡散層7を設け、フィールド酸化膜5下のリ
ーク電流経路の形成を抑えたものである。また一般に放
射線によってリーク電流が問題となるのは、捕獲される
生成電荷が正電荷であることからNチャネルトランジス
タが対象となり、上記の方策は通常Pチャネルトランジ
スタには適用されない。4A to 4C are a plan view, a sectional view taken along the line AA and the line BB of a conventional semiconductor device for preventing the leak current between the source and the drain, and particularly a plan view. In the figure, the field oxide film 5 is omitted. That is, the P well 2 is provided on the N type silicon substrate 1, the N + type diffusion layers 9 of the source / drain are provided in the P well 2, and a high level is formed under the gate oxide film 6 at both ends of the source / drain diffusion region. The P + diffusion layer 7 having a high concentration is provided to suppress the formation of the leak current path under the field oxide film 5. In general, the leakage current due to radiation is a problem because the generated charge to be trapped is a positive charge, and therefore the N-channel transistor is targeted, and the above measure is not usually applied to the P-channel transistor.
【0005】[0005]
【発明が解決しようとする課題】上述した耐放射線性を
有する半導体装置のソース・ドレイン間のリーク電流防
止用P+ 拡散層7は、リーク電流経路となるフィールド
酸化膜とソース・ドレインとなるN+ 拡散層9の間に間
隙なく存在していればその効果は十分ある。しかしなが
ら放射線照射量が10KGy以上になると、図5
(a),(b)に示すようなリーク電流経路16が無視
できなくなる。すなわち図5(a),(b)において点
線16で示されるリーク電流は、フィールド酸化膜5の
周辺に沿って流れるリーク電流であるが、このリーク電
流を抑えるべきP+ 拡散層7とフィールド酸化膜5の間
のわずかな間隙で放射線による反転が起こり、ソース・
ドレイン間リーク電流を生じる。このわずかな間隙は主
として拡散工程に起因するところが大きい。The P + diffusion layer 7 for preventing the leak current between the source and the drain of the above-described semiconductor device having radiation resistance has the field oxide film which serves as the leak current path and the N which serves as the source and drain. + If there is no space between the diffusion layers 9, the effect is sufficient. However, when the radiation dose is 10 KGy or more, as shown in FIG.
The leakage current path 16 as shown in (a) and (b) cannot be ignored. That is, the leakage current indicated by the dotted line 16 in FIGS. 5A and 5B is a leakage current flowing along the periphery of the field oxide film 5, but the P + diffusion layer 7 and the field oxidation which should suppress this leakage current. Radiation inversion occurs in the small gaps between the membranes 5,
Drain leakage current is generated. This slight gap is largely due to the diffusion process.
【0006】すなわち図6に示すように、ゲート酸化膜
6形成後にフォトレジスト膜10をマスクとして、選択
的に自己整合(セルフアライン)によりB+ (ボロン)
を注入し、フィールド酸化膜5とN+ 拡散層9との間に
P+ 拡散層7を形成しているが、酸化膜は、フィールド
酸化膜5の周辺の厚い酸化膜(700〜800nm)か
ら薄い数10nm程度のゲート酸化膜6に変化するた
め、フィールド酸化膜側の方ではB+ の不純物濃度が低
くなり、リーク電流抑制効果が低下する。That is, as shown in FIG. 6, after the gate oxide film 6 is formed, B + (boron) is selectively self-aligned by using the photoresist film 10 as a mask.
Is implanted to form the P + diffusion layer 7 between the field oxide film 5 and the N + diffusion layer 9. The oxide film is formed from a thick oxide film (700 to 800 nm) around the field oxide film 5. Since the gate oxide film 6 is changed to a thin film having a thickness of several tens of nm, the impurity concentration of B + becomes lower on the side of the field oxide film, and the leak current suppressing effect is reduced.
【0007】図7(a),(b)は別のP+ 拡散層7の
形成工程の例である。まず図7(a)に示すように、B
+ (ボロン)を注入しP+ 拡散層7を形成する。次に図
7(b)に示すように、全面の酸化膜を除去し、改めて
ゲート酸化膜も形成するわけである。しかしこの酸化膜
除去の際、フィールド酸化膜5の側面をエッチングされ
(等方性のため)、フィールド酸化膜5とP+ 拡散層7
の間に間隙(0.1〜0.5μm程度)が形成されるた
め、リーク電流の増大をまねく。またこの領域にはチャ
ネルストッパがほとんど存在していないため、その効果
もほとんど期待できない。FIGS. 7A and 7B show an example of another P + diffusion layer 7 forming process. First, as shown in FIG.
+ (Boron) is implanted to form the P + diffusion layer 7. Next, as shown in FIG. 7B, the oxide film on the entire surface is removed and a gate oxide film is formed again. However, when the oxide film is removed, the side surface of the field oxide film 5 is etched (because of the isotropicity), and the field oxide film 5 and the P + diffusion layer 7 are removed.
Since a gap (about 0.1 to 0.5 μm) is formed between the two, the leak current increases. Moreover, since there is almost no channel stopper in this region, its effect can hardly be expected.
【0008】[0008]
【課題を解決するための手段】本発明の半導体装置は、
N型半導体基板に形成されたPウェルと、このPウェル
上にゲート酸化膜を介して形成されたゲート電極と、こ
のゲート電極の両側の前記Pウェル内に形成されたソー
ス・ドレイン拡散層とを有する半導体装置において、少
くとも前記Pウェルの前記ゲート電極と交わる周辺部に
このPウェルと接する不純物濃度の高い第2のPウェル
を設けたものである。The semiconductor device of the present invention comprises:
A P-well formed on the N-type semiconductor substrate, a gate electrode formed on the P-well via a gate oxide film, and source / drain diffusion layers formed in the P-well on both sides of the gate electrode. In the semiconductor device having, the second P well having a high impurity concentration, which is in contact with the P well, is provided at least in the peripheral portion of the P well that intersects with the gate electrode.
【0009】すなわち従来からのPウェルの外周部もし
くはゲート電極に直交するPウェルの両辺側にこのPウ
ェルよりも不純物濃度の高い第2のPウェルを配し、し
かも第2のPウェルがフィールド酸化膜とゲート酸化膜
の接合部の下部に位置するような構造を有している。こ
れによりフィールド酸化膜端とPウェル間の間隙を流れ
る様なリーク電流を抑えることができる。That is, a second P well having a higher impurity concentration than the conventional P well is arranged on both sides of the P well or on both sides of the P well orthogonal to the gate electrode, and the second P well is a field. It has a structure located below the junction between the oxide film and the gate oxide film. As a result, it is possible to suppress a leak current that flows through the gap between the field oxide film edge and the P well.
【0010】[0010]
【実施例】次に本発明を図面を参照して説明する。図1
(a)〜(c)は本発明の第1の実施例の平面図、A−
A線及びB−B線断面図であり、特に平面図ではフィー
ルド酸化膜を除いて示している。The present invention will be described below with reference to the drawings. Figure 1
(A)-(c) is a top view of the 1st Example of this invention, A-
It is a cross-sectional view taken along the line A and the line B-B, and the field oxide film is not particularly shown in the plan view.
【0011】図1(a)〜(c)において半導体装置
は、N型シリコン基板1に形成されたPウェル2と、こ
の上にゲート酸化膜6を介して形成されたゲート電極8
と、このゲート電極8の両側のPウェル2内に設けられ
ソース・ドレインとなるN+ 拡散層9と、ゲート電極8
に直交してPウェル2内に設けられたリーク電流防止用
のP+ 拡散層7と、Pウェル2の外周部に設けられた第
2のPウェルとしてのP+ ウェル3とから主に構成され
ている。尚、4はチャネルストッパ,5はフィールド酸
化膜である。1A to 1C, the semiconductor device has a P well 2 formed on an N-type silicon substrate 1 and a gate electrode 8 formed on the P well 2 via a gate oxide film 6.
The N + diffusion layers 9 provided in the P well 2 on both sides of the gate electrode 8 and serving as the source and drain, and the gate electrode 8
Mainly composed of a P + diffusion layer 7 for preventing a leak current provided in the P well 2 orthogonal to the P well 2 and a P + well 3 as a second P well provided in the outer peripheral portion of the P well 2. Has been done. Incidentally, 4 is a channel stopper, and 5 is a field oxide film.
【0012】本第1の実施例の特徴は、従来のPウェル
2の外周部に不純物濃度の高いP+ウェル3を配したこ
とにある。従来の耐放射線性構造ではソース・ドレイン
間の内部リーク電流を抑えるためにP+ 拡散層7を設け
ていた。しかしながら前述の通りフィールド酸化膜5と
ゲート酸化膜6とのわずかな間隙を流れるリーク電流は
従来の方法では十分に抑えることができなかった。そこ
で本第1の実施例はこの間隙部分にP+ ウェル3を設
け、この不純物濃度をPウェル2よりも高くすることで
この部分の反転層形成の抑制を可能にした。The feature of the first embodiment resides in that the P + well 3 having a high impurity concentration is arranged on the outer peripheral portion of the conventional P well 2. In the conventional radiation resistant structure, the P + diffusion layer 7 is provided to suppress the internal leak current between the source and the drain. However, as described above, the leak current flowing through the slight gap between the field oxide film 5 and the gate oxide film 6 cannot be sufficiently suppressed by the conventional method. Therefore, in the first embodiment, the P + well 3 is provided in this gap portion and the impurity concentration is made higher than that of the P well 2, so that the formation of the inversion layer in this portion can be suppressed.
【0013】本第1の実施例の2重ウェルの深さは従来
のものと同じく5〜8μm程度であり、P+ ウェル3の
不純物濃度は表面濃度が通常のものと比較して1桁程度
(1016〜1017cm-3)高く設定する。但し濃度を高
くしすぎるとソース・ドレイン間の耐圧が低下してしま
うので必要とする素子特性に合わせて設定する。また、
P+ ウェル3の幅は設計にもよるが、前述の間隙の幅は
1μm以下と考えられるので数μm程度に設定する。但
しPウェル2及びP+ ウェル3形成時に熱処理による拡
散により実際には深さの0.7〜0.8倍程度の広がり
がプラスされる。The depth of the double well of the first embodiment is about 5 to 8 .mu.m as in the conventional one, and the impurity concentration of the P.sup. + Well 3 is about one digit as compared with the normal one. (10 16 to 10 17 cm −3 ) Set higher. However, if the concentration is too high, the withstand voltage between the source and the drain will be lowered, so it is set according to the required element characteristics. Also,
The width of the P + well 3 depends on the design, but since the width of the above-mentioned gap is considered to be 1 μm or less, it is set to about several μm. However, when the P well 2 and the P + well 3 are formed, a spread of about 0.7 to 0.8 times the depth is actually added due to diffusion by heat treatment.
【0014】図2は本発明の第2の実施例の平面図であ
る。2重ウェルの構造は第1の実施例と同じであるが、
この第2の実施例ではゲート電極8と直交する部分のみ
にP+ ウェル3Aを設けたものである。第1の実施例で
はP+ ウェル3を形成するために新規にマスクを作成す
る必要があるが、この第2の実施例ではPウェルの横方
向広がりを考慮すると、図1(a)に示したソース・ド
レイン間のリーク電流防止用P+ 拡散層7用のマスクを
代用することができ、拡散工程の追加のみで対応できる
利点がある。FIG. 2 is a plan view of the second embodiment of the present invention. The structure of the double well is the same as that of the first embodiment,
In the second embodiment, the P + well 3A is provided only in the portion orthogonal to the gate electrode 8. In the first embodiment, it is necessary to newly create a mask for forming the P + well 3, but in the second embodiment, considering the lateral spread of the P well, it is shown in FIG. Further, the mask for the P + diffusion layer 7 for preventing the leak current between the source and the drain can be used as a substitute, and there is an advantage that it can be dealt with only by adding a diffusion step.
【0015】[0015]
【発明の効果】以上説明したように本発明は、耐放射線
性構造を有する半導体装置において、通常のPウェルの
外周部もしくはゲート電極に直交する側にPウェルより
も不純物濃度が高い、第2のPウェルを設けることによ
り、フィールド酸化膜とゲート酸化膜との間隙を流れる
リーク電流を抑制することができるため、半導体装置の
耐放射線性を向上させることができるという効果があ
る。As described above, according to the present invention, in the semiconductor device having the radiation resistant structure, the impurity concentration is higher than that of the P well on the outer peripheral portion of the normal P well or on the side orthogonal to the gate electrode. By providing the P well, it is possible to suppress the leak current flowing through the gap between the field oxide film and the gate oxide film, and thus it is possible to improve the radiation resistance of the semiconductor device.
【図1】本発明の第1の実施例の平面図及び断面図。FIG. 1 is a plan view and a sectional view of a first embodiment of the present invention.
【図2】本発明の第2の実施例の平面図。FIG. 2 is a plan view of the second embodiment of the present invention.
【図3】放射線による半導体装置の劣化のメカニズムを
説明するための断面図。FIG. 3 is a cross-sectional view for explaining a mechanism of deterioration of a semiconductor device due to radiation.
【図4】従来の半導体装置の一例の平面図及び断面図。FIG. 4 is a plan view and a cross-sectional view of an example of a conventional semiconductor device.
【図5】従来の半導体装置におけるリーク電流経路を説
明するための平面図及び断面図。5A and 5B are a plan view and a cross-sectional view for explaining a leak current path in a conventional semiconductor device.
【図6】従来の半導体装置におけるリーク電流経路を説
明するための断面図。FIG. 6 is a cross-sectional view for explaining a leak current path in a conventional semiconductor device.
【図7】従来の半導体装置におけるリーク電流経路を説
明するための断面図。FIG. 7 is a cross-sectional view for explaining a leak current path in a conventional semiconductor device.
1 N型シリコン基板 2,2A Pウェル 3,3A P+ ウェル 4 チャネルストッパ 5 フィールド酸化膜 6 ゲート酸化膜 7 P+ 拡散層 8 ゲート電極 9 N+ 拡散層 10 フォトレジスト膜 12 放射線 13 酸化膜 14 生成電荷 15 反転層1 N-type silicon substrate 2, 2A P well 3, 3A P + well 4 Channel stopper 5 Field oxide film 6 Gate oxide film 7 P + Diffusion layer 8 Gate electrode 9 N + Diffusion layer 10 Photoresist film 12 Radiation 13 Oxide film 14 Generated charge 15 Inversion layer
Claims (2)
と、このPウェル上にゲート酸化膜を介して形成された
ゲート電極と、このゲート電極の両側の前記Pウェル内
に形成されたソース・ドレイン拡散層とを有する半導体
装置において、少くとも前記Pウェルの前記ゲート電極
と交わる周辺部にこのPウェルと接する不純物濃度の高
い第2のPウェルを設けたことを特徴とする半導体装
置。1. A P well formed on an N-type semiconductor substrate, a gate electrode formed on the P well via a gate oxide film, and a source formed in the P well on both sides of the gate electrode. A semiconductor device having a drain diffusion layer, wherein a second P well having a high impurity concentration in contact with the P well is provided at least in a peripheral portion of the P well that intersects with the gate electrode.
ルド酸化膜との接合部の下部に設けられている請求項1
記載の半導体装置。2. The second P well is provided below a junction between a gate oxide film and a field oxide film.
The semiconductor device described.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4107188A JPH0661484A (en) | 1992-04-27 | 1992-04-27 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4107188A JPH0661484A (en) | 1992-04-27 | 1992-04-27 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0661484A true JPH0661484A (en) | 1994-03-04 |
Family
ID=14452705
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4107188A Pending JPH0661484A (en) | 1992-04-27 | 1992-04-27 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0661484A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5610428A (en) * | 1994-06-10 | 1997-03-11 | Seiko Instruments Inc. | Semiconductor integrated circuit |
JP2011134784A (en) * | 2009-12-22 | 2011-07-07 | Brookman Technology Inc | Insulated gate semiconductor device and insulated gate semiconductor integrated circuit |
-
1992
- 1992-04-27 JP JP4107188A patent/JPH0661484A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5610428A (en) * | 1994-06-10 | 1997-03-11 | Seiko Instruments Inc. | Semiconductor integrated circuit |
JP2011134784A (en) * | 2009-12-22 | 2011-07-07 | Brookman Technology Inc | Insulated gate semiconductor device and insulated gate semiconductor integrated circuit |
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