JP2848478B2 - MIS type semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MIS type semiconductor device and, more particularly, to an MIS type semiconductor device having an LDD structure with improved radiation resistance.

[0002]

2. Description of the Related Art In a MIS type semiconductor device, element isolation is usually performed by a thick element isolation oxide film. When such a semiconductor device is irradiated with ionizing radiation such as γ-rays, a large amount of electron-hole pairs are generated in the element isolation oxide film (field oxide film) and the gate oxide film, and holes having low mobility are generated. It is trapped by the hole traps in the oxide film and is accumulated as positive fixed charges. Further, some of the holes cut off the bond at the silicon-oxide film interface to generate an interface state. As a result, a change occurs in the transistor characteristics.

FIG. 3 is a graph showing the change (deterioration) of the subthreshold characteristic of a MIS transistor due to γ-ray irradiation. In FIG.
The characteristics of the channel region and the parasitic MOS region before the irradiation of the line are shown, and “and” indicate the characteristics of the region after the irradiation of the γ-ray, respectively.

[0004] Although the subthreshold current in each region increases due to the γ-ray irradiation, the leakage current in the parasitic MOS path increases particularly remarkably. This is because the amount of electron-hole pairs generated by radiation is proportional to the volume (that is, thickness) of the oxide film. In an element isolation oxide film having a thickness of 10 times or more as compared with a gate oxide film, In addition, both the amount of positive charges accumulated in the oxide film and the amount of generation of the interface state are increased, and the characteristic deterioration is remarkable. In fact, 10 ⁵ ra
The threshold voltage of a parasitic MOS having an oxide film with a thickness of about 6000 ° decreases by several tens of volts and the leak level increases by several digits due to the irradiation of d (SI) with γ rays.

To cope with this point, the present inventor has already proposed a MIS transistor having a structure with high radiation resistance as shown in FIG. 4 (Japanese Patent Laid-Open No. 61-164265). FIG. 4A is a plan view of the MIS transistor proposed in the above publication, and FIGS. 4B and 4C are cross-sectional views taken along lines AA ′ and BB ′, respectively. FIG.

In FIG. 4, reference numeral 401 denotes a p-type silicon substrate; 402, a field oxide film selectively provided on the p-type silicon substrate; 403, an active region separated from other regions by the field oxide film 402; The formed gate oxide film, 404 is a gate electrode made of polysilicon, 407 is a high concentration n-type diffusion layer forming source / drain regions formed so as to match the gate electrode 404, and 408 is BPSG (Borophosphosilicate glass).
The film 409 is a high-concentration p-type region which is provided between the source / drain region (407) in the gate width direction and the field oxide film 402 and is doped at a higher concentration than the channel doping proposed by the above-mentioned invention. It is.

In the transistor configured as described above, as is apparent from the cross-sectional view of FIG. 4C, the height between the source / drain region (407) and the field oxide film 402 increases in order from the bottom. A stacked body of the concentration p-type region 409, the gate oxide film 403, and the BPSG film 408 exists. Thus, unlike a thermal oxide film such as a field oxide film, a BPSG film has a large number of recombination centers, electrons, and hole traps in the film, and an electron-hole pair in the film. Is generated, they are almost caught by them, so that it is difficult for the entire film to accumulate charges. For this reason, characteristic fluctuations that occur as a result of charge accumulation are less likely to occur.

In fact, for example, in a parasitic MOS transistor using a thin thermal oxide film (400 ° or less) + BPSG film (up to 6000 °) as a gate oxide film, 10 ⁵ rad (SI)
Of the threshold voltage due to γ-ray irradiation is about several volts, which is only about one tenth of that of a thick thermal oxide film.
That is, the MIS transistor having the structure shown in FIG. 4 exhibits high radiation resistance.

On the other hand, in recent years, miniaturization of MIS transistors has been advanced, and the generation of hot carriers due to an increase in the drain electric field strength has become remarkable.
d Drain) structure has become common. Therefore, it is necessary to take countermeasures against radiation for the transistor having the LDD structure. In this case, if the above-described invention is applied to the transistor having the LDD structure as it is, the structure shown in FIG. 5 is obtained. 5A is a plan view, and FIGS. 5B and 5C are cross-sectional views taken along lines AA ′ and BB ′, respectively.

In FIG. 5, the same parts as those in FIG. 4 are denoted by the same reference numerals in the last two digits, and thus duplicate description is omitted. In the transistor of FIG. 5, the side wall of the gate electrode 504 is provided. A sidewall oxide film 506 is formed in the active region, and a low-concentration n-type diffusion layer 505 matched to the gate electrode 504 and a high-concentration n-type diffusion layer 507 matched to the sidewall oxide film 506 are formed in the active region. Are formed.

[0011]

When the invention of the above-mentioned publication is applied to a transistor having an LDD structure as it is, FIG.
As shown in (c) of FIG.
05, 507) and the field oxide film 502,
In order from the bottom, the high concentration p-type region 509 and the gate oxide film 50
3. A structure in which a stacked body of the sidewall oxide film 506 and the BPSG film 508 exists. Here, the thickness of the side wall oxide film is about 4000 °, and the electron-hole pairs generated there by γ-ray irradiation form a large amount of accumulated charges and interface states similarly to the thermal oxide film. The sidewall oxide film forms a leak current path from the source to the drain via the field oxide film. Therefore, the LDD structure has a problem that the off-leak current at the time of radiation exposure cannot be suppressed.

[0012]

According to the present invention, there is provided an LDD structure having an M
In the IS type transistor, the side wall insulating film of the gate electrode is removed near the element isolation insulating film, and
The drain region is formed at least in the vicinity of the portion of the gate electrode from which the sidewall insulating film has been removed, separated from the element isolation insulating film.

[0013]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1A is a plan view of an n-channel MIS transistor according to the first embodiment of the present invention.
(B) and (c) are respectively AA ′ in FIG. 1 (a).
It is sectional drawing of the line and the BB 'line. As shown in FIG. 1, a field oxide film 102 for element isolation is formed on a p-type silicon substrate 101, and a gate oxide film 1 is formed on an active region surrounded by the field oxide film 102.
03 is formed thereon, and a gate electrode 104 made of polysilicon is formed thereon.

The side wall oxide film 1 is formed on the side wall of the gate electrode 104.
Although 06 is formed, the sidewall oxide film is removed from the field oxide film and its vicinity, unlike the example of FIG. In the surface region of the p-type silicon substrate 101, a low-concentration n formed in alignment with the gate electrode 104 is formed.
Type diffusion layer 105 and high-concentration n-type diffusion layer 107 formed so as to be aligned with sidewall oxide film 106.
These diffusion layers are formed apart from field oxide film 102 in the gate width direction. The whole including the transistor is covered with the BPSG film 108.

In the MIS transistor thus configured, the film structure between the source / drain regions (105, 107) and the field oxide film 102 is as shown in FIG.
As shown in FIG. 3, a p-type silicon substrate 101, a gate oxide film 103, and a BPSG film 108 are formed in this order from the bottom. As described above, the BPSG film has a large amount of electrons generated during γ-ray irradiation.
It absorbs hole pairs and does not contribute much to the accumulation of fixed charges or the generation of interface states.

In the gate oxide film, the accumulation of fixed charges and the generation of interface states pose a problem. However, the gate oxide film is usually thinner than 300.degree.
The amount of generation of electron-hole pairs is small, and electric charges such that an inversion layer is formed on the substrate surface are not accumulated. Therefore, in the transistor of the present embodiment, even when the γ-ray is irradiated, the leakage due to the parasitic MOS between the source and the drain remains at a low level. It is sufficient that the separation distance L between the source / drain region and the field oxide film is about the gate length.

FIG. 2A is a plan view of an n-channel MIS transistor according to a second embodiment of the present invention.
2 (b) and 2 (c) respectively show A-
It is sectional drawing of the A 'line and the BB' line. In FIG. 2, the same parts as those in FIG. 1 are denoted by the same reference numerals having the same last two digits, and thus duplicate description is omitted. In the present embodiment, the source / drain regions (205, 207) are used. In the isolation region between the gate electrode and the field oxide film 202, the high-concentration p-type region 20 doped with a higher impurity concentration than the channel region is formed.
9 are provided.

In this embodiment, the provision of the high-concentration p-type region 209 makes it possible to more completely prevent the inversion of the substrate surface caused by charges accumulated in the gate oxide film on this region. Actually, the decrease in the threshold voltage of the parasitic MOS in the isolation region is reduced by 1 as in the case of FIG.
0 ⁵ rad (SI) was able to be suppressed to several volts, which is a fraction of the conventional example or less.

While the preferred embodiment has been described above,
The present invention is not limited to these embodiments, and various modifications are possible. For example, a region where the source / drain region is not formed in the active region (ie, an isolation region)
Can be kept only in the vicinity under the gate electrode. Conversely, an isolation region is provided all around the active region,
The drain region may be completely separated from the field oxide film.

[0020]

As described above, according to the present invention, the LDD
In a MIS transistor having a structure, a sidewall oxide film near an element isolation oxide film is removed, and a region (isolation region) where a source / drain region is not formed is provided at least near a portion where a sidewall insulating film of a gate electrode is removed. Therefore, according to the present invention, it is possible to reduce the electric field intensity near the drain and to suppress the generation of accumulated charges and interface states between the source and drain regions during radiation exposure. it can. Thus, according to the present invention,
A semiconductor device having high hot carrier resistance and excellent radiation resistance even when miniaturized can be provided.

[Brief description of the drawings]

FIG. 1 is a plan view and a sectional view showing a first embodiment of the present invention.

FIG. 2 is a plan view and a sectional view showing a second embodiment of the present invention.

FIG. 3 is a graph showing changes in transistor characteristics due to radiation exposure.

FIG. 4 is a plan view and a cross-sectional view of a conventional radiation-resistant transistor.

FIGS. 5A and 5B are a plan view and a cross-sectional view when a conventional radiation-resistant transistor structure is formed into an LDD structure. FIGS.

[Explanation of symbols]

 101, 201, 401, 501 P-type silicon substrate 102, 202, 402, 502 Field oxide film 103, 203, 403, 503 Gate oxide film 104, 204, 404, 504 Gate electrode 105, 205, 505 Low concentration n-type diffusion Layers 106, 206, 506 Side wall oxide films 107, 207, 407, 507 High concentration n-type diffusion layers 108, 208, 408, 508 BPSG films 209, 409, 509 High concentration p-type regions

Claims (1)

(57) [Claims] An active region is provided on a semiconductor substrate of a first conductivity type surrounded by an element isolation insulating film, and a gate electrode is provided on the active region with a gate insulating film interposed therebetween to cross the active region. A side wall insulating film is provided on a side wall of the gate electrode, and a first source / drain region aligned with the gate electrode and a second source region aligned with the side wall insulating film are provided in a surface region of the semiconductor substrate. In a MIS type semiconductor device provided with a source / drain region, the sidewall insulating film is removed in the vicinity of the element isolation insulating film, and the first and second source / drain regions have at least An MIS type semiconductor device, wherein the gate electrode is formed near the part where the side wall insulating film is removed and is separated from the element isolation insulating film.