JPH06132488A - Mos transistor, integrated circuit employing same, and fabrication of mos transistor - Google Patents

Abstract

PURPOSE:To provide a MOSFET having high electrostatic breakdown strength at an I/O part having no adverse effect on the internal element part of integrated circuit. CONSTITUTION:An MOSFET 30 is employed at an I/O part 23 of an IC 20. In the MOSFET 30, gate oxide 35c is deposited thick in a predetermined region below the end part on the drain region 34 of a gate 36 as compared with gate oxide 35 in other region. Predetermined region at the end part on the source region 33 side of the drain region 34 is completely covered with the thick gate oxide 35c.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS transistor, an integrated circuit using the same, and a method for manufacturing a MOS transistor.

[0002]

2. Description of the Related Art An integrated circuit (hereinafter referred to as "IC: in
MOS field effect transistor (hereinafter referred to as “MOSFET: metal oxid”) used in an “integrated circuit”.
e semiconductor field effect transistor ")
The basic cross-sectional structure of is shown. As shown in FIG. 11, the MOSFET has a channel region 2 in the surface layer portion of the P-type silicon substrate 1.
An N-type source region 3 and an N-type drain region 4 are formed on both sides of. Then, the gate 6 is formed on the channel region 2 of the silicon substrate 1 with the source region 3 and the drain region 4 being bridged through the gate oxide film 5.

With the recent development of the semiconductor industry, there is a demand for higher integration of devices, and in order to cope with this, MOSF has been developed.
ET is being miniaturized. That is, MOSFET
The miniaturization of the device corresponds to high integration of the device by scaling down the size of each part of the MOSFET in accordance with the scaling rule proposed by Dennard et al. The basic idea of scaling is that, when the lateral dimension of the MOSFET, that is, the length and width of the channel region 2 is 1 / α (α: scaling coefficient), the vertical dimension of the MOSFET, that is, the gate oxide film 5 And the junction depth of the source region 3 and the drain region 4 are also proportional to 1 / α. At the same time, by setting all the voltages to 1 / α, the MOS
The potential distribution of each part of the FET is kept constant.

According to the scaling rules above, all voltages must be scaled down to 1 / α. However, in practice, this basic principle was not observed, and the power supply voltage of the miniaturized MOSFET was used as it was at the power supply voltage before scaling. When the length of the channel region 2 (channel length) is made shorter and shorter with the drain voltage kept constant, the electric field in the channel naturally becomes large due to the scaling coefficient. This is MOSF
It causes a major problem when operating in the saturation region of ET, namely the short channel effect. This is because, in the pinch-off state, the drain voltage, to be exact, V _D −V _Dsat is applied almost as it is to the depletion layer between the pinch-off point and the drain region 4, and a very large electric field peak appears in the vicinity of the drain region 4. . In general, electrons that are accelerated by a large electric field and have energy higher than thermal energy are called hot electrons, and many hot electrons are generated near the drain region, which causes a problem.

First, impact ionization (impac)
T ionization) is a phenomenon in which hot electrons hit the silicon crystal of the silicon substrate 1 and break the bond, so that electron-hole pairs are generated and an extra current flows. This current is a current generated as a result of electrons being drawn into the drain region 4 and holes flowing into the substrate 1, and flows between the drain region 4 and the substrate 1. When this current increases, as shown in FIG. 12, a voltage effect due to the resistance of the substrate 1 (the effective resistance is expressed as “R _S ”) occurs, and the potential of the substrate 1 near the source region 3 rises. . Especially when the substrate 1 is grounded, IR _sub > φ
_{At BI} (diffusion potential), the source region 3 becomes a forward bias, and a large amount of electrons are injected into the substrate 1. this is,
This is a kind of positive feedback phenomenon, and eventually the source region 3 and the drain region 4 become conductive, and a large amount of uncontrollable current may flow, resulting in destruction of the element.

Even if the current does not increase so far, light is generated by impact ionization in the drain region 4, which produces electron-hole pairs at the PN junction of the nearby device, causing an extra current. Also causes the problem. The most troublesome thing about hot electrons is that electrons with high energy are silicon substrate 1-gate oxide film 5.
This is a phenomenon of getting over the barrier at the interface and entering the gate oxide film 5. This shifts the threshold value in the positive direction because a part of the hot electrons is trapped in the gate oxide film 5 and becomes a negative fixed charge. in this way,
If the threshold value shifts in the positive direction, it becomes difficult for current to flow while the circuit is operating, and the characteristics of the MOSFET change, which reduces the reliability of the IC. This is generally called the hot electron effect.

Since the problems of the short channel effect, more specifically the hot electron effect, are all caused by the high electric field in the vicinity of the drain region 4, various devices for alleviating this electric field have been conventionally proposed. A typical example thereof is a MOSFET having an LDD (lightly doped drain) structure (hereinafter referred to as “LDD MOSFET”).

FIG. 13 shows a schematic sectional structure of an LDD MOSFET. In the LDDMOSFET, as shown in FIG. 13, the drain region 4 has an N-type diffusion layer 4a and an N-type diffusion layer 4a so as to make the impurity distribution of the drain region 4 as smooth as possible.
The N ⁻ type LDD diffusion layer 4 provided at the end of the type diffusion layer 4a on the source region 3 side and having a lower impurity concentration than the N type diffusion layer 4a.
and b. The source region 3 is also a N-type diffusion layer 3a, provided at four side end drain region of the N-type diffusion layer 3a, impurity concentration than the N-type diffusion layer 3a lower N ^-
The mold diffusion layer 3b.

A method of manufacturing the above LDDMOSFET will be briefly described with reference to FIG. First, after forming the field oxide film 7 and the gate oxide film 5 on the P-type silicon substrate 1, the gate 6 is formed on the gate oxide film 5. Next, P ⁺ is injected and diffused at a low concentration using the gate 6 as a mask to form the N ⁻ type diffusion layer 3b and the N ⁻ type LDD diffusion layer 4b with the channel region 2 interposed therebetween. Then, a pair of side spacers 8 and 9 are formed on both sides of the gate 6, respectively, and As ⁺ and P ⁺ are injected and diffused at a high concentration using the gate 6 and the pair of side spacers 8 and 9 as masks to form an N ⁻ type diffusion layer N-type diffusion layers 3a and 4a are formed outside the end of 3b and the N ⁻ type LDD diffusion layer 4b on the side of the gate 6 with the channel region 2 interposed therebetween.

[0010]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
Since the N ⁻ type LDD diffusion layer 4b relaxes the high electric field in the vicinity of the drain region 4, the electric field of the depletion layer formed in T does not become high. Therefore, the avalanche phenomenon is less likely to occur, and high-energy hot electrons are less likely to occur. Therefore, the hot electron effect can be prevented.

However, in the LDD MOSFET, the gate oxide film 5 is thin due to the above scale down. Therefore, as shown in FIG. 14, the relationship between the drain-substrate breakdown voltage and the gate breakdown voltage is such that as the voltage is increased, the drain-substrate breakdown voltage X> the gate breakdown voltage Y, and the current flows to the gate 6 side rather than the substrate 1 side. It becomes easy to flow. That is, the electrostatic breakdown voltage is low.

Due to the manufacturing process of the IC, this LDDMOSFET is used not only in the internal element section of the IC but also in the input / output section (hereinafter referred to as "I / O (input / output) section"). It is normal. That is, in the I / O part, as shown in FIG. 15, the drain of the LDDMOSFET 10 is directly connected to the input / output pad 11, and when a surge voltage is applied to the input / output pad 11, the drain-
Since the substrate breakdown voltage> the gate breakdown voltage, the surge current is generated by the N-type diffusion layer 4 as shown by the arrow in FIG.
It flows through the a, N ⁻ type LDD diffusion layer 4 b and the gate oxide film 5 to the gate 6. Therefore, the gate oxide film 5 below the drain region 4 side of the gate 6 (see A in FIG.
(See) may be destroyed. Further, even before the destruction of the gate oxide film 5 shown by A in FIG. 13 is reached, the gate oxide film 5 is charged with electric charges and a soft leak occurs.
Therefore, the internal element portion may be adversely affected and the reliability of the IC may be reduced.

In view of the above, the present invention provides a MOS transistor capable of increasing electrostatic breakdown voltage even if the gate insulating film is thinned by miniaturization, an integrated circuit using the same, and a method for manufacturing a MOS transistor. To aim.

[0014]

Means and Action for Solving the Problems A MOS transistor according to claim 1 for achieving the above object,
In an integrated circuit in which an LDDMOS transistor is used for an internal element section, the LDDMOS transistor is used for an input / output section for inputting / outputting to / from the internal element section, and includes a channel region and a source region and a drain with the channel region sandwiched therebetween. A semiconductor substrate in which a region is formed, and a gate formed on a channel region of the semiconductor substrate with a gate insulating film in a state of bridging the source region and the drain region,
The length of the channel region is set longer than the channel length of the LDDMOSFET, and the gate insulating film in a predetermined region at least below the drain region side end portion of the gate is at the source region side end portion of the drain region. The gate insulating film is provided thicker than the gate insulating film in other regions so as to completely cover the predetermined region.

A MOS type transistor according to a second aspect is
2. The MOS type transistor according to claim 1, wherein the source region comprises a source diffusion layer and a diffusion layer provided at an end of the source diffusion layer on the drain region side and having an impurity concentration lower than that of the source diffusion layer. The drain region has a single impurity diffusion structure, and the gate insulating film in a predetermined region below the drain region side end of the gate is a predetermined region at the source region side end of the drain region. So as to completely cover the gate insulating film in the other regions.

A MOS transistor according to claim 3 is
2. The MOS type transistor according to claim 1, wherein both the source region and the drain region have a single impurity diffusion structure, and a predetermined region below both ends of the gate on the source region side and the drain region side. The gate insulating film is provided thicker than the gate insulating films in other regions so as to completely cover a predetermined region at the drain region side end on the source region side and the source region side end of the drain region. Is.

In the above-mentioned MOS transistor, the gate insulating film in a predetermined region below the end of the gate on the drain region side is formed thicker than the gate insulating film in the other regions, and is thicker than the gate insulating films in the other regions. The thick gate insulating film completely covers the predetermined region at the end of the drain region on the source region side.
Regarding the relationship between the substrate breakdown voltage and the gate breakdown voltage, even if the gate insulating film is thinned due to miniaturization, drain-substrate breakdown voltage <gate breakdown voltage, and the current easily flows to the semiconductor substrate side rather than the gate side. That is, the electrostatic breakdown voltage becomes high.

The integrated circuit of claim 4 is the integrated circuit of claims 1, 2, and 3.
One of the MOS type transistors described is used for the input / output section, and the LDDMOS type transistor is used for the internal element section. In the above integrated circuit,
As described above, the MOS type transistor of the input / output section has a high electrostatic breakdown voltage and the drain-substrate breakdown voltage <gate breakdown voltage. Therefore, when a surge voltage is applied to the input / output section, the surge current is Flows from the region to the substrate, the gate insulating film on the edge of the drain region is less likely to be destroyed, and
Since the gate oxide film is less likely to be charged with electric charges, soft leak is less likely to occur. Therefore, the reliability of the integrated circuit is improved without adversely affecting the internal element portion.

A method for manufacturing a MOS type transistor according to a fifth aspect is a method for manufacturing the MOS type transistor according to the first aspect in parallel with the LDDMOS type transistor of the internal element portion, which is formed on a semiconductor substrate. A step of sequentially forming a gate insulating film and a gate, a step of implanting LDD ions into a semiconductor substrate using the gate as a mask, and a step of forming a pair of side spacers on a source region side and a drain region side of the gate, and isotropic etching. A step of removing at least the side spacers on the drain region side and the gate insulating film on the drain region side to expose the semiconductor substrate, and forming a gate insulating film again on the semiconductor substrate exposed in the above step by thermal oxidation The process and ion implantation into the semiconductor substrate using the gate as a mask are self-aligned Is intended to include the step of forming the in-region and the source region.

In the above manufacturing method, LDD ions are implanted to form a pair of side spacers for obtaining the LDD structure, and then isotropic etching is performed by using the gate as a mask to at least the side spacers on the drain region side, and By removing the gate insulating film on the drain region side and exposing the semiconductor substrate, etching proceeds not only in the vertical direction but also in the horizontal direction, and the gate insulating film below the drain region side end portion of the gate can be removed. Therefore, in the re-gate thermal oxidation step, the gate oxide film in the predetermined region below the drain region side end of the gate can be easily formed thicker than the gate insulating film in the other regions.

Further, the drain region can be easily formed while completely covering the predetermined region at the source region side end portion of the drain region with the thick gate insulating film in the predetermined region below the drain region side end portion of the gate. . That is, the mask alignment of the drain region can be performed easily and accurately. A method for manufacturing a MOS type transistor according to claim 6 is a method for manufacturing the MOS type transistor according to claim 2 in parallel with the LDDMOS type transistor of the internal element part, wherein the gate insulating film is formed on a semiconductor substrate. And a step of sequentially forming a gate, a step of implanting LDD ions into the semiconductor substrate using the gate as a mask, and then forming a pair of side spacers on a source region side and a drain region side of the gate, and a drain region by isotropic etching. The side spacer on the side and the gate insulating film on the drain region side to expose the semiconductor substrate, a step of forming a gate insulating film again on the semiconductor substrate exposed in the above step by thermal oxidation, and a gate and a source Self-alignment is achieved by ion implantation into the semiconductor substrate using the side spacers on the region side as a mask. It is intended to include a step of forming a drain region and a source region basis.

In the above manufacturing method, LDD ions are implanted to form a pair of side spacers for obtaining the LDD structure, and then isotropic etching is performed by using the side spacers on the gate and source regions as a mask to form a drain region on the drain region side. Remove the side spacer and gate insulating film,
By exposing the semiconductor substrate, the gate insulating film below the end portion of the gate on the drain region side is so-called side-etched.
The gate insulating film in a predetermined region below the end of the gate on the drain region side can be easily formed thicker than the gate insulating film in the other regions.

In addition, a thick gate insulating film of a predetermined region below the drain region side end portion of the gate completely covers the predetermined region at the source region side end portion of the drain region, and the drain region alone is easily formed. One impurity diffusion structure can be used. That is, the mask alignment of the drain region of the single impurity diffusion structure can be performed easily and accurately.

A method of manufacturing a MOS transistor according to a seventh aspect is a method for manufacturing the MOS transistor according to the third aspect in parallel with the LDDMOS transistor of the internal element section, which is formed on a semiconductor substrate. A step of sequentially forming a gate insulating film and a gate, a step of implanting LDD ions into a semiconductor substrate using the gate as a mask, and a step of forming a pair of side spacers on a source region side and a drain region side of the gate, and isotropic etching. A step of removing the pair of side spacers and the gate insulating film on the source region side and the drain region side to expose the semiconductor substrate, and forming a gate insulating film again on the semiconductor substrate exposed in the above step by thermal oxidation By the process and ion implantation into the semiconductor substrate using the gate as a mask,
It includes a step of forming a drain region and a source region in a self-aligned manner.

In the above-mentioned manufacturing method, LDD ions are implanted to form a pair of side spacers for obtaining the LDD structure, and then isotropic etching is performed by using the gate as a mask to form a pair of side spacers and the source region side and By removing the gate insulating film on the drain region side and exposing the semiconductor substrate, the gate insulating film below both ends of the gate on the source region side and the drain region side is side-etched. The gate insulating film in a predetermined region below both ends of the gate on the source region side and the drain region side can be easily formed thicker than the gate insulating films in other regions.

In addition, a thick gate insulating film in a predetermined region below both ends of the source region side and the drain region side of the gate, the predetermined region at the drain region side end of the source region and the source region side end of the drain region. It is possible to easily form the source region and the drain region into a single impurity diffusion structure while completely covering the above. That is, mask alignment of the source region and the drain region of the single impurity diffusion structure can be performed easily and accurately.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIGS.
Based on. FIG. 7 is a diagram showing a simplified configuration of an IC using the MOSFET according to the first embodiment of the present invention. Referring to FIG. 7, the MOSF according to the present embodiment
The configuration of the IC 20 using the ET will be described.

As shown in FIG. 7, the IC 20 has a high density of electronic circuits formed on a single P-type silicon substrate 21 based on a predetermined integrated circuit design. That is, IC20
The internal element portion 22 including, for example, a CPU is formed in the central portion of the P-type silicon substrate 21.
Surrounding the internal element section 22 and peripheral circuits (not shown)
A plurality of I / O units 23 for inputting / outputting between and are formed. Then, in the internal element portion 22, LDDMOSFE
T (not shown) is used, and the MOSFET 30 (see FIG. 1) according to the present embodiment is used for each I / O section 23.

FIG. 1 shows a MOSF according to the first embodiment of the present invention.
It is a schematic sectional drawing which shows the structure of ET. The structure of the MOSFET 30 according to this embodiment will be described with reference to FIG. The MOSFET 30 of the present embodiment is as shown in FIG.
The element is isolated by the field oxide film 31 formed on the surface of the P-type silicon substrate 21, and the channel region 32 and the channel region 32 are formed in the surface layer portion of the silicon substrate 21 in the region isolated by the field oxide film 31. N-type source region 33 and N-type drain region 34 sandwiched between
Are formed. The source region 33 and the drain region 3 are formed on the channel region 32 of the silicon substrate 21.
4 is bridged, and gate 3 is formed through gate oxide film 35.
6 is provided.

The P-type silicon substrate 21 has a specific resistance of 5 to 2
A relatively low impurity concentration of about 0 Ωcm is used. The field oxide film 31 is made of, for example, an insulating material such as SiO _{2 and} has a thickness of about 10,000 Å for element isolation.
It is provided to be thick. Immediately below the field oxide film 31, the threshold value of the MOSFET 30 is controlled to prevent the formation of a parasitic channel below the field oxide film 31, so that the channel stop ion concentration of, for example, B ⁺ is increased. The P-type impurity diffusion layer (hereinafter, referred to as “channel stopper”) 37 is formed.

Length of channel region 32 (channel length)
Is the LDDMOSFE used in the internal element section 22.
It is set longer than the channel length of T. The N-type source region 33 has a structure in which the impurity distribution of the source region 33 is made as gentle as possible. That is, the source region 33 is provided so as to protrude from the N-type diffusion layer 33a having a high concentration of N-type ions such as As ⁺ and P ⁺ and the end of the N-type diffusion layer 33a on the drain region 34 side, for example, P ^+. LDD ion concentration equal less than N-type diffusion layer 33a N ^-
And the mold diffusion layer 33b.

The N-type drain region 34 is formed of, for example, As ⁺ ,
It has a single drain structure in which the concentration of N-type ions such as P ⁺ is increased. The gate oxide film 35 is, for example, SiO ₂
It is made of an insulating material such as, and has a thin film thickness of about 250 Å and is connected to the field oxide film 31. In addition, the gate oxide film 35c in a predetermined region below the end of the gate 36 on the drain region 34 side.
Is about 35 in order to increase the electrostatic breakdown voltage of the MOSFET 30.
It is provided to have a thickness of about 0Å and is thicker than the gate oxide film 35 in other regions.
It completely covers the predetermined area at the side edge.

The gate 36 is made of a conductive material such as polysilicon which has been doped with phosphorus at a high concentration to reduce its resistance. The source region 33 has an LDD structure at the end of the gate 36 on the source region 33 side. For this purpose, side spacers 38 made of an insulating material such as SiO ₂ are deposited. That is, the gate 36 is surrounded by an insulating film such as SiO ₂ .

Further, the entire surface of the silicon substrate 21 is PSG (phospho-silicate glass) which is P-doped SiO _2.
BPSG (boron-phospho-silicate gl) with B mixed in
It is covered with an interlayer insulating film 39 made of an insulating material such as ass). Then, the interlayer insulating film 39 and the gate oxide film 35.
In the above, a source contact hole 40 is formed in a portion of the source region 33 corresponding to the N type diffusion layer 33 a, and a source electrode wiring 41 is formed through the source contact hole 40 so as to contact the N type diffusion layer 33 a. ing. Similarly, a drain contact hole 42 is formed in a portion corresponding to the drain region 34, and a drain electrode wiring 43 is formed so as to contact the drain region 34 through the drain contact hole 42. Further, a gate contact hole 44 is formed in a portion corresponding to the gate 36, and a gate electrode wiring 45 is formed so as to contact the gate 36 through the gate contact hole 44. Therefore, the source electrode wiring 41, the drain electrode wiring 43, and the gate electrode wiring 45 are insulated from each other by the interlayer insulating film 39.

Source electrode wiring 41, drain electrode wiring 4
3 and the gate electrode wiring 45 are made of a conductive material such as Al, and M on each electrode wiring 41, 43, 45.
A passivation film 46 made of an insulating material such as PSG is formed on the entire surface of the silicon substrate 21 to protect the surface of the OSFET 30 and prevent contaminants from entering from the outside.

In the above structure, the gate oxide film 35c in a predetermined region below the end of the gate 36 on the drain region 34 side is formed thicker than the gate oxide film 35 in the other region, and the gate oxide film in the other region is formed. Since the gate oxide film 35c formed thicker than 35 completely covers a predetermined region at the end of the drain region 34 on the source region 33 side, the relationship between the drain-substrate breakdown voltage and the gate breakdown voltage of the MOSFET 30 is shown in FIG. As shown. That is,
Regarding the relationship between the drain-substrate breakdown voltage and the gate breakdown voltage, even if the gate oxide film 35 is thinned by miniaturization, the drain-substrate breakdown voltage X <the gate breakdown voltage Y, and the current flows to the silicon substrate 21 side rather than the gate 36 side. It will be easier. That is,
The electrostatic breakdown voltage of the MOSFET 30 becomes stronger.

In the I / O unit 23 of the IC 20, the MOS
The drain of the FET 30 is directly connected to the input / output pad (not shown). As described above, the MOSFET 30 has high electrostatic breakdown voltage and drain-substrate breakdown voltage <gate breakdown voltage. Therefore, when a surge voltage is applied to the input / output pad, a surge current flows from the drain region 34 to the substrate 21.
To the gate oxide film 35c on the edge of the drain region 34.
Is less likely to be destroyed, and the gate oxide film 35 is less likely to be charged with electric charges, so that soft leak is less likely to occur. Therefore, the reliability of the IC 20 can be improved without adversely affecting the internal element portion 22.

The drain region 3 of the MOSFET 30
4 has a single drain structure instead of the LDD structure because the channel length of the MOSFET 30 is
This is because it is set longer than the channel length of the LDD MOSFET used in No. 2 and it is not necessary to consider hot electrons so much. 3 (a)-(d),
4 (a) to (d), 5 (a) to (c) and FIG.
(A)-(c) is a schematic sectional drawing which shows the manufacturing method of said MOSFET in order of process. 3 (a) to 3 (d) and FIG.
(A)-(d), FIG. 5 (a)-(c) and FIG. 6 (a).
A method of manufacturing the MOSFET 30 will be described with reference to (c). The MOSFET 30 is built in the P-type silicon substrate 21 in parallel with the LDD MOSFET of the internal element section 22.

First, element isolation is performed. That is, FIG.
As shown in FIG.
Approximately 10 times on the silicon substrate 21 by thermal oxidation at ~ 1000 ° C.
A pad oxide film 50 of 00Å is formed. Then, Fig. 3
As shown in (b), CVD (chemical vapor depositi
on) method, silicon nitride (S
The i ₃ N ₄ ) film 51 is laminated by about 1000Å. And S
A resist pattern 52 is formed on a predetermined region of the i ₃ N ₄ film 51. This resist pattern 52 becomes a pattern that defines a region in which a transistor will be formed.

Then, as shown in FIG.
Using the printed pattern 52 as a mask₃N_FourOne of the membranes 51
Etch the department. For this etching, for example
CF _Four/ O₂Of plasma etching is preferred
Yes. Next, using the same resist pattern 52 as a mask,
For example B⁺Channel stop ions such as 10¹³cm
^-2Inject about. At this point, the cash register used as the mask
Since the strike pattern 52 is already used, O₂Plasma treatment
As a result, the resist pattern 52 is ashed.
To do.

Then, as shown in FIG. 3D, the silicon substrate 21 is oxidized in a water vapor (H ₂ O) atmosphere at about 1000 ° C. for about 6 to 7 hours and is not covered with the Si ₃ N ₄ film 51. A field oxide film 31 of about 10000 Å is grown on the surface of the silicon substrate 21. Then, the P-type channel stopper 37 is formed immediately below the field oxide film 31. Here, H ₂ O is used instead of dry oxygen because the oxidation rate is high and the oxidation time can be shortened.

When the element isolation process is completed, gate oxidation and gate formation are performed. That is, as shown in FIG. 4A, the pad oxide film 50 and the Si ₃ N ₄ film 51 are removed by etching to expose the surface of the silicon substrate 21. Then, as shown in FIG. 4B, the silicon substrate 2
1 is thermally oxidized at about 900 to 1000 ° C. to form a gate oxide film 53 of about 250 Å on the silicon substrate 21 exposed in FIG. At this time, the both ends of the gate oxide film 53 are covered with the bird's beak of the field oxide film 31.
k). Then, polysilicon is deposited on the entire surface by the CVD method, and P or the like is added to the polysilicon. Then, a resist pattern (not shown) is formed on a predetermined region of the polysilicon, and the polysilicon is etched using the resist pattern as a mask to form the gate 36. Regarding the etching of polysilicon, it is important to perform an accurate etching process according to the resist pattern, and therefore it is preferable to use RIE (reactive ion etching).

When the gate oxidation step and the gate formation step are completed, ions are implanted. That is, as shown in FIG. 4C, with the gate 36 as a mask, LDD ions such as P ⁺ are supplied to the silicon substrate 21 for about 10 ¹³ cm ^−2.
To the surface layer. Then, as shown in FIG. 4C, SiO ₂ is deposited on the entire surface by the CVD method, and the entire surface is etched back by RIE to form a pair on both sides of the gate 36 (the source region 33 side and the drain region 34 side). Side spacers 38 and 54 are formed.

Thereafter, as shown in FIG. 5A, a resist 55 is applied and masked on the entire surface. And FIG.
As shown in (b), the resist 55, the side spacers 54, and the gate oxide film 53 on the drain region 34 side are removed by isotropic etching using HF to expose the silicon substrate 21. At this time, the etching progresses isotropically in both the vertical and horizontal directions, and the gate oxide film 53 below the end of the gate 36 on the drain region 34 side is also
It is removed by so-called side etching. As a result, the gate 36 is formed on the remaining gate oxide film 53 in an overhang state protruding toward the drain region 34. At this point, the resist 55 used as the mask has been used up, so that ashing is performed by O ₂ plasma treatment.

Then, as shown in FIG. 5C, the silicon substrate 21 is again thermally oxidized at about 900 to 1000 ° C. to form a gate oxide film 35 of about 250 Å on the silicon substrate 21. At this time, the drain region 3 in the gate 36
Since the polysilicon on the 4 side is also oxidized at the same time, the gate 3
The gate oxide film 35c in a predetermined region below the end of the drain region 34 of 6 is formed to be thicker than the gate oxide film 35 in other regions by about 350 Å. Further, the gate 36 is surrounded by an insulating film. After that, annealing is performed at about 900 ° C. Then, in self-alignment, the N ⁻ type diffusion layer 33b and the N ⁻ type LDD diffusion layer 34b are bonded to the P type silicon substrate 21 with the channel region 32 interposed therebetween.

Next, as shown in FIG. 6A, the gate 3
6 and the side spacer 38 as a mask, for example, A
s ⁺ or the like is implanted into the silicon substrate 21 at about 6 × 10 ¹⁵ cm ^-2 , and the gate 36 and the side spacers 38 are also formed.
As a mask, for example, P ⁺ is implanted into the silicon substrate 21 at about 6 × 10 ¹⁵ cm ⁻² . When the ion implantation is completed, an interlayer insulating film is formed. That is, as shown in FIG. 6B, BPSG is deposited by the CVD method to form the interlayer insulating film 39. Then, reflow is performed to flatten the surface of the interlayer insulating film 39. After that, about 900-9
Anneal at 50 ° C. Then, in a self-aligned way,
High concentration N-type diffusion layer 33a and N-type drain region 34
, But are bonded to the P-type silicon substrate 21 with the channel region 32 interposed therebetween. That is, only the drain region 34 has a single drain structure. The predetermined region at the end of the drain region 34 on the source region 33 side is completely covered with the thick gate oxide film 35c in the predetermined region below the end of the gate 36 at the drain region 34 side.

When the above step of forming the interlayer insulating film is completed, a metallization and a peggedation film are formed. That is, as shown in FIG. 6C, a resist (not shown) is applied to the entire surface for mask alignment, and a hole is formed in the resist only at the wiring outlet. Then, using the resist as a mask, the interlayer insulating film 39 and the lower gate oxide film 35 are removed by etching by RIE, and the N-type diffusion layer 33a and the drain region 34 in the source region 33 and the contact holes 40, 42, 44 are opened respectively. Then, after stripping the resist, for example, Al or the like is vapor-deposited on the entire surface by, for example, sputtering,
Using mask alignment and RIE, each electrode wiring 41,
43 and 45 are patterned. Then, for example, PSG is deposited on the entire surface by the CVD method to form the passivation film 46.

According to the manufacturing method as described above, FIG.
After the pair of side spacers 38 and 54 are formed at both ends of the gate 36 for obtaining the LDD structure on the source region 33 side and the drain region 34 side in the step (d), FIG.
In the step of, isotropic etching is performed by using the side spacers 38 on the side of the gate 36 and the source region 33 as a mask,
By removing the side spacer 54 and the gate oxide film 53 on the drain region 34 side to expose the silicon substrate 21, the gate oxide film 53 below the end of the gate 36 on the drain region 34 side can be side-etched. In the gate thermal oxidation step, the gate oxide film 35c in a predetermined region below the end of the gate 36 on the drain region 34 side can be easily formed thicker than the gate oxide film 35 in other regions (FIG. See c)).

In addition, the thick gate oxide film 3 in a predetermined region below the end of the gate 36 on the drain region 34 side.
With 5c, it is possible to easily form only the drain region 34 into a single drain structure while completely covering a predetermined region at the end of the drain region 34 on the source region 33 side (see FIG. 6B). That is, the mask alignment of the drain region 34 having the single drain structure can be performed easily and accurately.

Next, a second embodiment of the present invention will be described in detail with reference to FIGS. FIG. 8 is a schematic sectional view showing the structure of a MOSFET according to the second embodiment of the present invention. Figure 8
The structure of the MOSFET 30 according to the present embodiment will be described with reference to FIG. The MOSFET 30 of this embodiment is the first
The difference from the embodiment is that the N-type source region 33 has a single source structure as shown in FIG.
Of the gate oxide film 35d in a predetermined region below the end of the source region 33 on the side of the source region 33 is thicker than the gate oxide film 35 in other regions by about 350 Å, and the source region 34 is formed by the thick gate oxide film 35d. The point is that the predetermined area is completely covered. Other configurations, operations, and effects are similar to those of the first embodiment.

The source region 33 also has a single source structure because the channel length of the MOSFET 30 is set longer than the channel length of the LDDMOSFET used in the internal element portion 22, and hot electrons are taken into consideration. It is not necessary. 9 (a)-
10C and 10A and 10B are schematic cross-sectional views showing a method of manufacturing the MOSFET in the order of steps. FIG. 9 (a)
10 (a) and 10 (b), a method of manufacturing the MOSFET 30 will be described. In addition,
3 (a) to (d), FIGS. 4 (a) to (d) and FIG.
Since the steps up to (a) are the same as those in the first embodiment, the description thereof will be omitted.

After forming side spacers 38 and 54 at both ends of the gate 36 to obtain an LDD structure and covering the entire surface with a resist 55 (see FIG. 5A), as shown in FIG. 9A. By isotropic etching using HF, the pair of side spacers 38, 54 and the gate oxide film 53 on the source region 33 side and the drain region 35 side are removed to expose the P-type silicon substrate 21. At this time, the etching progresses isotropically both in the vertical direction and in the horizontal direction, and the gate oxide film 53 below both ends of the gate 36 on the source region 33 side and the drain region 34 side is also removed.
As a result, the gate 36 is formed on the remaining gate oxide film 53 in an overhang state protruding toward both the source region 33 side and the drain region 34 side. The resist 60 used as the mask is ashed at this point and is ashed.

Then, as shown in FIG. 9B, the silicon substrate 21 is again thermally oxidized at about 900 to 1000 ° C. to form a gate oxide film 35 of about 250 Å on the silicon substrate 21. At this time, the source region 33 in the gate 36
Since the polysilicon on the drain side and the drain region 34 side is also oxidized at the same time, the gate oxide film 35c in a predetermined region below the ends of the gate 36 on the source region 33 side and the drain region 34 side is about 350 .ANG. Will be formed thicker than the gate oxide film 35. Further, the gate 36 is surrounded by an insulating film. Then, when annealing is performed, the N ⁻ -type LDD diffusion layer 3 is self-aligned.
3b and the N ⁻ type LDD diffusion layer 34b are bonded to the P type silicon substrate 21 with the channel region 32 interposed therebetween.

Subsequent manufacturing steps are the same as those for manufacturing a normal MOSFET. In the source and drain forming process, as shown in FIG. 9C, for example, As ⁺ and P ⁺ are added to the silicon substrate 21 using the gate 36 as a mask.
Inject. In the interlayer insulating film forming step, as shown in FIG. 10A, BPSG is deposited to form the interlayer insulating film 39, and then reflow is performed to flatten the surface of the interlayer insulating film 39. After that, annealing is performed. Then, the N-type source region 33 and the N-type drain region 3 are self-aligned.
4 is a P-type silicon substrate 21 with a channel region 32 interposed therebetween.
To each. That is, the source region 33 has a single source structure and the drain region 34 has a single drain structure. Further, the predetermined regions at the drain region 34 side end of the source region 33 and the source region 33 side end of the drain region 33 are the predetermined regions below the source region 33 side and the drain region 34 side ends of the gate 36. It is completely covered with the thick gate oxide films 35c and 35d.

In the metallization and peggedation film forming step, as shown in FIG. 10B, contact holes 40, 42 and 44 are opened on the source region 33, the drain region 34 and the gate 36, respectively. The electrode wirings 41, 43, 45 are patterned. Then, for example, PSG is deposited on the entire surface to form the passivation film 46.

According to the manufacturing method as described above, a pair of side spacers 38 and 5 are provided at both ends of the gate 36 for obtaining the LDD structure on the source region 33 side and the drain region 34 side.
4 is formed, the source region 33 is formed by isotropic etching using the gate 36 as a mask in the step of FIG.
Of the gate oxide film 53 on the side of the drain region 34 and the side of the drain region 34 to expose the silicon substrate 21.
Since the gate oxide film 53 below both ends of the source region 33 side and the drain region 34 side can be side-etched, in the re-gate thermal oxidation step, both ends of the gate 36 on the source region 33 side and the drain region 34 side are removed. Gate oxide film 35 in a predetermined region below
c and 35d can be easily formed thicker than the gate oxide film 35 in other regions (see FIG. 9B).

Further, the thick gate oxide films 35c and 35d in predetermined regions below both ends of the gate 36 on the source region 33 side and the drain region 34 side are formed by the end regions of the source region 33 on the drain region 34 side and the drain region 34.
It is possible to easily make the source region 33 have a single source structure and the drain region 34 have a single drain structure while completely covering a predetermined region at the end of the source region 33 side (see FIG. 10A). That is, mask alignment of the source region 33 having the single source structure and the drain region 34 having the single drain structure can be performed easily and accurately.

The present invention is not limited to the above embodiments, and it goes without saying that many changes or modifications can be made within the scope of the present invention. In the above example,
Although an N-channel MOSFET has been described, the present invention may be applied to a P-channel MOSFET.

[0059]

As is apparent from the above description, according to the MOS transistor of the first to third aspects of the present invention, the relationship between the drain-substrate breakdown voltage and the gate breakdown voltage is reduced even if the gate insulating film is thinned by miniaturization. , Drain-substrate breakdown voltage <gate breakdown voltage, and electrostatic breakdown voltage increases.

In the integrated circuit according to the fourth aspect, when the surge voltage is applied to the input / output section, the surge current changes to the MO of the input / output section.
Since it flows from the drain region of the S-type transistor to the substrate, the gate insulating film on the end of the drain region is less likely to be destroyed, and the gate oxide film is less likely to be charged with electric charge.
Soft leaks are unlikely to occur. Therefore, the internal element portion is not adversely affected, and the reliability of the integrated circuit is improved.

According to the manufacturing method of the fifth aspect, in the re-gate thermal oxidation step, the gate oxide film in the predetermined region below the end of the gate on the drain region side is easily made thicker than the gate insulating film in the other regions. Can be formed.
In addition, a thick gate insulating film in a predetermined region below the end of the gate on the drain region side completely covers the predetermined region on the end of the drain region on the source region side, and the mask alignment of the drain region is performed easily and accurately. be able to.

According to the manufacturing method of claim 6, in the re-gate thermal oxidation step, the gate insulating film in a predetermined region below the end of the gate on the drain region side is easily formed thicker than the gate insulating film in the other regions. can do. In addition, a thick gate insulating film in a predetermined region below the end of the gate on the drain region side completely covers the predetermined region at the end of the drain region on the source region side. Can be done easily and accurately.

According to the manufacturing method of claim 7, in the re-gate thermal oxidation step, the gate insulating film in a predetermined region below both ends of the gate on the source region side and the drain region side is easily changed to a gate insulating film in another region. Can be formed thicker than. In addition, a thick gate insulating film in a predetermined region below both ends of the gate on the source region side and the drain region side is used to completely cover the predetermined region at the drain region side end of the source region and the source region side end of the drain region. It is possible to easily and accurately perform mask alignment of the source region and the drain region of the single-impurity diffusion structure which covers.

[Brief description of drawings]

FIG. 1 is a schematic sectional view showing the structure of a MOSFET according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between a drain-substrate breakdown voltage and a gate breakdown voltage of a MOSFET.

FIG. 3 is a schematic cross-sectional view showing the method of manufacturing the MOSFET in order of steps.

FIG. 4 is a schematic cross-sectional view showing the method of manufacturing the MOSFET following FIG. 3, in order of steps.

FIG. 5 is a schematic cross-sectional view showing the method of manufacturing the MOSFET following FIG. 4, in order of steps.

FIG. 6 is a schematic cross-sectional view showing the method of manufacturing the MOSFET following FIG. 5, in order of steps.

FIG. 7 is a diagram showing a simplified configuration of an IC using a MOSFET.

FIG. 8 is a schematic sectional view showing the structure of a MOSFET according to a second embodiment of the present invention.

FIG. 9 is a schematic cross-sectional view showing the method of manufacturing the MOSFET in order of steps.

FIG. 10 is a schematic cross sectional view showing the method of manufacturing the MOSFET in the order of steps, which is subsequent to FIG. 9;

FIG. 11 is a diagram showing a cross-sectional structure of the most basic MOSFET.

FIG. 12 is a diagram schematically showing a short channel effect of a MOSFET.

FIG. 13 is a schematic cross-sectional view showing the structure of an LDD MOSFET.

FIG. 14 is a diagram showing a relationship between a drain-substrate breakdown voltage and a gate breakdown voltage of an LDD MOSFET.

FIG. 15 is an equivalent circuit diagram when an LDD MOSFET is used in the IC I / O section.

[Explanation of symbols]

20 IC 21 P-type silicon substrate 22 Internal element part 23 I / O part 30 MOSFET 32 Channel region 33 N-type source region 33a N-type diffusion layer 33b N ^- type diffusion layer 34 N-type drain region 35, 53 Gate oxide film 35c Gate Oxide film 35d in a predetermined region below the end of the drain region side of the gate oxide film 36 in a predetermined region below the end of the source region side of the gate 36 gates 38, 54 side spacers

Claims (7)

[Claims] 1. An integrated circuit in which an LDDMOS transistor is used for an internal element section, which is used for an input / output section for inputting / outputting to / from an internal element section, and which sandwiches a channel region and a channel region. A semiconductor substrate having a source region and a drain region formed therein, and a gate formed on a channel region of the semiconductor substrate via a gate insulating film in a state of bridging the source region and the drain region. Is the LDDMOS of the internal element
The gate insulating film is provided longer than the channel length of the FET, and the gate insulating film in the predetermined region below at least the drain region side end portion of the gate completely covers the predetermined region in the drain region source region side end portion. In addition, the MOS type transistor is provided thicker than the gate insulating film in the other regions. 2. The MOS type transistor according to claim 1, wherein the source region is a source diffusion layer, and a diffusion layer having an impurity concentration lower than that of the source diffusion layer is provided at an end of the source diffusion layer on the drain region side. The drain region has a single impurity diffusion structure, and the gate insulating film in a predetermined region below the drain region side end of the gate is the source region side end of the drain region. A MOS transistor, which is formed thicker than a gate insulating film in other regions so as to completely cover a predetermined region in each part. 3. The MOS transistor according to claim 1, wherein both the source region and the drain region have a single impurity diffusion structure, and the source region side and the drain region side end portions of the gate are both The gate insulating film in the predetermined region below is thicker than the gate insulating films in other regions so as to completely cover the predetermined region at the drain region side end on the source region side and the source region side end of the drain region. A MOS transistor, which is provided. 4. The MOS according to claim 1, 2, or 3.
Type transistor is used for the input / output section, and LDDMOS type transistor is used for the internal element section. 5. A method for manufacturing the MOS type transistor according to claim 1 in parallel with the LDDMOS type transistor of the internal element part, comprising the steps of sequentially forming a gate insulating film and a gate on a semiconductor substrate, After implanting LDD ions into the semiconductor substrate using the gate as a mask, a step of forming a pair of side spacers on the source region side and the drain region side of the gate, at least by the isotropic etching, the side spacer on the drain region side, and A step of removing the gate insulating film on the drain region side and exposing the semiconductor substrate, a step of forming a gate insulating film again on the semiconductor substrate exposed in the above step by thermal oxidation, and a semiconductor substrate using the gate as a mask Forming a drain region and a source region in a self-aligned manner by ion implantation of A method of manufacturing a MOS transistor, comprising: 6. A method for manufacturing a MOS type transistor according to claim 2 in parallel with the LDDMOS type transistor of the internal element part, comprising the steps of sequentially forming a gate insulating film and a gate on a semiconductor substrate, After implanting LDD ions into the semiconductor substrate using the gate as a mask, a step of forming a pair of side spacers on the source region side and the drain region side of the gate, side spacers on the drain region side and the drain region by isotropic etching Side gate insulation film is removed,
The step of exposing the semiconductor substrate, the step of forming a gate insulating film again on the semiconductor substrate exposed in the step by thermal oxidation, and the ion implantation into the semiconductor substrate using the side spacers on the gate and source regions as a mask, M including a step of forming a drain region and a source region in a self-aligned manner
A method for manufacturing an OS transistor. 7. A method for manufacturing a MOS type transistor according to claim 3 in parallel with the LDDMOS type transistor of the internal element part, comprising the steps of sequentially forming a gate insulating film and a gate on a semiconductor substrate, After the LDD ions are implanted into the semiconductor substrate using the gate as a mask, a step of forming a pair of side spacers on the source region side and the drain region side of the gate, by isotropic etching, a pair of side spacers and a source region side and A step of removing the gate insulating film on the drain region side and exposing the semiconductor substrate, a step of forming a gate insulating film again on the semiconductor substrate exposed in the above step by thermal oxidation, and a semiconductor substrate using the gate as a mask The step of forming a drain region and a source region in a self-aligned manner by ion implantation of A method for manufacturing a MOS transistor, comprising: