JPH06283680A - Mos semiconductor device - Google Patents

Abstract

PURPOSE:To provide a MOS semiconductor device which can prevent the occurrence of a punch through phenomenon and parasitic MOS leakage even when no guard area is provided and has a small element area and an excellent high voltage resistance. CONSTITUTION:A source electrode 211 is provided below a drain electrode 221 so that the electrode 211 can cross part of the drain electrode 221. When a high-level potential is applied across the drain electrode 221 while a semiconductor substrate 100 and the source electrode 211 are maintained at low-level potentials, an inversion layer 230 is formed below the drain electrode 221. However, since the source electrode 211 crosses part of the drain electrode 221, the inversion layer is not formed at the crossing part due to the potential of the source electrode 211. Therefore, the occurrence of leakage caused by a parasitic MOS can be suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high breakdown voltage MO used in a large scale integrated circuit (LSI) for driving a display.
The present invention relates to an S semiconductor device.

[0002]

2. Description of the Related Art A MOS semiconductor device used in an LSI or the like is an N channel MOSFET (N channel insulated gate field effect transistor, hereinafter referred to as NMOS) or P channel.
It is composed of only a channel MOSFET (hereinafter referred to as PMOS) or a complementary MOSFET (hereinafter referred to as CMOS) in which NMOS and PMOS are connected in series. For these MOS semiconductor devices, various proposals have been made in order to increase the breakdown voltage, as described in, for example, JP-A-61-27052.
2 (a) and 2 (b) are views showing a conventional high breakdown voltage CMOS semiconductor device described in the above-mentioned document, FIG. 2 (a) is a sectional view, and FIG. 2 (b) is a partially enlarged view thereof. It is a top view.
In this high breakdown voltage CMOS semiconductor device, as shown in FIG. 2A, a latch-up prevention structure is adopted. That is,
A P-type well region 2 is formed in the N-type silicon substrate 1, and the field regions of the silicon substrate 1 and the well region 2 are selectively oxidized (Local Oxidation of Silicon met).
A buried field oxide film 3 formed by hod (hereinafter referred to as LOCOS method) is formed. Silicon substrate 1
A PMOS 10 is formed on the main surface of, and an NMOS 20 is also formed on the main surface of the well region 2. PM
The OS 10 is composed of a P ⁺ type source region 11 and a drain region 12, and a gate electrode 14 made of polysilicon on the gate oxide film 13. The NMOS 20 is
An N ⁺ type source region 21 and a drain region 22, and a gate electrode 24 made of polysilicon on the gate oxide film 23.
It consists of and. Further, under the field oxide film 3, the channel stopper regions 31, 32 having a low impurity concentration are formed.
And high-impurity-concentration guard regions 33 and 34 are formed.

As shown in FIG. 2B, each source region 1
1, 21 and the drain regions 12 and 22 are provided with contact holes 41, and the PMOS 10 and the NMOS 20 pass through these contact holes 41 and the PMOS 10 and the NMOS 20 are shown by broken lines A.
They are connected to each other by an L wiring 42 to form an inverter circuit. In addition, the Al wiring 42 and the silicon substrate 1,
And each element formed on the main surface of the well region 2 and the Al
The wirings 42 are insulated from each other by an insulating film except for the contact holes 41. The feature of this CMOS semiconductor device is that the field oxide film 3 is formed as shown in FIG.
It is in the structure below. That is, the N-type channel stopper region 31 having a low impurity concentration is provided on the entire lower surface of the field oxide film 3 formed on the silicon substrate 1, and is separated from the P ⁺ -type source region 11 and the drain region 12 of the PMOS 10,
A high impurity concentration N ⁺ type guard region 33 is formed in the channel stopper region 31. Also, the well region 2
A low impurity concentration P-type channel stopper region 32 is provided on the entire lower surface of the field oxide film 3 on the side of the NMOS 2
0 of the N ⁺ type source region 21 and the drain region 22, and a high impurity concentration of P in the channel stopper region 32.
A mold guard area 34 is formed.

Generally, in a high breakdown voltage CMOS semiconductor device, the impurity concentration of the channel stopper regions 31 and 32 is lowered in order to increase the junction breakdown voltage of the source regions 11 and 21, the drain regions 12 and 22, and the channel stopper regions 31 and 32. There is a need. However, the channel stopper region 3
If 1 and 32 are formed to have a low impurity concentration, inversion occurs under the field oxide film 3 to generate a parasitic MOS, and latch-up easily occurs. Therefore, in order to prevent latch-up, the channel stopper regions 31 and 32 are set to a sufficiently low concentration, and the guard regions 33 and 34 are set to a high concentration to realize a high breakdown voltage CMOS semiconductor device.

[0005]

However, in the CMOS semiconductor device having the above configuration, it is necessary to provide the guard regions 33 and 34 between the adjacent PMOS 10 and NMOS 20, so that the element spacing between those PMOS 10 and NMOS 20 is widened. This greatly hinders the reduction of the element area. On the contrary, if the guard regions 33 and 34 are removed in order to reduce the element area, the drain regions 12 and 2 are removed.
A defect called a punch-through phenomenon in which a depletion layer from 2 reaches an adjacent element, or a portion directly under the lead wiring of the drain regions 12 and 22 is inverted, and a parasitic MOS between adjacent elements is generated.
Since a leak is generated, it is difficult to provide a MOS semiconductor device which is technically sufficiently satisfactory. The present invention solves the problem that the above-mentioned conventional art has that the element area becomes large when a guard region is provided in order to prevent a punch-through phenomenon and parasitic MOS leakage, and an excellent MOS having a small element area is solved. A semiconductor device is provided.

[0006]

According to a first aspect of the present invention, in order to solve the above problems, a predetermined surface is provided on a main surface of a semiconductor substrate of a first conductivity type of first and second conductivity types having opposite polarities. A source region and a drain region that are formed apart from each other, a source electrode and a drain electrode that are respectively drawn from the source region and the drain region, and a gate insulating film disposed between the source region and the drain region. In a MOS semiconductor device including a gate electrode, the following measures are taken. That is, the source electrode is arranged below the drain electrode and across a part of the drain electrode. In the second invention, the source electrode of the first invention is arranged so as to surround the periphery of the drain region.

[0007]

According to the first invention, since the MOS semiconductor device is constructed as described above, for example, the semiconductor substrate and the source electrode are held at the "L" level potential, and the drain electrode is held at the "H" level potential. Is applied, an inversion layer is formed thereunder by the electric field of the drain electrode. However,
Since the source electrode is formed under the drain electrode, the electric field of the drain electrode terminates at the source electrode,
The inversion layer is not formed at the intersection of the drain electrode and the source electrode. According to the second invention, for example, the first
Similarly to the invention of 1, the depletion layer extends from the drain region when the semiconductor substrate and the source electrode are held at the “L” level and a potential of the “H” level is applied to the drain electrode. However, since the periphery of the drain region is surrounded by the “L” level source electrode, the electric field of the drain electrode terminates at the source electrode. That is, the depletion layer extending from the drain region is blocked by the potential of the source electrode. Therefore, the above problem can be solved.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIGS. 1 (a) and 1 (b) show the high breakdown voltage M of the first embodiment of the present invention.
FIG. 3 is a diagram showing an OS semiconductor device (eg, NMOS),
The figure (a) is a plan view and the figure (b) is its A1-A2.
It is a line expansion sectional view. A field insulating film 101 for element isolation is formed on the main surface of the P-type semiconductor substrate 100.
NMO is formed in the region surrounded by the field insulating film 101.
S200 is formed. The NMOS 200 has an N ⁺ type source region 201 and a drain region 202 formed on the main surface of the semiconductor substrate 100 with a predetermined distance therebetween, and a gate insulating film (not shown) is provided between the source region 201 and the drain region 202. A gate electrode 203 made of polysilicon or the like is disposed therewith, and the entire surface thereof is covered with the insulating film 102.

Source region 201 and drain region 202
First and second contact holes 210 and 220 are formed in the upper insulating film 102, respectively. A source electrode 211 made of a metal such as Al is formed as a first layer wiring on the first contact hole 210, and the source electrode 211 is connected to the source region 201 through the contact hole 210. There is. The source electrode 21 is formed on the source electrode 211 at the X portion through the insulating film 102.
A drain electrode 221 made of metal such as Al for the second layer is formed so as to cross
1 is connected to the drain region 202 via the second contact hole 220. This kind of NMOS200
Then, for example, the semiconductor substrate 100 is set to the “L” level of the ground potential VSS, the drain electrode 221 is set to the “H” level on the power supply potential VDD side, and the source electrode 211 is set to the “L” level on the ground potential VSS side. Connecting. Then, when an “H” level potential is applied to the gate electrode 203, the depletion layer formed near the main surface of the semiconductor substrate 100 below the gate electrode 203 becomes thin, and the drain region 20.
2 and the source region 201, a current path (channel) formed between the source electrode 211 and the drain electrode 221 is turned on. On the other hand, when an “L” level potential is applied to the gate electrode 203, the depletion layer formed under the gate electrode 203 becomes thicker, the channel between the source region 201 and the drain region 202 becomes thinner, and the source becomes thinner. The state between the electrode 211 and the drain electrode 221 is turned off.

In this embodiment, when the drain electrode 221 is at "H" level, the inversion layer 230 is formed below the field insulating film 101 due to the influence of the electric field.
At this time, since the source electrode 211 has the same “L” level as the semiconductor substrate 100, the electric field of the drain electrode 221 terminates at the source electrode 211. Therefore, the inversion layer 230 is not formed below the field insulating film 101 at the intersection of the drain electrode 221 and the source electrode 211, so that the leakage due to the parasitic MOS is suppressed. Therefore, it is not necessary to form a high-concentration guard region as in the conventional case, and the element area can be reduced.

Second Embodiment FIGS. 3A and 3B show a high breakdown voltage M of the second embodiment of the present invention.
FIG. 3 is a diagram showing an OS semiconductor device (eg, NMOS),
The same figure (a) is a top view and the same figure (b) is B1-B2.
It is a line expansion sectional view. Elements common to those in FIG. 1 showing the first embodiment are designated by common reference numerals. In this NMOS 200, as in the first embodiment, a gate electrode 203 is formed between the N ⁺ type source region 201 and the drain region 202, and the source region 201 is formed in the first layer via the first contact hole 210. Source electrode 21
1 and the drain region 202 is further connected to the drain electrode 2 of the second layer through the second contact hole 220.
21 is connected. Here, the present embodiment is different from the first embodiment in that the source electrode 211 is the drain electrode 22.
That is, it is formed so as to traverse a part of No. 1 and surround the periphery of the drain region 202 except for the gate electrode 203 side.

In the NMOS 200 of this embodiment, the semiconductor substrate 100 and the source electrode 211 are maintained at the “L” level potential and the drain electrode 22 is used, as in the first embodiment, for example.
If an “H” level potential is applied to 1, the gate electrode 20
When 3 is at "H" level, the source electrode 211 and the drain electrode 221 are turned on. On the other hand, when the gate electrode 203 is at “L” level, the source electrode 211 and the drain electrode 221 are turned off. Here, since the drain electrode 221 is at the “H” level potential, the electric field from the drain electrode 221 causes the field insulating film 10 to pass through.
The depletion layer 240 extends downwardly by 1. However, since the drain region 202 is surrounded by the “L” level source electrode 211, the electric field of the drain electrode 221 terminates at the source electrode 211. Therefore, the drain region 202
The depletion layer 240 extending from the source electrode 211 is suppressed by the potential of the source electrode 211, the extension of the depletion layer 240 is blocked, and a punch-through phenomenon to an adjacent transistor can be prevented. Therefore, similarly to the first embodiment, it is not necessary to form a high-concentration guard region as in the conventional case, and the element area can be reduced.
Further, in this embodiment, since the second-layer drain electrode 221 is arranged on the first-layer source electrode 211, the drain electrode 221 can be drawn out in any direction, and the wiring can be freely arranged. There is also the advantage that the degree is high.

The present invention is not limited to the above embodiment,
Various modifications are possible. The following are examples of such modifications. (I) In FIGS. 1 and 3, as a MOS semiconductor device, N
Although the MOS 200 has been described as an example, the same operation and effect as in the above embodiment can be obtained even if the MOS 200 is configured by the PMOS. In addition, these NMOS200 or PMOS
May be formed in the well region formed on the semiconductor substrate. (Ii) In the above embodiment, the NMOS 200 has been described as an example. However, the above embodiment may be applied to a CMOS configuration in which NMOS and PMOS are connected in series as in the prior art, or the above may be applied to an LSI having a plurality of NMOSs or PMOSs. Examples may be applied.

[0014]

As described in detail above, according to the first aspect of the invention, since the source electrode is arranged under the drain electrode and across a part of the drain electrode, the lower part of the drain electrode is not provided. Since the inversion layer generated at 1 is not formed at the portion intersecting with the source electrode, the leakage due to the parasitic MOS can be suppressed. Therefore, it is not necessary to form a high-concentration gate region as in the related art, and the element area can be reduced. According to the second invention, since the source electrode is arranged so as to surround the periphery of the drain region, the depletion layer extending from the drain region is suppressed by the potential of the source electrode and its extension is blocked, It is possible to prevent the punch-through phenomenon to the activated transistor. Therefore, it is not necessary to form a high-concentration guard region as in the conventional case, and the element area can be reduced. Furthermore, since the drain electrode is formed on the upper layer of the source electrode, the drain electrode can be drawn out in any direction, and the degree of freedom of wiring is increased.

[Brief description of drawings]

FIG. 1 is a diagram showing a high voltage MOS semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a conventional high breakdown voltage CMOS semiconductor device.

FIG. 3 is a diagram showing a high breakdown voltage MOS semiconductor device according to a second embodiment of the present invention.

[Explanation of symbols]

100 semiconductor substrate 101 field insulating film 102 insulating film 200 NMOS 201 source region 202 drain region 203 gate electrodes 210, 220 first and second contact holes 211 source electrode 221 drain electrode 230 inversion layer 240 depletion layer

Claims (2)

[Claims] 1. A source region and a drain region formed at a predetermined distance on a main surface of a semiconductor substrate of a first conductivity type of first and second conductivity types having opposite polarities, and the source region and the drain. In a MOS semiconductor device comprising a source electrode and a drain electrode respectively drawn from the region, and a gate electrode provided between the source region and the drain region via a gate insulating film, the source electrode is the A MOS semiconductor device, characterized in that the MOS semiconductor device is arranged below the drain electrode and across a part of the drain electrode. 2. The MOS semiconductor device according to claim 1, wherein the source electrode is provided so as to surround the periphery of the drain region.