JPS60245177A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60245177A JPS60245177A JP10102184A JP10102184A JPS60245177A JP S60245177 A JPS60245177 A JP S60245177A JP 10102184 A JP10102184 A JP 10102184A JP 10102184 A JP10102184 A JP 10102184A JP S60245177 A JPS60245177 A JP S60245177A
- Authority
- JP
- Japan
- Prior art keywords
- drain
- current
- region
- type
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 230000005669 field effect Effects 0.000 claims 1
- 230000006866 deterioration Effects 0.000 abstract description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract 1
- 229910052782 aluminium Inorganic materials 0.000 abstract 1
- 230000002265 prevention Effects 0.000 abstract 1
- 239000012535 impurity Substances 0.000 description 4
- 239000000969 carrier Substances 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 230000003321 amplification Effects 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体装置に関し、高インピーダンス入力で
あり、高出力電流が得られ、かつ、素子特性劣化の少な
い新規な構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device, and relates to a novel structure that has a high impedance input, can obtain a high output current, and has little deterioration in device characteristics.
従来例の構成とその問題点
素子の微細化に伴なって発生する問題点の一つにホット
キャリアの問題がある。このホットキャリアは、ドレイ
ン接合近傍の高電界領域で発生し閾値電圧変動、９ｍ劣
化等の問題を引き起こす。Conventional configuration and its problems One of the problems that occur with the miniaturization of elements is the problem of hot carriers. These hot carriers are generated in the high electric field region near the drain junction, causing problems such as threshold voltage fluctuation and 9m degradation.
ドレイン接合近傍の電界を緩和するだめ、ドレイン接合
のチャンネル側にドレインに接したドレインと不純物の
型が同一である低、不純物領域を設けた構造（以下Ｌ
Ｄ Ｄ ［Ｌｉｇｈｔｌｙ ｄｏｐｅｄ ｄｒａｉｎ］
構造と略す）等がとられている。In order to alleviate the electric field near the drain junction, a low impurity region (hereinafter referred to as L
D D [Lightly doped drain]
structure) etc. are taken.
第１図は、従来のＬＤＤ構造を有するＭＯＳＦＥＴの断
面図である。１はｐ型シリコン基板、２はゲート酸化膜
、３はゲート電極、４人はソース領域、４Ｂはドレイン
領域、６は低不純物濃度領域、６はＳｉｎ、、よりなる
サイドウオールである。FIG. 1 is a cross-sectional view of a MOSFET having a conventional LDD structure. 1 is a p-type silicon substrate, 2 is a gate oxide film, 3 is a gate electrode, 4 is a source region, 4B is a drain region, 6 is a low impurity concentration region, and 6 is a sidewall made of Sin.
ドレインのチャンネル側に低不純物濃度領域を設けたこ
とにより、ドレイン接合部の横方向電界が緩和されホッ
トキャリアの発生をおさえることができる。By providing the low impurity concentration region on the channel side of the drain, the lateral electric field at the drain junction is relaxed and the generation of hot carriers can be suppressed.
しかし、構造上チャンネル領域と、ドレイン領域の間に
低不純物濃度領域６が必要となる。また製造上ドレイン
形成のマスクとして、ゲートの両側に、サイドウオール
６を形成する必要がある。However, due to the structure, a low impurity concentration region 6 is required between the channel region and the drain region. Further, in manufacturing, it is necessary to form sidewalls 6 on both sides of the gate as a mask for drain formation.
これらは素子の微細化に反し、素子面積を大きくするこ
ととなる。さらにサイドウオール６を用いるＬＤＤ構造
は、サイドウオール形成の必要条件として、サイドウオ
ール幅の１．５〜２倍以上のゲート電極膜厚を必要とし
、段差等の問題が発生する。These are contrary to miniaturization of the element and increase the area of the element. Furthermore, the LDD structure using the sidewall 6 requires a gate electrode film thickness that is 1.5 to 2 times or more the width of the sidewall as a necessary condition for forming the sidewall, which causes problems such as steps.
発明の目的
本発明は、上記問題点を解決するもので、高インピーダ
ンス入力であるというＭＯＳＦＥＴの特徴を有しながら
、高出力電流が得られ、かつ素子特性劣化の少ない、微
細化可能な半導体装置を提供せんとするものである。OBJECT OF THE INVENTION The present invention solves the above-mentioned problems, and provides a semiconductor device that can be miniaturized, which has the characteristic of MOSFET of high impedance input, can obtain high output current, and has little deterioration of device characteristics. We aim to provide the following.
発明の構成
本発明は、上記目的を達する為、通常のＭＯ８ＦＩＣＴ
のドレイン領域内に、ドレインと導電型の異なる領域を
形成し、たとえばこれをエミッタとし、従来のドレイン
領域をベース、ドレイン・ソースをとり囲む領域をコレ
クタとしたバイポーラトランジスタを形成し、チャネル
電流をベース電流としてドレインのトランジスタに注入
することにより、出力としては、このバイポーラトラン
ジスタのもつ電流増幅率ｈＦｉｌにより増幅された電流
を得るというものである。Structure of the Invention In order to achieve the above object, the present invention uses a conventional MO8FICT.
A region with a conductivity type different from that of the drain is formed in the drain region of the transistor, and a bipolar transistor is formed, for example, with this as the emitter, the conventional drain region as the base, and the region surrounding the drain and source as the collector. By injecting the base current into the drain transistor, the output is a current amplified by the current amplification factor hFil of this bipolar transistor.
実施例の説明 以下、本発明の実施例を図面に従って説明する。Description of examples Embodiments of the present invention will be described below with reference to the drawings.
第２図ａは、本実施例の半導体装置の断面図であるっ２
１はｎ型基板で、２２はｐウェル領域、２３．２４はそ
れぞれソース、ドレイン領域である。２６はドレイン２
４領域中に形成されたｐ型頭域、Ａｌ配線などの導電性
材料２６はソース領域２３とｐウェル領域２２を短絡す
る。電極２７はｐ型頭域に接続されている。２８はゲー
ト電極、２９はゲート酸化膜、３０は酸化膜である。本
実施例に示した構造の等何回路を第２図すに示す。FIG. 2a is a cross-sectional view of the semiconductor device of this example.
1 is an n-type substrate, 22 is a p-well region, and 23 and 24 are source and drain regions, respectively. 26 is drain 2
A conductive material 26 such as a p-type head region and an Al wiring formed in the four regions short-circuits the source region 23 and the p-well region 22. Electrode 27 is connected to the p-type head region. 28 is a gate electrode, 29 is a gate oxide film, and 30 is an oxide film. A similar circuit having the structure shown in this embodiment is shown in FIG.
同図ａに対応する部分には同一の符号が記されている。The same reference numerals are given to the parts corresponding to a in the figure.
ゲート電極２８にソース２３．ドレイン２４からなるＭ
ＯＳＦＥＴにチャンネルが形成される様に電位を与える
と、ソース２３．ドレイン２４間に電流が流れる。この
電流は、ドレイン２４をベースとするバイポーラトラン
ジスタのエミッタ２６、コレクタ２２からなるバイポー
ラトランジスタのベース電流となり、電極２７からはこ
のベース電流（チャネル電流）をバイポーラトランジス
タの電流増幅率（ｈｙｘ ）倍された電流出力が得られ
る。したがってＭＯＳＦＥＴのチャンネル部分を流れる
電流は、得だい出力電流のｈ□分の１ですみ、素子劣化
もそれだけ起こりにくい。さらに、ノース２３．ドレ４
フ２４間の電位差は、ＭＯＳＦＥＴが動作時にはほぼ０
となり、この点からも、素子特性劣化の防止に効果があ
る。本実施例に示した構造では、エミッタ領域２５の形
成には電極２７を接結するためのコンタクト窓を通して
行なうことができるので、新たに、マスクズレに対する
マージンをとる必要がなく、この点でもＬＤＤ構造の様
な従来構造よりも微細化に適している。The source 23. is connected to the gate electrode 28. M consisting of drain 24
When a potential is applied to the OSFET to form a channel, the source 23. A current flows between the drains 24. This current becomes the base current of the bipolar transistor consisting of the emitter 26 and collector 22 of the bipolar transistor with the drain 24 as the base, and from the electrode 27 this base current (channel current) is multiplied by the current amplification factor (hyx) of the bipolar transistor. A current output can be obtained. Therefore, the current flowing through the channel portion of the MOSFET is approximately 1/h□ of the output current, and element deterioration is less likely to occur. Furthermore, North 23. Dre 4
The potential difference between the terminals 24 and 24 is approximately 0 when the MOSFET is in operation.
From this point of view as well, it is effective in preventing deterioration of device characteristics. In the structure shown in this embodiment, since the emitter region 25 can be formed through the contact window for connecting the electrode 27, there is no need to provide a margin for mask misalignment, and in this respect, the LDD structure It is more suitable for miniaturization than conventional structures such as.
発明の詳細
な説明したように、本発明によれば、ＭＯＳトランジス
タの高インピーダンス入力である点と、バイポーラトラ
ンジスタの高出力電流が得られるという長所をかねそな
え、かつ、ＭＯＳ ｌ−ランシロ １、 。DETAILED DESCRIPTION OF THE INVENTION As described in detail, the present invention combines the advantages of a high impedance input of a MOS transistor and the high output current of a bipolar transistor, and is a MOS transistor.
スタのチャンネル内を流れる電流が少なく、またソース
・ドレイン間の電位差も小さいことから素子劣化の少な
いデバイスが得られる。Since the current flowing through the channel of the star is small and the potential difference between the source and drain is also small, a device with less element deterioration can be obtained.
第１図は従来のホット・キャリア効果の軽減を目的とし
だＬＤＤ構造の半導体装置の断面図、第２図（ａ）は本
発明の一実施例の半導体装置の断面図、第２図（ｂ）は
同図（ａ）の等価回路図である。
２３・・・・・・７−ス領域、２４・・・・・・ドレイ
ンとベースをかねる領域、２６・・・・・・エミッタ領
域、２２・・・・・・コレクタとＭＯＳの基板をかねる
領域、２６゜２７・・・・・・配線。FIG. 1 is a sectional view of a conventional semiconductor device with an LDD structure aimed at reducing the hot carrier effect, FIG. 2(a) is a sectional view of a semiconductor device according to an embodiment of the present invention, and FIG. ) is an equivalent circuit diagram of the same figure (a). 23...7-source region, 24... region that serves as drain and base, 26... emitter region, 22... serves as collector and MOS substrate Area, 26°27...Wiring.
Claims (2)
、前記ドレインと異なる導電性の半導体領域が設けられ
、かつこの半導体領域に電極が設けられたことを特徴と
する半導体装置。(1) A semiconductor device characterized in that a semiconductor region having a conductivity different from that of the drain is provided in a drain region of an MO8 field effect transistor, and an electrode is provided in this semiconductor region.
ンジスタの一部を構成することを特徴とする特許請求の
範囲第１項に記載の半導体装置。(2) The semiconductor device according to claim 1, wherein the drain region and the semiconductor region constitute part of a bipolar transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59101021A JPH0612818B2 (en) | 1984-05-18 | 1984-05-18 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59101021A JPH0612818B2 (en) | 1984-05-18 | 1984-05-18 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60245177A true JPS60245177A (en) | 1985-12-04 |
| JPH0612818B2 JPH0612818B2 (en) | 1994-02-16 |
Family
ID=14289542
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59101021A Expired - Lifetime JPH0612818B2 (en) | 1984-05-18 | 1984-05-18 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0612818B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0272754A2 (en) * | 1986-12-22 | 1988-06-29 | Koninklijke Philips Electronics N.V. | Complementary lateral insulated gate rectifiers |
| JPH02101747A (en) * | 1988-10-11 | 1990-04-13 | Toshiba Corp | Semiconductor integrated circuit and manufacture thereof |
-
1984
- 1984-05-18 JP JP59101021A patent/JPH0612818B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0272754A2 (en) * | 1986-12-22 | 1988-06-29 | Koninklijke Philips Electronics N.V. | Complementary lateral insulated gate rectifiers |
| JPH02101747A (en) * | 1988-10-11 | 1990-04-13 | Toshiba Corp | Semiconductor integrated circuit and manufacture thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0612818B2 (en) | 1994-02-16 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |