JPH0612818B2 - Semiconductor device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and to a novel structure which has a high impedance input, a high output current can be obtained, and a deterioration in element characteristics is small.

Configuration of Conventional Example and Its Problems One of the problems that occurs with the miniaturization of elements is the problem of hot carriers. The hot carriers are generated in a high electric field region near the drain junction and cause problems such as threshold voltage fluctuation and gm deterioration. In order to alleviate the electric field near the drain junction, there is a structure (hereinafter abbreviated as LDD [Lightly doped drain] structure) provided on the channel side of the drain junction with a low impurity region having the same impurity type as the drain in contact with the drain. It is taken.

FIG. 1 is a sectional view of a conventional MOS FET having an LDD structure. Reference numeral 1 is a p-type silicon substrate, 2 is a gate oxide film, 3 is a gate electrode, 4A is a source region, 4B is a drain region, 5 is a low impurity concentration region, and 6 is a sidewall made of SiO ₂ . By providing the low impurity concentration region on the channel side of the drain, the lateral electric field at the drain junction can be relaxed and generation of hot carriers can be suppressed.

However, a low impurity concentration region 5 is required between the channel region and the drain region structurally. Further, it is necessary to form the sidewalls 6 on both sides of the gate as a mask for forming the drain in manufacturing. These are against the miniaturization of the device and increase the device area. Furthermore, the LDD structure using the sidewalls 6 requires a gate electric field film thickness of 1.5 to 2 times the sidewall width or more as a necessary condition for forming the sidewalls, which causes a problem such as a step.

An object of the present invention is to solve the above-mentioned problems, and while having the characteristic of a MOSFET having a high impedance input, a high output current can be obtained under the control of the gate voltage, and the element characteristic deterioration is small. An object of the present invention is to provide a semiconductor device that can be miniaturized.

In order to achieve the above-mentioned object, the present invention forms a region having a conductivity type different from that of the drain in the drain region of a normal MOSFET, for example, this is used as an emitter, and the conventional drain region is used as a base and a drain / source is formed. By forming a bipolar transistor with the surrounding region as a collector and injecting a channel current as a base current into the drain transistor, a current amplified by the current amplification factor H _FE of this bipolar transistor is obtained as an output. It is a thing. Further, the source region and the substrate region in contact with the source region are short-circuited by the same electrode provided on the surface in contact with them.

Description of Embodiments Embodiments of the present invention will be described below with reference to the drawings. FIG. 2a is a sectional view of the semiconductor device of this embodiment. 21 is n
The mold substrate 22 is a p-well region, and 23 and 24 are source and drain regions, respectively. 25 is a conductive material such as a p-type region formed in the drain 24 region and Al wiring 26
Short-circuits the source region 23 and the p-well region 22. The electrode 27 is connected to the p-type region. 28 is a gate electrode,
Reference numeral 29 is a gate oxide film, and 30 is an oxide film. An equivalent circuit of the structure shown in this embodiment is shown in FIG. 2b. The same reference numerals are given to the portions corresponding to FIG. Gate electrode 2
When a potential is applied to 8 so that a channel is formed in the MOSFET composed of the source 23 and the drain 24, the source 2
3, a current flows between the drains 24. This current becomes the base current of the bipolar transistor including the emitter 25 and collector 22 of the bipolar transistor whose base is the drain 24, and this base current (channel current) is multiplied by the current amplification factor (h _FE ) of the bipolar transistor from the electrode 27. The obtained current output is obtained. Therefore M
The current flowing through the channel part of the OSFET is 1 / h _{FE of the} desired output current, and element deterioration is less likely to occur. Further, the potential difference between the source 23 and the drain 24 becomes almost 0 when the MOSFET is in operation, which is also effective in preventing the deterioration of the element characteristics. Further, since the source region 23 and the p-well region 22 in contact with the source region are short-circuited by the same electrode 26 provided on the surface in contact with each other, connection can be made with the same contact window, and the source is different from the source. It is more effective in miniaturization compared to the case where the substrate potential is taken by another one, and there is little change in the substrate potential with respect to the source potential especially in the vicinity of the source diffusion layer, so that the latch-up state does not occur and the gate voltage is lowered. And it is possible to return to the original state. That is, the current can be controlled by the gate voltage. In the structure shown in this embodiment,
Since the emitter region 25 can be formed through a contact window for connecting the electrode 27, it is not necessary to newly provide a margin for mask misalignment, and also in this respect, the structure can be made finer than the conventional structure such as the LDD structure. Suitable for

EFFECTS OF THE INVENTION As described above, according to the present invention, the high impedance input of the MOS transistor and the advantage that a high output current of the bipolar transistor can be obtained are obtained, and the current flows in the channel of the MOS transistor. Since the current is small and the potential difference between the source and drain is small, a device with less element deterioration can be obtained. Further, since the source region and the substrate region in contact with this source region are short-circuited by the same electrode provided on the surface where they are in contact, connection can be made with the same contact window, and the substrate potential at a position different from the source It is more effective in miniaturization compared to the case of taking the above, and there is little change in the substrate potential with respect to the source potential especially in the vicinity of the source diffusion layer. It is possible to

[Brief description of drawings]

FIG. 1 is a sectional view of a conventional semiconductor device having an LDD structure for reducing the hot carrier effect, FIG. 2 (a) is a sectional view of a semiconductor device according to an embodiment of the present invention, and FIG. 2 (b). ) Is the same figure
It is an equivalent circuit diagram of (a). 23 ... Source region, 24 ... Region that also serves as drain and base, 25 ... Emitter region, 22 ... Collector and M
Area that doubles as the OS substrate, 26, 27 ... Wiring.

Claims (1)

[Claims] 1. A drain region of a MOS field effect transistor is provided with a conductive semiconductor region different from the drain region, and a first electrode is connected to the semiconductor region, and the source region and the source region are in contact with each other. A semiconductor device characterized by being short-circuited with a substrate region by a second electrode provided on the surface in contact with these.