JPS6212665B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to semiconductor integrated circuit devices, particularly lateral bipolar transistors and static induction transistors (hereinafter referred to as SIT).
Static Induction Semiconductor Logic Circuit Device (Static Induction Transistor Logic)
It's called SITL. ).

The above-mentioned SITL, which is the object of the present invention, is an integrated injection logic (hereinafter referred to as I ² L).
The reverse-acting bipolar transistor in is replaced with an enhancement junction type SIT,
The principle is Digest of Technical Papers The
8th Confevence on Solid State Devices'76
(Tokyo) A-2-6, introduced in PP53-54. FIG. 1 is a general equivalent circuit diagram of the basic gate. In the figure, 101 is a PNP transistor, 102 is an N-channel junction type SIT, and 1 is a
PNP transistor 101 which becomes the power supply terminal of SITL
2 is the emitter terminal of the PNP transistor 10.
1 collector and N-channel junction type SIT102
3 is the input terminal connected to the gate of
a ground terminal connected to the base of PNP transistor 101 and the source of N-channel SIT 102;
is an output terminal connected to the drain of the N-channel junction type SIT 102. Note that the PNP transistor 101 is connected to the constant current source for gate bias of the N-channel junction type SIT and its preceding stage.
Operates as SITL load, N-channel junction type
SIT102 operates as an inverter.

FIG. 2a is a plan view of the basic gate portion of the SITL structure, and FIG. 2b is a sectional view of FIG. 2a taken along line bb. In the figure, reference numeral 11 denotes a low resistivity N-type semiconductor substrate which is a starting material, and 12 denotes high resistivity N-type semiconductor regions 13 and 14 formed by epitaxial growth on one main surface of this substrate 11, respectively. These are P-type semiconductor regions formed in predetermined portions of the N-type semiconductor region 12 in close proximity to each other by a selective diffusion method, among which the P-type semiconductor region 1
4 is formed in a ring shape so as to laterally surround a part of the N-type semiconductor region 12, and as a result, an opening A exists where the N-type semiconductor region 12 is exposed. Reference numeral 15 denotes a low resistivity N-type semiconductor region formed by diffusing phosphorus or the like into a predetermined portion of the surface region of the N-type semiconductor region 12 in the opening A, and this N-type semiconductor region 15 is formed shallower than the P-type semiconductor region 14, and desirably is formed so as not to contact the P-type semiconductor region 14. like this
In the SITL configuration, the above-described lateral PNP transistor 101 is composed of a P-type semiconductor region 13 serving as an emitter region, an N-type semiconductor region 12 serving as a base region, and a P-type semiconductor region 14 serving as a collector region. Further, the N-channel junction type SIT includes an N-type semiconductor region 11 that becomes a source region, a portion 12' below the N-type semiconductor region 15 of the N-type semiconductor region 12 that becomes a channel region, and a P-type semiconductor region 14 that becomes a gate region.
and an N-type semiconductor region 15 which becomes a drain region. Here, the impurity concentration and channel width of the N-type semiconductor region portion 12' which becomes the channel region of the SIT 102 are such that the potential of the gate terminal 2 is
On the other hand, when the potential is zero or very small, the depletion layer extends widely into the channel portion 12' of the N-type semiconductor region, and the channel is sufficiently pinched off.On the other hand, when the gate potential is positive (approximately 0.7V), the depletion layer It is set so that it becomes short to form a channel, that is, so that the source 3 and drain 4 are in a conductive state. Therefore, in the SITL having such a configuration, when the input terminal 2 is in an open state, the N-type semiconductor region 1 is connected from the P-type semiconductor region 13, which is the emitter region of the PNP transistor 101.
By the holes injected into 2, the PN junction consisting of the P-type semiconductor region 14 and the N-type semiconductor region 12, which is the collector region and also the gate region of the N-channel junction type SIT 102, is biased in the forward direction. Therefore, the depletion layer formed in the N-type semiconductor region 12 becomes short, a channel is formed, the source 3 and the drain 4 become conductive, and the potential of the output terminal connected to the drain 4 decreases. . Since this output terminal is connected to the input terminal of the next-stage SITL, that is, the gate of the next-stage N-channel junction type SIT (not shown), the gate potential thereof decreases. As a result, the N-channel junction type SIT in the next stage becomes in a pinch-off state, and the output terminal of the next stage rises to a potential determined by the load. That is, SITL
It can be seen that the circuit has an inverted logic circuit configuration.

As described above, since the SITL uses the PNP transistor 101 as a constant current source and load, it has a configuration in which no resistance is used as a power source or load. In addition, the PNP transistor 101
Since the N-type semiconductor substrate 11, which is usually a common area of each, is grounded so that the base is grounded and the N-channel junction type SIT 102 is grounded, there is no need to separate the circuit elements from each other. For this reason, SITL has a very simple structure,
Conventional general bipolar configuration or MOSFET
The integration density is much higher than that of the semiconductor integrated circuit of this structure.

However, in the conventional SITL as described above, the channel region of the SIT is surrounded by the P-type semiconductor region 14 which is the gate region, so the gate area is large and the gate-source and gate-source regions are surrounded by the P-type semiconductor region 14.
The drain junction capacitance is large, and the SIT gate and
Because the sources are sequentially biased, there is a problem in that minority carriers accumulate in the N-type semiconductor region 12, thereby limiting the switching speed.

The present invention was made in order to solve the problems of the conventional SITL as described above.
The aim is to provide an improved SITL that takes advantage of the advantages of SITL, significantly improves the switching speed, and enables high-speed operation.

An embodiment of the present invention will be described in detail below with reference to FIG. Figure 3 a is a plan view, and Figure 3 b is the plan view.
-b sectional view, and figure c is the cc sectional view. In FIG. 3, the same symbols as in FIG. 2 indicate the same or corresponding parts,
The redundant explanation will be omitted, and the points that are essentially different from the conventional one shown in FIG. 2 will be explained.

First, in this example, the N-channel junction type
P where the channel region of SIT102 is the gate region
type semiconductor region 14 and is surrounded by an insulator 17 made of oxide, and a P type semiconductor region 16 which becomes part of the gate region is located in a part of the channel region directly under the N type semiconductor region 15 which is the drain region.
is formed so as to be connected to the P-type semiconductor region 14. Here, the channel region is the N-type semiconductor region 12 surrounded by the P-type semiconductor regions 14 and 16 and the insulator 17 as described above, but in this embodiment, the channel region is divided into two by the P-type semiconductor region 16. It is divided into And again P
The shaped semiconductor regions 14 and 16 serve as gate regions, and the conditions for controlling the SIT channel by the gates are as follows. First, when the gate potential is zero volts or a minute potential, the depletion layer extends from the P-type semiconductor region 16 toward the insulator 17 and reaches the insulator 17, and the entire channel regions 12' and 12'' are covered with the depletion layer. , so that the N-channel junction type SIT is in the cutoff state, and on the other hand, when the gate potential is positive, the P-type semiconductor region 16
The distance between the P-type semiconductor region 16 and the insulator 17, the concentration of the N-type semiconductor region 12, etc. are adjusted so that the depletion layer extending from the P-type semiconductor region 16 and the insulator 17 becomes short, a channel is formed, and the N-channel junction type SIT becomes conductive. Set.

The structure of an SITL using an SIT with one drain has been described above as an embodiment of the present invention.
In addition to SITL using a so-called multi-drain structure SIT with two or more drains,
It can be applied more effectively. In such a SITL according to the present invention, the gate region 1
Since the area of 4 and 16 can be significantly reduced, each junction capacitance can be significantly reduced.
Furthermore, since most of the channel and gate regions 14 and 16 are surrounded by the oxide 17, minority carriers injected from the gate region into the N-type semiconductor region 12 are significantly reduced. Therefore, the switching speed of SITL is greatly improved and high-speed operation is possible.
You can get SITL.

The embodiments of the structure of the SITL according to the present invention have been described above, but a person skilled in the art can easily create a SITL with such a structure by the method described above.

First, an impurity concentration is increased on one main surface of the low resistivity N-type semiconductor region 11 by epitaxial growth.
After forming an N-type semiconductor layer 12 with a thickness of about 10 ¹³ to 10 ¹⁴ /cm ³ and then removing a predetermined portion of the N-type semiconductor region 12 by etching, an insulator 17 such as SiO ₂ is filled by a burying method or a selective oxidation method. Form. Then N
A P-type semiconductor region 13 is formed in a predetermined portion of the P-type semiconductor region 12.
and 14 are formed by a diffusion method or the like.

At this time, the channel portion is surrounded by the P-type semiconductor region 14 and the insulator 17, and at the same time, one side of the P-type semiconductor region 14 is formed to face the P-type semiconductor region 13 with the N-type semiconductor region 12 in between. Next, a P-type semiconductor region 16 is formed in a predetermined portion of the channel region by high-energy ion implantation or the like so that one end thereof is connected to the P-type semiconductor region 14, and then an N-type semiconductor region 15, which is a drain region, is formed. Formed by a diffusion method or the like. Here, it is desirable that the P-type semiconductor region 16 be formed at a predetermined interval so as not to be in direct contact with the N-type semiconductor regions 15 and 11. After that, the process is similar to the conventional one explained in FIG.

As explained above, the present invention does not surround the channel region only with the gate region as in the conventional case, but surrounds the channel region with the gate region and an insulating material, and forms a band-shaped gate region directly under the drain region.
Furthermore, by surrounding part of the gate region with an insulating material, the effect of reducing each junction capacitance, accumulated carriers, etc. and improving high frequency characteristics is not limited to the above-mentioned SITL. , which can be implemented as the SIT itself, and can also be applied to general depletion junction field effect transistors in which a conductive path as a channel is formed when the gate voltage is zero potential or minute potential. It is.

Further, in the above embodiment, an SITL having a combination structure of a PNP transistor and an N-channel type SIT has been described, but it is clear that an SITL having a combination structure of an NPN transistor and a P-channel type SIT can also be implemented.

Further, in the above embodiment, an example was explained in which the source region was formed by the semiconductor substrate 11, but it is also possible to use a P-type semiconductor as the semiconductor substrate and form a source region partially made of an N ⁺ type semiconductor on the surface of the P-type semiconductor. , a large number of
SITL is formed without mutual isolation,
A semiconductor device other than the SITL may be isolated and integrated on another portion of the surface of the substrate.

[Brief explanation of the drawing]

Figure 1 is the equivalent circuit diagram of SITL, Figure 2 is the conventional
FIG. 3 is a plan view and a sectional view showing the structure of the SITL as an embodiment of the present invention. 1... Emitter terminal, 2... Input terminal, 3...
Ground terminal (source), 4... Output terminal (drain), 11... N-type semiconductor substrate, 12... N-type semiconductor region, 12', 12''... Channel region, 13
... P-type semiconductor region, 14 ... P-type semiconductor region,
15...N-type semiconductor region, 16...P-type semiconductor region, 17...Insulator, 101...PNP transistor, 102...N-channel junction type SIT.

Claims (1)

[Claims] 1 a semiconductor substrate having a first conductivity type; a first semiconductor region having a first conductivity type formed on the semiconductor substrate and having a lower impurity concentration than the semiconductor substrate;
second and third semiconductor regions which are formed on the main surface of the first semiconductor region to face each other at a predetermined interval and both have a second conductivity type; a first conductivity type formed on the main surface of the first semiconductor region on the opposite side, shallower than the third semiconductor region, spaced apart from the third semiconductor region, and having a higher impurity concentration than the first semiconductor region. an insulator region formed to surround the fourth semiconductor region, spaced apart from the fourth semiconductor region, in contact with the third semiconductor region, and in contact with the semiconductor substrate; It is provided within the first semiconductor region so as to be spaced apart from the fourth semiconductor region and below the fourth semiconductor region, with a part facing the fourth semiconductor region, and one end including the part is provided in the first semiconductor region. A semiconductor device comprising: a fifth semiconductor region having a second conductivity type, the fifth semiconductor region being in contact with the third semiconductor region, and the other end of the fifth semiconductor region being in contact with the insulator region facing the third semiconductor region.