JPS5910592B2 - Semiconductor device and its manufacturing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, particularly a static induction transistor (hereinafter referred to as SIT).

), and even logic using static induction transistors (
Hereinafter referred to as SITL. ) is related to semiconductor integrated circuits based on In order to cope with the increasing density and integration of semiconductor integrated circuits, the MOSFET method, which requires no separation between elements, requires a small number of steps, and is easy to manufacture, has been mainly used.

However, in the MOSFET system, control becomes considerably difficult as the channel length is shortened, but in the bipolar system, control is based on the base width, so the MOSFET
It has the advantage of being easier to control than the MOSF
It can be faster than the ET method. Therefore, as long as problems such as the need for isolation between elements and the large number of steps are solved, it will be put into practical use in a wider range of areas as high-density, highly integrated semiconductor integrated circuits that can be used at high speeds and high frequencies. It is possible and a lot of research has been done.

One of them is IntegratedInjectiOnLOgic, which controls minority carriers using a composite structure of vertical Npn transistors and horizontal Pnp transistors.
(IIL) was developed, and StaticInductiOnTransistOr which controls a large number of carriers was developed.
(SIT) and a lateral Pnp transistor.
ticIn-DuctiOnTransistOrLO
gic (SITL) has been proposed.

FIG. 1 shows the basic gate structure of the above-mentioned IIL. In the figure, 11 is a substrate made of a cage-shaped semiconductor that becomes the emitter of a Pnp transistor, and 12 is a substrate formed by an epitaxial method and is the base of the Pnp transistor and the Npn An n-type region that operates as the emitter of the transistor, 13 is the collector of the Pnp transistor and the Np
a p-type region, 1, which acts as the base of an n-transistor;
4 is a cage-shaped region that operates as a collector of an Npn transistor, 15 is an emitter of a Pnp transistor, that is, a p-type region that operates as an injector, B is an input terminal, Cl and C2 are multi-collector output terminals, I is an injector terminal, 16 is an insulating film, and 17 is an aluminum electrode.

Further, FIG. 2 shows the above-mentioned SITL, in which 21 is an n+ type substrate that operates as a source of the SIT, and 22 is a PnP substrate formed by an epitaxial method.
an n-type region that operates as the base of the transistor and a channel of the SIT; 23 a p-type region that operates as the collector of the Pnp transistor and the gate of the SIT;
24 is an n+ type region that operates as a drain of SIT;
25 is the emitter of the Pnp transistor, that is, a p-type region that operates as an injector, G is the input terminal, and Dl
, D, are multi-drain output terminals, and I is an injector terminal.

Note that the three regions indicated as 23 actually have an integral structure so as to surround the drain 24. Further, in the figure, 28 is an insulating film, and 29 is an aluminum electrode. Here, when comparing FIG. 1 and FIG. 2, the area 15-12-13 in FIG. 1 and the area 25-13 in FIG.
All of 22 and 23 constitute lateral Pnp transistors and function as constant current sources. The different part is the switching transistor, and as mentioned above, the SITL shown in FIG. 2 uses a reverse operation SIT, unlike the Npn transistor. That is, the cage substrate 21 is the source, the region 22 is the channel, the region 24 is the drain, and the region 24
The p+ type region 23 surrounding the gate is the gate. The impurity density of the n-type region 22, which operates as a channel portion, is set to be as low as 1013 to 1014c7n-3, so that the channel length can be easily controlled over a wide range. Furthermore, the impurity density in regions 23 and 25 is 1018C.
The concentration is as high as WL-3, and the n-region 22 has a low concentration. Therefore, even if the gate potential is 0 volts, the depletion layer 26 in the channel is on both sides as shown by the dotted line in FIG. , the channel is in a pinch-off state, a high potential barrier is created within the channel, and therefore no drain current flows if the drain voltage is relatively low. On the other hand, as a positive voltage is applied to the gate, the potential barrier decreases. When the gate voltage reaches 0.6 to 0.7 volts, the junction between the P+ gate and the n- channel becomes forward biased.
Electrons flow between the source and drain. Therefore, SIT
In L, on-off is performed in the above two states. Therefore, as in the case of IL, the load of the switching transistor can be used as a Pnp constant current source in the subsequent stage, so that a logic circuit can be constructed without using any resistance for either the power supply or the load. Also, Npn transistor, n
Channel static induction transistors are operated with their emitters grounded and sources grounded, and PNP transistors are operated with their bases grounded, so they can be grounded using a common substrate, eliminating the need for a separation process between elements. As a result, the degree of integration is much improved compared to conventional bipolar and MOSFET systems. On the other hand, IIL. and SITL
Comparing the capacitances of the switching transistors, we find that in the former case, the emitter-base capacitance is a p+cage junction capacitance, whereas in the latter, the source-gate capacitance is a p+n junction, and the dimensions of each region are the same. In terms of capacity, SITL has a smaller capacity.

Furthermore, when comparing the collector-base junction of IIL and the drain-gate junction of SITL, the latter has a smaller junction area and therefore has a smaller capacitance. In this way, when comparing the two with basic gate structures of similar dimensions as a whole,
The total capacity of the SITL is approximately 1/10 of the total capacity of the IIL, allowing higher speed operation. However, even in such SITL, problems still remain.

That is, the channel width is limited by the gate 23 formed so as to surround the drain 24, so the drain region 24 cannot be made large, and if the drain 24 is formed deep, the junction area with the gate 23 is limited. becomes larger, the capacity increases, and high-speed operation becomes impossible. Furthermore, if the drain 24 is formed shallowly, the distance between the source and the drain becomes large, which has the disadvantage that the drain resistance when conducting becomes large. The present invention is applicable to the conventional SIT as described above.
This was done in order to solve the problems in the drain region, increasing the cross-sectional area of the channel without increasing the capacitance, thereby reducing the resistance between the drain and source and increasing the speed. The lower surface of the drain region is formed in a concave or convex shape, and the upper surface of the source region is formed in a convex or concave shape so as to increase the effective cross-sectional area of the channel. It is characterized by reducing drain resistance. FIG. 3 is a sectional view showing one embodiment of the SITL of the present invention, and in the same figure, 22, 23, 24, 2592
8 and 29 have the same configuration as in FIG.

Further, 27 is a p-type semiconductor substrate, 30 consisting of 30a, 30b, and 30c is a source region 5 having a convex upper surface, and 31 consisting of 31a and 31b is a source region 5 having a concave lower surface. The drain region is 30,
31 are formed in a concave and convex shape facing each other so that the thickness of the channel portion sandwiched therebetween is equal at any position. Such an SITL according to the present invention can be produced by a method as shown in FIG. 4 or FIG. 5. First, the method shown in FIG. 4 will be explained.

First, as shown in FIG. 2A, an n-type impurity is introduced onto the main surface of the p-type substrate 27 by diffusion or ion implantation to form a region 30a that will become a source, and a thin epitaxial layer is formed on the region 30a. 22a is formed, and an insulating film 28 serving as a mask layer is used on the insulating film 28 to diffuse n-type impurities into a portion corresponding to the region below where the drain of the n-channel SIT is to be formed, thereby connecting it to the previously formed region 30a. A region 30b is formed, a source region 30 with a protrusion is formed, the mask 28 is removed, and then, as shown in FIG. Then, the insulating film mask 28 is formed again.

Next, as shown in figure c, n-type impurities are introduced by diffusion or ion implantation to form a protruding source region 30c, and then the insulating film 28 is removed, and the epitaxial layer is again formed as shown in figure d. A layer 22c is additionally formed.
After forming the region 22 in this way, an injector region 25 and a gate region 23 are further formed, and then, as shown in FIG. At this time, in the present invention, it is necessary to form the drain into a concave shape, so as shown in FIG. A thick insulating film is formed in the area where impurities are not introduced, and an even thicker insulating film is formed in the areas where impurities are not introduced.If n-type impurities are then introduced by ion implantation, a concave shape as shown in Figure f is formed. A drain region 31 can be formed.

After that, as shown in FIG.
8 is grown, a contact hole is made in it, and an Al electrode 29 is formed to complete the SITL.

Next, another embodiment for obtaining such a semiconductor device of the present invention will be described with reference to FIG.

As shown in figure a, a source region 30a is first formed on the entire surface of the p-type semiconductor substrate 27, and then a well-known photolithography technique is used to form the insulating film 28 as a mask in a portion directly below the drain. As shown in FIG.
', and further, an n+ region 30♂ is formed by diffusion or ion implantation in a portion where a convex portion is to be formed. At this time, it should be noted that since this embodiment utilizes the difference in the lifting of the impurities in the regions 30b' and 30c' in the next epitaxial process, the ease with which the impurities are lifted is This means that it is necessary to differentiate between The ease with which it floats varies depending on the substance, and also on the concentration of impurities. In this embodiment, antimony (Sb) is used for the region 30a, and Sb is also used for the region 30b'. Therefore, the impurity concentration of the region 30b' is made sufficiently higher than that of the region 30a, and the impurity concentration of the region 30c is made sufficiently higher than that of the region 30a.
For ', MP) is used because it has a larger lifting effect than Sb. Furthermore, at this time, a difference in diffusion coefficients of impurities may be utilized. Next, as shown in FIG. 4D, a region 22 is formed by an epitaxial method, and regions 30b and 30c are formed using the floating impurities described above to complete the region 30, and then a region that will become an injector and a gate is formed. 25 and 23 are formed. The subsequent formation of the region 31 that will become the drain may be performed by the method described in the previous embodiment, or by simultaneous diffusion of impurities having different diffusion coefficients.
The method shown in Figures D, e, and f may also be used.

That is, as shown in FIG. d, a mask 28 made of an insulating material
Using a method, first a deep portion 31a is formed, then a mask 28 made of an insulating material is formed as shown in FIG. Good too. As is clear from the above description, in the SITL of the present invention obtained as described above, the distance between the source and drain is shortened without bringing the gate into contact with the source and drain, and the gate width, that is, the channel width is increased. Since it is possible to keep the junction capacitance small, the resistance between the drain and source can be reduced, and the range in which the conduction current can be varied can be expanded.
Therefore, it is possible to achieve higher speeds in the large current region and higher speeds and higher performance in the smaller current region.

In the above embodiment, a case was explained in which an n-channel SIT and a Pnp transistor were used, but the present invention is not limited to that example.
The present invention can be applied to the case of using a transistor, and can also be applied to the SIT itself.

Furthermore, in the present invention, it goes without saying that the drain region may be made convex and the source region may be made concave.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of a conventional IIL, and Figure 2 is a cross-sectional view of a conventional IIL.
FIG. 3 is a cross-sectional view showing an embodiment of the SITL of the present invention, and FIGS. FIG. 3 is a cross-sectional view of the SITL in each step of FIG. 11...Cage-shaped semiconductor substrate, 12...Epitaxial layer (n type region), 13...P type region, 14...N+ type region, 15...p
Shape area, 16...Insulator, 17...A
l electrode, 21... cage-shaped semiconductor substrate, 22...
... n-type region, 23 ... p-type region, 25.
... p-type region, 26 ... depletion layer, 27.
...P-type semiconductor substrate, 28...Insulator mask, 29...Al electrode, 30...Source region, 30a, 30a' material with small elevation Source regions formed of 30b, 30b'... Source regions formed of a material with large upheaval, 30cζ...
. . . Source region, 31a, 31b . . . Drain region, B . . .
...Input terminal, C,,C2...Multi-collector output terminal, Dl, D2...Multi-drain output terminal, I...Injector.

Claims (1)

[Scope of Claims] 1. A first region made of a semiconductor of a first conductivity type, one main surface of which is formed in a convex or concave shape, and a first region formed on the one main surface, and the first region 1st with higher resistivity
a second region made of a semiconductor of a conductivity type; and a third region made of a semiconductor of a second conductivity type formed on the upper surface of the second region so as to surround a portion of the second region to be a channel.
and a second region above the channel portion, the semiconductor is made of a first conductivity type semiconductor having a lower specific resistance than the second region, and the lower surface thereof is one main surface of the first region. and a fourth region formed in a concave or convex shape opposite to the first region, the first region is a source, the second region is a channel, the third region is a gate, and the fourth region is a drain. semiconductor device. 2 Adjacent to the third region, a fifth region of the second conductivity type is added to the upper surface of the second region, and this region is used as an emitter, and the third region and the fifth region of the second region 2. The semiconductor device according to claim 1, wherein the portion between the two regions serves as a base, and the third region serves as a collector. 3. The semiconductor device according to claim 1, wherein the first region is formed on a surface portion of a second conductivity type semiconductor substrate. 4 A first region made of a semiconductor of a first conductivity type and having one main surface formed in a convex or concave shape, and a second region formed on the one main surface and having a higher specific resistance than the first region. 1
a second region made of a semiconductor of a conductivity type; and a third region made of a semiconductor of a second conductivity type formed on the upper surface of the second region so as to surround a portion of the second region to be a channel.
and a second region above the channel portion, the semiconductor is made of a first conductivity type semiconductor having a lower specific resistance than the second region, and the lower surface thereof is one main surface of the first region. and a fourth region formed in a concave or convex shape opposite to the semiconductor device, wherein the first region is a source, the second region is a channel, the third region is a gate, and the fourth region is a drain. In the manufacturing method, when forming the first region, first a part of the second region is formed, then the second region is formed thinly, and then impurities are partially introduced, and such a process is performed. A method for manufacturing a semiconductor device, comprising repeating the steps at least twice to form a convex or concave first region. 5 A first region made of a semiconductor of a first conductivity type and having one main surface formed in a convex or concave shape, and a second region formed on the one main surface and having a higher specific resistance than the first region. 1
a second region made of a semiconductor of a conductivity type; and a third region made of a semiconductor of a second conductivity type formed on the upper surface of the second region so as to surround a portion of the second region to be a channel.
and a second region above the channel portion, the semiconductor is made of a first conductivity type semiconductor having a lower specific resistance than the second region, and the lower surface thereof is one main surface of the first region. and a fourth region formed in a concave or convex shape opposite to the semiconductor device, wherein the first region is a source, the second region is a channel, the third region is a gate, and the fourth region is a drain. , at least three semiconductor regions each containing impurities of the first conductivity type and having different areas are formed in an overlapping manner, and then a second region is formed on the surface thereof, and the three semiconductor regions are A method of forming a first region by floating impurities in the three semiconductor regions into the second region, wherein the heights of the impurities in the three semiconductor regions are set to be different from each other. death,
A method of manufacturing a semiconductor device, comprising forming a first region having a convex or concave shape. 6 A first region made of a semiconductor of a first conductivity type and having one main surface formed in a convex or concave shape, and a second region formed on the one main surface and having a higher specific resistance than the first region. 1
a second region made of a semiconductor of a conductivity type; and a third region made of a semiconductor of a second conductivity type formed on the upper surface of the second region so as to surround a portion of the second region to be a channel.
and a second region above the channel portion, the semiconductor is made of a first conductivity type semiconductor having a lower specific resistance than the second region, and the lower surface thereof is one main surface of the first region. and a fourth region formed in a concave or convex shape opposite to the semiconductor, wherein the first region is a source, the second region is a channel, the third region is a gate, and the fourth region is a drain, The fourth region is formed by ion implantation of impurities, and at that time, as a mask for the ion implantation,
A semiconductor device characterized in that a fourth region having a concave or convex lower surface is formed by using a mask having a highly transparent portion and a weakly transparent portion in the portion through which ions are transmitted. manufacturing method.