JPH11338401A - Driving circuit of matrix type display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a driving circuit of a matrix type display device, which can be formed in a small size as a whole, and by which the effect due to fluctuation of a driving power source voltage occurring while a matrix type display device is driven is reduced to the utmost. SOLUTION: Positive-side and negative-side driving power sources are supplied from positive-side and negative-side power source supply circuits 14, 15 to a row-side voltage applying circuit 13, and the row-side voltage applying circuit 13 and the positive-side and negative-side power source supply circuits 14, 15 are formed on SOI board 31 in the electrically separated state, respectively, and also arranged in the closed state, respectively, to thereby enable to shorten drawing-around of a power source wire for the connection between each circuit. Therefore, even if an electric potential of the power source wire is fluctuated largely, the adverse effect, such as a cross talk and the like, are not exerted on other control signal wires or the like, and a row-side drive circuit 12 can be formed in a small size as a whole.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matrix type display in which display cells formed at intersections between the scanning electrodes and data electrodes of a matrix type display device are displayed by applying a driving voltage to each of the electrodes. The present invention relates to a driving circuit of a device.

[0002]

2. Description of the Related Art For example, EL (Electoro Luminescence)
In a matrix type display device such as a panel, a display cell is formed at each intersection of a scanning electrode and a data electrode, and a display cell is formed by applying a driving voltage having different polarities to the scanning electrode and the data electrode. Is displayed. When the display cell once in the display state is returned to the non-display state, one or both of the electrodes are connected to the ground to discharge the electric charge charged in the display cell.

Since the saturation luminance voltage for bringing the display cells of the EL panel into a display state is generally a high voltage exceeding 200 V, it is necessary to apply the driving voltages to the respective electrodes with the polarities of the driving voltages reversed as described above. Thus, the potential shared by each is reduced. In addition, in order to stabilize the characteristics of the EL panel, the polarity of each applied voltage is controlled so as to be inverted for each frame for switching the display screen.

As a method of driving such a matrix type display device, for example, Japanese Patent Publication No. Hei 7-31483 and Japanese Patent Publication No. Hei 7-95225, and Japanese Patent Laid-Open Publication No. Hei 8-137.
No. 435 has been proposed.

[0005]

In these prior arts, as shown in FIG. 9, a push-pull type voltage applying circuit 1 is used.
A drive power supply is applied to each electrode via the. However, since the driving power supply voltage is relatively high as described above, it is considered that the power supply circuits 2 and 3 for supplying the driving power need to be configured outside the IC in which the voltage applying circuit 1 is configured. .

Therefore, during driving of the EL panel, the potentials of the power supply lines 4 and 4 connecting them are several tens of volts to hundreds of tens of
Therefore, the control signal line on the circuit board may have adverse effects such as crosstalk. There is also a problem that the overall configuration becomes large.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to minimize the influence of fluctuations in the drive power supply voltage that occurs during driving of a matrix type display device, and to make the entire device compact. It is another object of the present invention to provide a driving circuit of a matrix type display device which can perform the above.

[0008]

According to the driving circuit for a matrix type display device according to the first to third aspects, a push-pull type for applying a driving voltage to a scanning electrode (11) of a matrix type display device (10). The scanning-side voltage application circuit (13) is supplied with positive-side and negative-side drive power from the positive-side and negative-side power supply circuits (14, 15). The negative power supply circuit is formed on the semiconductor substrate (31) in a state of being electrically separated from each other (Claim 1), and is formed and arranged on the semiconductor substrate in a state of being close to each other (Claim 1). 2). Then, specifically, the semiconductor substrate is constituted by an SOI substrate (claim 3).

In the matrix type display device (10), since the driving voltage is applied to all the data electrodes (16) at the same time, the driving voltage on the data electrode (16) side is set relatively low. It may be advantageous to set the drive voltage on the scan electrode (11) side relatively high.

In such a case, the scanning side voltage application circuit (1
3) Even if the potential of the power supply line connecting between the positive and negative power supply circuits (14, 15) fluctuates greatly, the same semiconductor substrate is kept electrically isolated from each other. Since it is formed on the (31) (claims 1 and 3), the length of the power supply line can be shortened, and there is no adverse effect such as crosstalk on other control signal lines and the like, and the whole is reduced in size. Can be configured. Further, by forming and arranging the circuits so as to be close to each other, the effect can be enhanced more than (claim 2).

According to the driving circuit of the matrix type display device of the present invention, the scanning-side voltage application circuit (13) and the positive and negative power supply circuits (14, 15) are replaced by LDMOS transistors (18, 19, 22). , 23, 26, 27), the on-resistance can be reduced and the current driving capability can be improved as compared with the high-voltage MOS transistor having the normal configuration, so that the whole can be further reduced in size.

According to the driving circuit of the matrix type display device of the fifth or sixth aspect, the scanning side voltage applying circuit (13)
The gates of the P-channel and N-channel MOS transistors (18, 19) constituting a) are driven by gate drive circuits (53, 55), and their drive timing
That is, the timing at which the divided voltage is output from the output terminal of the voltage dividing circuit (20, 21) to each gate is determined by the timing of the MOS transistor (5,
2, 54) (claim 5).

Therefore, each scanning side voltage applying circuit (13a)
It is possible to individually control the application timing of the drive voltage from the controller. The positive and negative power supply circuits (1
4, 15) supply the positive and negative power supplies to the plurality of scanning voltage applying circuits (13a) (claim 6).
By sharing the positive-side and negative-side power supply circuits (14, 15), the overall configuration can be made even smaller.

According to the driving circuit of the matrix type display device of the seventh or eighth aspect, the matrix type display device (1
The push-pull data-side voltage application circuit (58) for applying a drive voltage to the data electrode (16) of (0) has a positive-side and a negative-side drive from the positive-side and negative-side power supply circuits (59, 60). When power is supplied, the data-side voltage application circuit (58) and the positive-side and negative-side power supply circuits (5
9, 60) are formed on the semiconductor substrate (31) in a state of being electrically separated from each other (claim 7).

That is, by making the circuit on the data electrode (16) side the same as the circuit on the scanning electrode (11) side,
Since both manufacturing processes are shared, the production can be performed more easily. Furthermore, by configuring the power supply circuits (14, 15, 59, 60) on the scanning side and the data side to have substantially the same withstand voltage (claim 8), the manufacturing steps of both can be made more common. It can be made more easily.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment in which the present invention is applied to an EL panel will be described below with reference to FIGS. FIG. 5 is a functional block diagram showing a configuration of one column of a driving circuit for driving a row-side (scanning-side) electrode of an EL panel. In FIG. 5, one end of each display cell 10a constituting an EL panel (matrix display device) 10 is provided. , Each row side electrode 1
1 is connected. Each row-side electrode 11 is connected to an output terminal 12 a of a row-side drive circuit (drive circuit) 12 configured as an IC, that is, an output terminal of a row-side voltage application circuit (scanning voltage application circuit) 13. I have.

The positive and negative power supply terminals of each row voltage application circuit 13 are connected to positive and negative power supply circuits 14 and 15 respectively.
Are connected respectively. The power terminal and the ground terminal of each positive-side power supply circuit 14 are connected to the low-side drive circuit 1.
2 are connected to the + VDH terminal and the VDL terminal, respectively, and the power supply terminal and the ground (GND) terminal of each negative-side power supply circuit 15 are connected to the -VDH terminal and the VDL 'terminal of the low-side drive circuit 12, respectively. .

Note that ± 200 V is supplied to the + VDH terminal and the −VDH terminal as positive and negative drive power supplies. The VDL terminal is connected to the ground,
A control power supply of 5 V is supplied to the VDL 'terminal.

On the other hand, a column-side (data-side) electrode 16 is connected to the other end of each display cell 10a, and these column-side electrodes 16 are commonly used as output terminals of a column-side drive circuit 17. It is connected. The positive and negative drive power supply voltages supplied to the column drive circuit 17 are ± 50
V. Actually, as shown in FIG. 6, a plurality of row-side electrodes 11 and a plurality of column-side electrodes 16 exist, and both are arranged so as to be orthogonal to each other.
Each display cell 10a of the EL panel 10 is formed.

FIG. 3 shows the electrical configuration of the low-side voltage application circuit 13 and the positive and negative power supply circuits 14 and 15 more specifically. 3, a low-side voltage application circuit 13 includes a P-channel MOSFET (P-channel MOS transistor, hereinafter referred to as an FET) 18 and an N-channel MOSFET.
A channel MOSFET (N-channel MOS transistor, hereinafter referred to as FET) 19 is configured by push-pull connection. These FETs 18 and 19
Parasitic diodes 18a and 19a are respectively formed between the source and the drain.

Between the source of the FET 18 and the ground, there is connected a voltage dividing circuit (gate drive circuit) 20 having resistors 20a and 20b connected in series.
And 20b are connected to the gate of FET18. A voltage dividing circuit (gate driving circuit) 21 formed by connecting resistors 21a and 21b in series is connected between the source of the FET 19 and the ground.
The common connection point of 1a and 21b is connected to the gate of FET19. And the commonly connected FET
The drains of 18 and 19 are connected to the output terminal 12a of the row side drive circuit 12.

The positive-side power supply circuit 14, like the low-side voltage application circuit 13, is configured by a push-pull connection of a P-channel MOSFET 22 and an N-channel MOSFET 23. Is connected to the source of the FET 18.

An N-channel MOS is connected between the sources of the FETs 22 and 23 through a series circuit of resistors 24a and 24b.
The drain-source of the FET 25 is connected, and the common connection point of the resistors 24a and 24b is connected to the gate of the FET 22. The sources of the FETs 22 and 23 are connected to the + VDH terminal and the VDL terminal of the low-side drive circuit 12, respectively. Gates of the FETs 23 and 25 are externally supplied with gate signals.

Similarly to the low-side voltage application circuit 13, the negative-side power supply circuit 15 is also configured by a push-pull connection of a P-channel MOSFET 26 and an N-channel MOSFET 27. The drain is connected to the source of the FET 19. FE
Between the sources of T27 and T27, resistors 28a and 28b
The drain-source of the P-channel MOSFET 29 is connected through a series circuit of
Are connected to the gate of the FET 27. The sources of the FETs 27 and 26 are connected to the -VDH terminal and the VDL 'terminal of the low-side drive circuit 12, respectively.

An unillustrated EL is connected to the gate of the FET 29.
A gate signal is supplied from the controller, and a gate signal is supplied to the gate of the FET 26 via the gate drive circuit 30 from the EL controller. This gate drive circuit 30
When a gate signal is given from the EL controller, FE
The FET 26 is turned on by applying a negative voltage to the gate of T26.

In the above configuration, the output pattern of the row-side voltage application circuit 13 to the row-side electrode 11 is (1)
+ VDH application, (2) GND (VDL) connection, (3)-
VDH application, (4) GND (VDL ') connection, and (5) floating (high impedance). Hereinafter, the switching operation of each FET in each case will be described.

(1) Applying + VDH In this case, the FET 22 of the positive power supply circuit 14 is turned on to turn on the FET 22. Then, since the source of the FET 18 of the low-side voltage application circuit 13 is connected to + VDH, the divided output of the voltage dividing circuit 20 is applied to its gate, and the FET 18 is turned on.

On the other hand, on the negative power supply circuit 15 side, the gate drive circuit 30 applies a negative voltage to the gate of the FET 26 to turn on the FET 26. Then, since the source of the FET 19 of the low-side voltage application circuit 13 is connected to VDL ', the divided voltage output of the voltage dividing circuit 21 is substantially at the ground level, and the FET 19 is turned off. Therefore, the level of the output terminal 12a of the row side drive circuit 12 becomes + VDH.

(2) GND (VDL) connection From the state of + VDH application, the FE of the positive side power supply circuit 14
When T25 is turned off, the FET 22 and the FET 18 of the low-side voltage application circuit 13 are turned off. And FET
When a positive voltage is applied to the gate of 23 to turn on the FET 23, the source of the FET 18 is connected to VDL. At this time, the output terminal 12a of the row side drive circuit 12 is connected to the FET1
8 is connected to VDL via the parasitic diode 18a (to discharge a positive charge as described later).

(3) Application of -VDH In this case, the FET 27 of the negative power supply circuit 15 is turned off, and the FET 27 is turned on by turning on the FET 29. Then, since the source of the FET 19 of the low-side voltage application circuit 13 is connected to -VDH, the gate thereof has:
The divided voltage output of the voltage dividing circuit 21 is applied, and the FET 19 is turned on.

On the other hand, in the positive power supply circuit 14, the FET
25, the FET 22 and the low-side voltage application circuit 1
The third FET 18 is turned off. Then, since the source of the FET 19 of the low-side voltage application circuit 13 is connected to -VDH, the divided output of the voltage dividing circuit 21 is applied to the gate of the FET 19, and the FET 19 is turned on. Therefore, the level of the output terminal 12a of the low-side drive circuit 12 is-
VDH.

(4) GND (VDL ') connection-From the state of -VDH application, the FE of the negative power supply circuit 15
When T29 is turned off, the FET 27 and the FET 19 of the low-side voltage application circuit 13 are turned off. And FET2
By turning on 6, the source of the FET 19 is connected to VDL '. At this time, the output terminal 12a of the row side drive circuit 12
Is VDL via the parasitic diode 19a of the FET 19.
(To discharge negative charges as described later). (5) Floating In this case, both the FETs 18 and 19 are turned off.

FIGS. 1 and 2 schematically show cross sections when the above-mentioned row-side drive circuit 12 is formed on an SOI substrate (semiconductor substrate) 31. FIG. P-channel MO constituting voltage application circuit 13
FIG. 3 schematically shows a cross section when the SFET 18 is formed as an LD (Lateral Double-diffused) MOSFET.

In FIG. 2, the SOI substrate 31 has a structure in which a single crystal silicon layer 34 is provided on a support substrate 32 made of, for example, a single crystal silicon substrate with a silicon oxide film 33 interposed therebetween. In the layer 34, an island-shaped silicon layer 34a separated from other element formation regions by a ring-shaped insulating isolation trench 35 is formed. The insulating isolation trench 35 is in a state of being buried with the insulating silicon oxide film 36 and the polysilicon 37.

In the region of the island-like silicon layer 34a which is in contact with the silicon oxide film 33, a low impurity concentration electric field relaxation layer 3 is formed.
8 are formed. This electric field relaxation layer 38 is made of boron,
This is a single crystal silicon layer in which the concentration of impurities such as phosphorus, arsenic, and antimony is extremely low, and substantially functions as an intrinsic semiconductor layer.

The upper part of the island-shaped silicon layer 34a is a drift layer 39 made of a P-diffusion layer. The drift layer 39 is provided as a low impurity concentration layer because a relatively high resistance is required. However, the drift layer 39 is set to have a higher impurity concentration than the electric field relaxation layer 38.

The drift layer 3 is formed on the island-shaped silicon layer 34a.
The N-type impurity is diffused from the surface side of the substrate 9 to form a double well 40 having a ring shape (for example, an oval shape) in plan view. This double well 40
Is composed of an N well 40a reaching the inside of the electric field relaxation layer 38 and an N well 40b for forming a channel which is arranged at a surface side portion thereof so as to be continuous with the N well 40a. The N well 40b is formed by a well-known double diffusion technique together with the source diffusion layer 41 formed of a P + diffusion layer, whereby a P channel region is formed on the surface of the N well 40b. It has become.

On the surface side of the N well 40b, a source diffusion layer 42 of an N + diffusion layer for taking the potential of the N well 40b is formed. In this case, since the N wells 40a and 40b and the source diffusion layers 41 and 42 are formed in a ring shape, the P channel region is also formed in the same ring shape. By forming the P-channel region in a ring shape in this manner, it is possible to obtain an FET structure in which concentration of an electric field can be reduced and a large current can flow.

In the island-shaped silicon layer 34a, a P-well 43 is formed as a deep drain region in which P-type impurities are diffused so as to be located at the center of the ring-shaped source diffusion layers 41 and 42. This P-well 43
Are formed at a depth (slightly deep state) similar to the junction depth of the N well 40a. A drain contact layer 44 made of a P + diffusion layer is formed on the surface of the P well 43. In this case, the impurity concentration of the P well 43 is set to an intermediate level between the impurity concentrations of the drift layer 39 and the drain contact layer 44.

On the single crystal silicon layer 34, an N well 4
0b and the drain contact layer 44, and the N well 4
An LOCOS oxide film 45 for electric field relaxation is formed in a portion such as between Ob and the adjacent island-shaped silicon layer 34a. In a portion corresponding to the P channel region formed in the N well 40b, a gate polysilicon film 46 is formed.
Are formed via a gate oxide film (silicon oxide film) not shown, and the shape of the gate polysilicon film 46 is formed in a ring shape corresponding to the P channel region.

Further, the source diffusion layers 41 and 42 and the drain contact layer 4 described above are formed on the single crystal silicon layer 34.
4, an insulating film 47 made of a silicon oxide film is formed so as to cover the LOCOS oxide film 45 and the gate polysilicon film 46.

Each electrode film is formed of aluminum on the insulating film 47 as follows. That is,
At a position corresponding to the source diffusion layers 41 and 42, a source electrode film 48 (as a planar shape) electrically connected to the source diffusion layers 41 and 42 via contact holes is formed in a ring shape.

At a position corresponding to the drain contact layer 44, a drain electrode film 50 electrically connected to the drain contact layer 44 via a contact hole is formed in a ring shape. Also, the gate polysilicon film 4
The gate polysilicon film 4 is located at a position corresponding to 6.
The gate electrode film 51 electrically connected to the gate electrode 6 via a contact hole is formed in a rod shape (as a planar shape).

As described above, the island-shaped silicon layer 34
a, a drain contact layer 44 and ring-shaped source diffusion layers 41 and 42 formed concentrically therearound.
And a drain center type P channel type L
A DMOSFET (LDMOS transistor) 18 is formed.

FIG. 1 schematically shows a cross section when the row side drive circuit 12 is formed on the SOI substrate 31 as described above. In the center, an island-shaped silicon layer 3
4a, and island-shaped silicon layers 34b and 34c are formed on the left and right sides in FIG. The row-side voltage application circuit 13 is formed on the island-shaped silicon layer 34a, and the positive-side and negative-side power supply circuits 14 and 15 are formed on the island-shaped silicon layers 34b and 34c, respectively.

The LDM formed on each island-like silicon layer
There is one OSFET and another LDMOSFET
Are not shown in FIG. 1 because they are arranged on the depth side in FIG.

Next, the operation of the first embodiment will be described with reference to FIG. FIG. 4 shows a timing chart when a drive voltage is applied to the column-side electrode 16 and the row-side electrode 11 by an EL controller (not shown). When the column-side voltage application circuit 17 latches the display data for one row (row-side electrode 11) output from the EL controller, the driving voltage (data voltage: −50 V) is applied to the column-side electrode 16 according to the display data. Is applied.

For convenience of illustration, FIG. 4 shows only one column-side electrode 16 and three (-) row-side electrodes 11. Further, as shown by a broken line in FIG. 4, the row-side electrodes 11 to 11 are in a floating state as an initial state.

For example, if the display data for one line is "1011"
0 (corresponding to,,, of the column-side electrodes 16) ”, a data voltage is applied to, of the column-side electrodes 16, and no data voltage is applied to,. The column side voltage application circuit 17
The timing at which the row-side voltage application circuit 13 applies a drive voltage (scanning voltage: +200 V) to the row-side electrode 11 (FIG. 4)
The data voltage is applied in synchronization with (see (b)) (see FIG. 4 (a)).

Then, two ends of the display cell 10a at the intersection of the row-side electrode 11 and the column-side electrode 16 to which the data voltage is applied by the column-side voltage application circuit 17 are provided.
When a voltage of 50 V is applied, the display cell 10a is charged, reaches a saturation luminance voltage, and enters a display state.

Thereafter, the row-side electrode 11 is connected to GND (VD
L) level, and the electric charge (positive on the low-side electrode 11 side) charged in the display cell 10a is discharged. Then, the next time the scanning voltage is applied to the row side electrode 11, the row side electrode 11 returns to the floating state.

In the same manner, a scanning voltage is applied to the row-side electrode 11 at a predetermined scanning cycle, and the corresponding display cell 10a is charged and discharged immediately after the display state. When the scanning of all the row-side electrodes 11 is completed, the display of the EL panel 10 for one screen (first frame) is completed.

Although each display cell 10a is discharged immediately after being charged and brought into the display state, the time during which the display state is in the display state is short. However, since the scanning cycle is extremely fast, an afterimage is not recognized by human eyes. By remaining, the screen for one frame appears to be displayed. In the next second frame, the polarity of the drive voltage applied to the display cell 10a is reversed between the column-side electrode 16 and the row-side electrode 11. That is,
The data voltage is + 50V and the scanning voltage is -200V. In this case, when discharging the charge (negative) charged in the display cell 10a, the low-side electrode 11 is set to the VDL 'level.

As described above, according to the present embodiment, the low-side voltage application circuit 13 is supplied with positive and negative drive power from the positive and negative power supply circuits 14 and 15, and
Since the row-side voltage application circuit 13 and the positive-side and negative-side power supply circuits 14 and 15 are formed on the SOI substrate 31 in a state of being electrically separated from each other and arranged in a state of being close to each other, It is possible to shorten the length of the power supply line connecting between the circuits, and even if the potential of the power supply line greatly changes, it does not adversely affect other control signal lines and the like such as crosstalk, and the entire low-side drive circuit 12 Can be made small.

The column-side electrode 1 applied simultaneously
Even when the drive voltage of the row-side drive circuit 12 is set relatively low and the drive voltage of the individually applied row-side electrode 11 is set relatively high, adverse effects due to the operation of the row-side drive circuit 12 can be suppressed. .

According to the present embodiment, the low-side voltage application circuit 13 and the positive and negative power supply circuits 14 and 15
Is constituted by the LDMOSFET, the on-resistance can be reduced and the current driving capability can be improved as compared with the high breakdown voltage MOSFET having the normal configuration, and the whole can be further reduced in size.

FIG. 7 shows a second embodiment of the present invention. The same parts as those in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted. Only different parts will be described below. In the second embodiment, the low-side voltage application circuit 13 in the first embodiment is used.
Voltage dividing circuit 20 for driving the gate of FET 18
Is connected to GND via the source-drain of an N-channel MOSFET (MOS transistor) 52. Then, the voltage dividing circuit 20 and the FET 52
Constitute the gate drive circuit 53.

The power supply side terminal of the voltage dividing circuit 21 for driving the gate of the FET 19 is a P-channel MOSFET (M
An OS transistor) 54 is connected to a control power supply via a source-drain thereof, and is connected to the voltage dividing circuit 21 and the FET 5.
4 constitutes the gate drive circuit 55. As described above, the row-side voltage application circuit 13a is configured.

The gates of these FETs 52 and 53 are supplied with gate signals from an EL controller. And the positive and negative power supply circuits 1
A plurality of row-side voltage application circuits 13a are connected to the output terminals of 4 and 15, so that a row-side drive circuit (drive circuit) 56 is configured.

According to the second embodiment configured as described above, the gate drive circuits 53 and 55 for the FETs 18 and 19 are provided.
By providing the FETs 52 and 54, respectively, even if the positive and negative power supply circuits 14 and 15 are connected in common, the EL controller gives a gate signal at a predetermined scanning timing, so that each row-side voltage is supplied. F of the application circuit 13a
The on / off of the ETs 18 and 19 can be individually controlled. Therefore, the positive and negative power supply circuits 14 and 15 can be shared, and the row drive circuit 56 can be made smaller.

FIG. 8 shows a third embodiment of the present invention. The same parts as those in the first embodiment are denoted by the same reference numerals, and the description will be omitted. Only the different parts will be described below. In the third embodiment, the column-side drive circuit 17 of the first embodiment is used.
Is replaced by a column-side drive circuit 57 having the same configuration as the row-side drive circuit 12.

That is, the column-side voltage application circuit (data-side voltage application circuit) 58 and the positive-side and negative-side power supply circuits 59 and 60 constituting the column-side drive circuit 57 are connected to the row-side voltage application circuit 13 and the positive and Just like the negative side power supply circuits 14 and 15, the same type of circuit is configured by push-pull connected P and N channel MOSFETs.
These are formed on the same SOI substrate 31. The drive circuit 61 includes the row-side drive circuit 12 and the column-side drive circuit 57. In FIG. 8, the gate drive circuit of each FET is not shown.

According to the third embodiment configured as described above, the row-side and column-side drive circuits 13 and 57 are connected to the SOI
Since the process for forming the substrate 31 can be shared, the manufacturing process can be further simplified.

The present invention is not limited to the embodiment described above and shown in the drawings, and the following modifications or extensions are possible. In the third embodiment, the withstand voltage of each of the FETs constituting the column-side drive circuit and the data-side drive circuit may be set to be the same by setting the data-side drive voltage and the scan-side drive voltage to the same potential (± 125 V). With such a configuration, the manufacturing process of the drive circuit can be further shared. The row-side drive circuit 13 of the third embodiment may be replaced with the row-side drive circuit 56 of the second embodiment. The switching elements that make up each circuit are LDMOSFET
However, the present invention is not limited to this configuration, and may be configured by other types of MOS transistors. The matrix type display device is E
The liquid crystal panel is not limited to the L panel 10 and may be, for example, a liquid crystal panel.

[Brief description of the drawings]

FIG. 1 is a diagram schematically showing a cross section when a row-side drive circuit according to a first embodiment of the present invention is formed on an SOI substrate.

FIG. 2 shows a P-channel MO constituting a low-side voltage application circuit.
The figure which shows typically the cross section at the time of forming SFET as LDMOSFET.

FIG. 3 is a diagram more specifically showing an electrical configuration of a row side voltage application circuit and positive side and negative side power supply circuits;

FIG. 4 is a timing chart when a driving voltage is applied to each of a column-side electrode and a row-side electrode by an EL controller.

FIG. 5 is a functional block diagram showing a configuration for one column of a drive circuit for driving a row-side electrode of an EL panel.

FIG. 6 is a diagram schematically showing the configuration of the entire EL panel.

FIG. 7 is a view corresponding to FIG. 3, showing a second embodiment of the present invention;

FIG. 8 is a diagram showing an electrical configuration of a row-side drive circuit and a column-side drive circuit according to a third embodiment of the present invention.

FIG. 9 is a diagram corresponding to FIG. 3 showing a conventional technique.

[Explanation of symbols]

Reference numeral 10 denotes an EL panel (matrix type display device), 10a denotes a display cell, 11 denotes a row-side electrode (scanning electrode), 12 denotes a row-side drive circuit (drive circuit), and 13 denotes a row-side voltage application circuit (scan-side voltage application). Circuit), 14 is a positive power supply circuit, 1
5 is a negative side power supply circuit, 16 is a column side electrode (data side electrode), 17 is a column side drive circuit, 18, 22 and 26 are P channel MOSFETs (P channel MOS transistors and LDMOS transistors), 19, 23 and 27 Is N
Channel MOSFETs (N-channel MOS transistors, LDMOS transistors), 20 and 21 are voltage divider circuits, 31 is an SOI substrate (semiconductor substrate), 52 is an N-channel MOSFET (MOS transistor), 53 is a gate drive circuit, 54 is a P-channel MOSFET (MOS transistor), 55 is a gate drive circuit, 56 is a row-side drive circuit (drive circuit), 57 is a column-side drive circuit, 58 is a column-side voltage application circuit (data-side voltage application circuit), and 59 is a positive-side power supply A circuit, 60 is a negative power supply circuit, and 61 is a drive circuit.

Claims (8)

[Claims] 1. A matrix type display device (10) in which a display cell (10a) is formed at each intersection of a plurality of scanning electrodes (11) and data electrodes (16). The scanning electrode (11) and the data electrode (16)
By applying a drive voltage to each of the display cells (1)
0a) a driving circuit of a matrix type display device (10) configured to set a display state, wherein a push-pull scanning side voltage applying circuit (13) for applying a driving voltage to the scanning electrode (11); A positive power supply circuit (14) for supplying a positive drive power to the scanning voltage application circuit (13); and a negative power supply for supplying a negative drive power to the scanning voltage application circuit (14). And a scanning side voltage application circuit (14) and a positive side and negative side power supply circuit (15) are formed on a semiconductor substrate (31) in a state of being electrically separated from each other. A driving circuit for a matrix display device. 2. The scanning-side voltage application circuit (13) and the positive-side and negative-side power supply circuits (14, 15) are formed and arranged on the semiconductor substrate (31) in close proximity to each other. 2. A driving circuit for a matrix type display device according to claim 1, wherein: 3. The driving circuit according to claim 1, wherein the semiconductor substrate is an SOI substrate. 4. The scanning-side voltage application circuit (13) and the positive and negative power supply circuits (14, 15)
S transistor (18, 19, 22, 23, 26, 2
4. The method according to claim 1, wherein the method comprises:
The driving circuit for a matrix type display device according to any one of the above. 5. The scanning-side voltage application circuit (13a),
Push-pull connected P-channel and N-channel MO
The P-channel and N-channel MOS transistors (1).
8 and 19), one end of each of the gate drive circuits (53, 55) has a positive side and a negative side power supply voltage supply circuit (14, 1).
5) a voltage dividing circuit (20, 21) connected to the output terminal of each of the MOS transistors (18, 19), and an output terminal connected to the gate of the corresponding MOS transistor (18, 19); And MOS transistors (52, 54) connected to output a divided voltage from the output terminals of the corresponding voltage dividing circuits (20, 21) when turned on. 5. The driving circuit for a matrix type display device according to claim 1, wherein: 6. The positive and negative power supply circuits (14,
The driving circuit for a matrix type display device according to claim 5, wherein the driving circuit (15) is configured to supply a positive power supply and a negative power supply to the plurality of scanning voltage applying circuits (13a). 7. A push-pull data side voltage application circuit (58) for applying a drive voltage to said data electrode (16).
A positive power supply circuit (59) for supplying a positive drive power to the data voltage application circuit (58); and a negative power supply for supplying a negative drive power to the data voltage application circuit (58). A power supply circuit (60), wherein the data-side voltage application circuit (58) and the positive-side and negative-side power supply circuits (59, 60) are electrically separated from each other on the semiconductor substrate (31). The driving circuit for a matrix type display device according to claim 1, wherein the driving circuit is formed by: 8. The matrix type according to claim 7, wherein the withstand voltages of the power supply circuits (14, 15, 59, 60) on the scanning side and the data side are configured to be substantially the same. A driving circuit of a display device.