JP3722071B2 - Semiconductor integrated circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an output selection circuit in a driver of a matrix type liquid crystal display device.
[0002]
[Prior art]
The liquid crystal driver is constituted by a semiconductor integrated circuit, and has a plurality of output terminals. Each output terminal selects one value from 2 ⁿ gradation voltages by an output selection circuit, and applies a predetermined voltage to the liquid crystal. Is.
[0003]
In recent years, with the increase in size and resolution of liquid crystal display devices, the output selection circuit of the liquid crystal driver also increases the number of analog switches with the increase in the number of gradations and the number of pixels, the load on the liquid crystal data line, and the liquid crystal writing. As the time is shortened, the switch transistor size needs to be increased, and the chip size tends to increase year by year.
[0004]
FIG. 9 shows an example of an output selection circuit in a conventional liquid crystal driver disclosed in Japanese Patent Laid-Open No. 10-260664.
[0005]
The conventional output selection circuit is composed of an array of enhancement type transistors (hereinafter referred to as EMOS transistors) and depletion type transistors (hereinafter referred to as DMOS transistors), and a desired output can be obtained by setting the arrangement of the enhancement type and the depletion type. FIG. 9 shows a 3-bit output selection circuit as an example. L1 to L3 and their inverted signals are applied to the gate electrodes of the transistors running up and down, and V1 to V8 corresponding to each output are applied from the left side to the offset drain region of the transistors running left and right. Output is obtained. For example, when L1 to L3 is “000”, the value of V1 is obtained for the output Q, and when L1 to L3 is “010”, the value of V3 is obtained for the output Q.
[0006]
As each switching transistor used in the output selection circuit, for example, a transistor having an offset drain structure such as a LOCOS offset structure or an LDD offset structure is used so as to withstand an output voltage necessary for driving the liquid crystal display device.
[0007]
FIG. 2 and FIG. 4 are a cross-sectional view and a plan view, respectively, in the case where the output selection circuit as described above is configured by a LOCOS offset structure transistor. 2 and 4, 11 is a silicon single crystal substrate, 12 is a gate oxide film, 13a to 13f are polysilicon gate electrodes, 14 is a LOCOS oxide film, 15 is an offset drain region, 16 is a channel region of a DMOS transistor, 17 Is an activation region surrounded by the LOCOS oxide film 14, 20a to 20c are transistor pairs in a conjugate relationship, and FIG. 2 corresponds to a cross-section at B-B 'in FIG.
[0008]
FIG. 6 and FIG. 8 are a cross-sectional view and a plan view, respectively, in the case where the output selection circuit as described above is composed of transistors having an LDD offset structure. In the figure, 11 is a silicon single crystal substrate, 12 is a gate oxide film, 13a to 13f are polysilicon gate electrodes, 15 is an offset drain region, 16 is a channel region of a DMOS transistor, and 17 is surrounded by a LOCOS oxide film 14. An activation region, 18 is an LDD sidewall, 19 is a source / drain region, 20a to 20c are transistor pairs in a conjugate relationship, and FIG. 6 corresponds to a cross section taken along lines D to D ′ in FIG.
[0009]
[Problems to be solved by the invention]
However, along with the recent increase in size and definition of liquid crystal display devices, the above-described output selection circuit of the liquid crystal driver requires an increase in the number of analog switches and an increase in the size of the switch transistor, which increases the chip size. there were.
[0010]
In addition, in order to form a DMOS transistor, a pattern baking process, an impurity implantation process, and an additional cleaning process are required, resulting in an increase in the number of process steps and an increase in process cost.
[0011]
In view of the above problems, an object of the present invention is to provide an output selection circuit capable of reducing the chip size and simultaneously reducing the number of process steps.
[0012]
[Means for Solving the Problems]
In order to solve the above problems, an output selection circuit according to the present invention includes an EMOS transistor having a LOCOS offset structure and a parasitic transistor having a gate electrode on an extension of one of the LOCOS offset drain regions. Two types of transistor pairs having two types of transistors at symmetrical positions, a transistor row in which at least n of the transistor pairs are connected in an offset drain region, and a transistor in which at least 2 ^{n of the} transistor rows are connected at a gate electrode It consists of an array. An input signal and its opposite signal are applied to the gate electrodes of the at least n transistor pairs, respectively, and an input voltage of at least 2 ⁿ gradations is applied to one offset drain region of the transistor array. The two types of transistor pairs are arranged so that only one value of the input voltage is output to the other offset drain region of the array. Thus, by using a parasitic transistor instead of the DMOS transistor and further reducing the gate length of the parasitic transistor, the conjugate transistor pair area is reduced, and the chip size can be reduced as shown in FIG. is there. In addition, since no DMOS transistor is used, the number of process steps in the DMOS formation process can be reduced.
[0013]
In order to solve the above problems, another output selection circuit according to the present invention has an EMOS transistor having an LDD offset structure and a gate length that is the same as that of the LDD offset structure so that the offset drain regions on both sides are in contact with each other in the channel portion. Are composed of two types of transistor pairs in which the EMOS transistors having the same structure are connected at symmetrical positions in the offset drain region. It comprises a transistor array in which at least n transistor pairs are connected in an offset drain region, and a transistor array in which at least 2 ⁿ transistor arrays are connected through a gate electrode. An input signal and its opposite signal are applied to the gate electrodes of the at least n transistor pairs, respectively, and an input voltage of at least 2 ⁿ gradations is applied to one offset drain region of the transistor array. The two types of transistor pairs are arranged so that only one value of the input voltage is output to the other offset drain region of the array. Thus, by using an EMOS transistor with a reduced gate length instead of a DMOS transistor, the area of the conjugate transistor pair can be reduced, and the chip size can be reduced as shown in FIG. In addition, since no DMOS transistor is used, the number of process steps in the DMOS formation process can be reduced.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
The present invention will be described below with reference to the drawings.
[0015]
FIG. 1 is a cross-sectional view of an output selection circuit according to a first embodiment of the present invention. In the figure, 11 is a silicon single crystal substrate, 12 is a gate oxide film, 13a to 13f are polysilicon gate electrodes, 14 is a LOCOS oxide film, 15 is an offset drain region, and 17 is an activation surrounded by the LOCOS oxide film 14. The regions 20a to 20c are transistor pairs in a conjugate relationship. FIG. 3 is a plan view of the output selection circuit according to the first embodiment of the present invention, and FIG. 1 corresponds to a cross-sectional view taken along lines A to A ′ of FIG.
[0016]
In the present embodiment, the EMOS transistors 13b, 13d, and 13f constituting the output selection circuit have the same structure as the conventional example, but the gate electrodes 13a, 13c, and 13e of the DMOS transistor in the conventional example are respectively conjugated with each other in the present invention. Arranged on the extension of the offset drain region 15 and the LOCOS oxide film 14 of the related EMOS transistors 13b, 13d, and 13f, the gate length is reduced to the extent that there is no influence of wiring delay. This is a so-called parasitic transistor structure and performs the same function as the DMOS transistor in the conventional example. That is, since the offset drain region 15 of the EMOS transistor having the conjugate relationship is directly connected to the offset drain region of the adjacent conjugate transistor pair, the output voltage is set regardless of the ON / OFF state of the gate electrode of the parasitic transistor. The signal can be transmitted to the right adjacent conjugated transistor pair.
[0017]
In this way, by using a parasitic transistor instead of a DMOS transistor, and further disposing an EMOS transistor in a conjugated transistor pair as shown in FIG. 7 in a space that has become unnecessary by reducing the gate length of the parasitic transistor. The chip size can be reduced. In addition, since no DMOS transistor is used, the DMOS formation process can be omitted.
[0018]
Since the output selection circuit of this embodiment does not have a new structure compared to the output selection circuit of the conventional example, it can be easily realized by changing the mask layout and deleting the channel region 16 of the DMOS transistor. Can understand.
[0019]
FIG. 5 is a sectional view of an output selection circuit according to the second embodiment of the present invention. In the figure, 11 is a silicon single crystal substrate, 12 is a gate oxide film, 13a to 13f are polysilicon gate electrodes, 15 is an offset drain region, 18 is an LDD sidewall, and 19 is a source / drain region. FIG. 7 is a plan view of the output selection circuit according to the second embodiment of the present invention, and FIG. 5 corresponds to a cross-sectional view taken along C-C ′ in FIG.
[0020]
In the present embodiment, the EMOS transistors 13b, 13d, and 13f constituting the output selection circuit have the same structure as the conventional example. However, the gate lengths of the gate electrodes 13a, 13c, and 13e of the DMOS transistor in the conventional example are as follows. The offset drain regions 15 formed on both sides of the gate electrode are joined to each other in the channel region and reduced to such an extent that there is no influence of wiring delay. The structure in which the offset drain region is joined in the channel region is a kind of DMOS transistor, and performs the same function as the DMOS transistor in the conventional example. That is, since the offset drain region 15 of the EMOS transistor having a conjugate relationship is directly connected to the offset drain region and the channel region of the adjacent conjugate transistor pair, the output voltage can be set regardless of the ON / OFF state of the gate electrode. The signal can be transmitted to the right adjacent conjugated transistor pair.
[0021]
As shown in FIG. 7, the chip size can be reduced by arranging the EMOS transistors of the conjugate transistor pair in the space that is not required by using the EMOS transistor having a reduced gate length instead of the DMOS transistor. It can be done. In addition, since no DMOS transistor is used, the DMOS formation process can be omitted.
[0022]
Since the output selection circuit of this embodiment does not have a new structure compared to the output selection circuit of the conventional example, it can be easily realized by changing the mask layout and deleting the channel region 16 of the DMOS transistor. Can understand.
[0023]
In this embodiment, the source / drain regions are added to the configuration, but it is apparent from the first embodiment that the switching transistors may be connected only by the offset drain regions.
[0024]
Furthermore, although the present invention has been described by taking the liquid crystal driver as an example, it goes without saying that the present invention can be applied to an output selection circuit of any driver such as a PDP panel driver or a printer driver.
[0025]
【The invention's effect】
As described above, the output selection circuit according to the present invention reduces the chip size by reducing the gate length of the DMOS transistor, and at the same time omits the DMOS channel injection, thereby reducing the number of process steps and cost. A circuit can be provided.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of an output selection circuit according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view of an output selection circuit with a LOCOS offset structure according to a conventional example. FIG. 4 is a plan view of an output selection circuit with a LOCOS offset structure in a conventional example. FIG. 5 is a cross-sectional view of an output selection circuit in a second embodiment of the present invention. FIG. 7 is a cross-sectional view of an output selection circuit with an LDD offset structure in FIG. 7. FIG. 8 is a plan view of an output selection circuit according to a second embodiment of the present invention. Circuit diagram of conventional output selection circuit [Explanation of symbols]
11 Silicon single crystal substrate 12 Gate oxide films 13a to 13f Polysilicon gate electrode 14 LOCOS oxide film 15 Offset drain region 16 Channel region 17 of DMOS transistor Activation region 18 surrounded by LOCOS oxide film 14 LDD sidewall 19 Source / drain Transistor pairs in which the regions 20a to 20c are conjugated with each other

Claims (1)

An EMOS transistor having a LOCOS offset structure in which a gate oxide film is formed on an activation region surrounded by a LOCOS oxide film, and an offset drain region is formed immediately below the LOCOS oxide film and on a substrate on the side of the gate oxide film When the offset drain region, and the offset drain LOCOS oxide film on the region and the three-layer structure composed of a gate electrode formed on the LOCOS oxide film, and a transistor pair consisting of said offset drain the transistor pair a transistor array that at least n connected by a region, the transistor rows consists of at least 2 ⁿ pieces linked transistor array by the gate electrodes, respectively applied to the input signal and the opposite signal to the gate electrode of said at least n transistor pairs , the tiger One each input voltage of at least 2 ⁿ gradations in the offset drain region of the applied of Jisutaarei, said that only one value of the voltage of the other of the offset drain region to the input voltage of the transistor array is output, the transistor pair A semiconductor integrated circuit characterized by being arranged.

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