JP2005189680A - Buffer circuit, circuit for driving display device and display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce power consumption by lessening an area supplied to layout of an output stage of a drive signal by being applied to a flat display device by an organic EL element for instance, concerning a buffer circuit, a circuit for driving a display device and the display device. <P>SOLUTION: Drain sources of a set of transistors TR1 and TR2 of a single channel are connected to be arranged between a positive side power source Vcc1 and a negative side power source Vss, and the set of the transistors TR1 and TR2 are driven by drive signals IN and INX complementarily changing a signal level. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a buffer circuit, a display circuit drive circuit, and a display device, and can be applied to a display device using, for example, an organic EL (Electro Luminescence) element. In the present invention, the drain and source of a set of transistors of a single channel are connected and arranged between a positive power supply and a negative power supply, and these one set of transistors are driven by a drive signal whose signal level changes complementarily. By doing so, the area provided for the layout can be reduced so that the power consumption can be reduced.

  Conventionally, in a display device, for example, as disclosed in Japanese Patent Laid-Open No. 5-265411, a driving signal is sequentially transferred by a shift register circuit provided in a vertical driving circuit to generate a driving signal for each line. Each pixel is driven by using a buffer circuit in accordance with the drive signal thus generated, and an inverter circuit using a P-channel MOS transistor and an N-channel MOS transistor is applied to the buffer circuit. .

  That is, as shown in FIG. 5, in such a display device 1, a pixel portion 2 in which pixels are arranged in a matrix is formed on a glass substrate 3 using a TFT (Thin Film Transistor) made of amorphous silicon. . In addition, TFTs using amorphous silicon have a drawback that a P-channel transistor cannot be formed, and the mobility is as small as 1/100 compared to transistors using single crystal silicon or polysilicon. In the display device 1 of a kind, an integrated circuit is formed by vertical drive circuits 4A and 4B that sequentially drive each pixel of the pixel unit 2 in units of lines using single crystal silicon, polysilicon, or the like in a separate process. The integrated circuits of the vertical drive circuits 4A and 4B are arranged around the glass substrate 3 together with the integrated circuit of the horizontal drive circuit 5 for setting the gradation of each pixel.

  On the other hand, an inverter circuit using TFTs made of amorphous silicon is formed by N-channel transistors TR1 and TR2 as shown in FIG. That is, the drains and sources of the pair of transistors TR1 and TR2 are connected, the transistors TR1 and TR2 are arranged between the positive power supply Vcc1 and the negative power supply Vss, and the gate of the transistor TR2 on the positive power supply Vcc1 side is set to a predetermined Connected to the positive power supply Vcc2. In this inverter circuit, an input signal IN as shown in FIG. 7A is input to the gate of the transistor TR1 on the negative power supply Vss side, and the output signal OUT (see FIG. 7) from the midpoint of connection of these transistors TR1 and TR2. 7 (B)) is output. Here, in this inverter circuit, the positive power supply Vcc2 supplied to the gate of the transistor TR2 is set to a voltage higher than the threshold voltage Vth of the transistor TR2 with respect to the voltage of the positive power supply Vcc1, thereby operating. At this time, the cutoff of the transistor TR2 is effectively avoided, the H level of the output voltage OUT is held at the voltage of the positive power supply Vcc1, and the transient in the output signal OUT is prevented.

  By the way, if a buffer circuit is formed by an inverter circuit using TFTs shown in FIG. 6 to form a driving circuit for a display device, a horizontal driving circuit and a vertical driving circuit can be integrally formed on a glass substrate. It is considered that the manufacturing process can be simplified.

  However, in the inverter circuit shown in FIG. 6, the transistor TR2 on the positive power supply Vcc1 side is always kept on, and the transistor TR1 on the negative power supply Vss side is turned on / off according to the logic level of the input signal IN. Therefore, the L level of the output signal OUT becomes a signal level obtained by dividing the potential difference between the positive power supply Vcc1 and the negative power supply Vss by the on-resistance ratio of the transistors TR1 and TR2. Thus, in order to sufficiently lower the L level of the output signal OUT, the shape of the transistor TR1 on the negative power supply Vss side is made sufficiently larger than the transistor TR2 on the positive power supply Vcc1 side, and these transistors TR1, It is necessary to sufficiently increase the ON resistance ratio of TR2. Specifically, it is necessary that the transistors TR1 and TR2 have a channel width of about 1000/7 [μm] and 10/7 [μm]. As a result, such an inverter circuit using TFTs has a problem that a large area is required for the layout.

  On the other hand, in the display device 1, the parasitic capacitance increases in such a drive target of the inverter circuit due to the increase in size and resolution of the pixel portion. As described above, when the transistor TR2 is increased in size, the output capacitance Cp of the inverter circuit is increased accordingly. In order to ensure a high transient response characteristic when the capacity of such a load increases, it is necessary to further reduce the output impedance in the inverter circuit. For this purpose, both the transistors TR1 and TR2 must be connected. It is necessary to further increase the size and further reduce the on-resistance of the transistors TR1 and TR2. Specifically, when the channel width of the transistor TR2 is set to 1000/7 [μm], which is 100 times the above-described value, the channel width of the transistor TR1 needs to be set to about 100,000 / 7 [μm]. In addition, a larger area is required for the layout of the inverter circuit.

  Thus, when a large area is required for the layout of the inverter circuit, it becomes difficult to narrow the frame in the display device, and the obtained panel size is also limited.

In the inverter circuit of FIG. 6, since the transistor TR2 on the positive power supply Vcc1 side is always turned on, when the transistor TR1 is turned on, a so-called through current flows through the transistors TR2 and TR1, thereby There is also a problem that power consumption increases.
JP-A-5-265411

  The present invention has been made in view of the above points, and an attempt is made to propose a buffer circuit capable of reducing the power consumption by reducing the area provided for the layout, a display device driving circuit using the buffer circuit, and a display device. To do.

  In order to solve such a problem, the invention according to claim 1 is applied to the buffer circuit of the output stage of the drive signal, and the source or drain is connected to the positive side power source, and the drain or source is set as the output terminal. Negative power supply of the same channel type as the positive power supply transistor in which the source or drain is connected to the drain of the positive power supply transistor and the drain or source of the positive power supply transistor and the drain or source is connected to the negative power supply A drive signal or a signal having a reverse polarity of the drive signal is input to the gate of the transistor on the positive power supply side, and a signal or drive signal having the reverse polarity of the drive signal is input to the gate of the transistor on the negative power supply side. Enter.

  According to a second aspect of the present invention, in the configuration of the first aspect, an inverter circuit that generates a signal having a reverse polarity of the drive signal from the drive signal or an inverter circuit that generates a drive signal from the signal of the reverse polarity of the drive signal is provided. The inverter circuit is formed by a transistor of the same channel type as the transistor on the positive power supply side.

  According to a third aspect of the present invention, the present invention is applied to a driving circuit of a display device that drives a pixel portion in which pixels are arranged in a matrix, and is driven via a buffer circuit on a scanning line extending in the horizontal direction of the pixel portion. The buffer circuit is configured to connect a source or drain to the positive power source, and connect the drain or source to the output terminal of the drive signal, and the drain of the positive power source transistor. Alternatively, a source having a source or drain connected to the source and a transistor on the negative power source side having the same channel type as the transistor on the positive power source side having the drain or source connected to the negative power source is provided. A drive signal or a signal with a reverse polarity to the drive signal is input to the gate, and a signal or a drive signal with the reverse polarity to the drive signal is input to the gate of the transistor on the negative power supply side. To.

  According to a fifth aspect of the invention, a predetermined number of signal lines extending in the vertical direction of the pixel portion are applied to a drive circuit of a display device for driving a pixel portion in which pixels are arranged in a matrix. One digital-analog conversion circuit is assigned to the signal line, and the output signal of the digital-analog conversion circuit is sequentially distributed to a predetermined number of signal lines to drive the signal lines, and the distribution to the signal lines is connected to the signal lines respectively. This is executed by on / off control by a drive signal through the buffer circuit of the transistor, and the buffer circuit has a source or drain connected to the positive power supply, and the drain or source is set to the output terminal of the drive signal. Connect the source or drain to the drain or source of the positive side power supply transistor and the positive side power supply side transistor, and The transistor on the positive power supply side and the transistor on the negative power supply side of the same channel type connected to the drain or source are input to the gate of the transistor on the positive power supply side or a signal having a polarity opposite to that of the drive signal is input. Then, a signal having a polarity opposite to that of the drive signal or a drive signal is input to the gate of the transistor on the negative power supply side.

  According to the invention of claim 7, the present invention is applied to a display device having a pixel portion in which pixels are arranged in a matrix and a driving circuit for driving the pixel portion, and the driving circuit extends in the horizontal direction of the pixel portion. A driving signal is output to the scanning line via the buffer circuit, and the buffer circuit connects the source or drain to the positive power source, and the drain or source is set to the output terminal of the driving signal. And a negative power source transistor of the same channel type as a positive power source transistor in which a source or drain is connected to a drain or source of a positive power source transistor and a drain or source is connected to a negative power source. The drive signal or a signal having a polarity opposite to that of the drive signal is input to the gate of the transistor on the positive power supply side, and the drive signal is input to the gate of the transistor on the negative power supply side. Enter the reverse polarity of the signal or drive signal.

  In the invention of claim 8, the present invention is applied to a display device having a pixel portion in which pixels are arranged in a matrix and a drive circuit for driving the pixel portion, and the drive circuit extends in the vertical direction of the pixel portion. One digital-analog conversion circuit is assigned to a predetermined number of continuous signal lines, the output signal of the digital-analog conversion circuit is sequentially distributed to the predetermined number of signal lines, and the signal lines are driven. Distribution is performed by on / off control by a drive signal through a buffer circuit of a transistor connected to each signal line. The buffer circuit connects the source or drain to the positive power supply, and the drain or source is connected to the drive signal. The source is connected to the drain or source of the positive power supply side transistor set at the output terminal and the positive power supply side transistor. Alternatively, a positive-side power source transistor having a drain connected and a drain or source connected to a negative-side power source and a negative-side power source transistor of the same channel type, and a drive signal or A signal having a reverse polarity of the drive signal is input, and a signal having a reverse polarity of the drive signal or a drive signal is input to the gate of the transistor on the negative power supply side.

  According to the configuration of claim 1, the transistor is applied to a buffer circuit at an output stage of a drive signal, a source or drain is connected to a positive power supply, and the drain or source is set as an output terminal; A positive power supply transistor having a source or drain connected to a drain or source of a positive power supply transistor and a drain or source connected to a negative power supply and a negative power supply transistor of the same channel type. If a drive signal or a signal having a reverse polarity to the drive signal is input to the gate of the transistor on the positive power supply side, and a signal or drive signal having a reverse polarity to the drive signal is input to the gate of the transistor on the negative power supply side Can be complementarily turned on and off to output a drive signal. As a result, even when driving an object to be driven with a large capacity, these transistors should be formed in a small size to ensure sufficient transient response characteristics, and to ensure H level and L level with sufficient signal level. In addition, power consumption can be reduced.

  According to the configuration of claim 2, in the configuration of claim 1, an inverter circuit that generates a signal having a reverse polarity of the drive signal from the drive signal, or an inverter circuit that generates a drive signal from the signal of the reverse polarity of the drive signal is provided. If the inverter circuit is formed of a transistor of the same channel type as the transistor on the positive power supply side, a buffer circuit can be formed simply by supplying a drive signal or a signal having a polarity opposite to that of the drive signal. it can.

  Thus, according to the configurations of claims 3 and 5, respectively, the driving circuit by the buffer circuit that can be applied to the driving circuit for the scanning line and the signal line, respectively, can reduce the area used for the layout and reduce the power consumption. Can be provided. Moreover, according to the structure of Claim 7 and Claim 8, the display apparatus by such a drive circuit can be provided.

  According to the present invention, it is possible to reduce the power consumption by applying to the output stage of the drive signal and reducing the area provided for the layout.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings as appropriate.

(1) Configuration of Embodiment FIG. 2 is a block diagram showing a display device according to an embodiment of the present invention. The display device 21 includes a pixel unit 22 in which pixels of organic EL elements are arranged in a matrix, and scanning lines SCNA and SCNB provided in the pixel unit 22 so as to extend in the horizontal direction. Vertical drive circuits 23A and 23B for outputting drive signals, and a horizontal drive circuit 24 for setting the gradation of each pixel via signal lines SIGR, SIGG, and SIGB provided so as to extend in the vertical direction to the pixel portion 22 are provided. The N channel type TFT made of amorphous silicon is integrally formed on the glass substrate 25. The display device 21 generates various drive signals, clocks and the like necessary for the operation of the vertical drive circuits 23A and 23B and the horizontal drive circuit 24 by a timing generator (TG) 26, and generates the vertical drive circuit 23A on the glass substrate 25, 23B is supplied to the horizontal drive circuit 24, and gradation data D1 indicating the gradation of each pixel is supplied to the horizontal drive circuit 24, thereby displaying a desired image.

  FIG. 1 is a connection diagram showing the vertical drive circuit 23A. The vertical drive circuit 23A inputs the drive signal S1 output from the timing generator 26 to the shift register 31, and sequentially receives the drive signal S1 by the latch circuits 31A, 31B, 31C,. The output signals of the latch circuits 31A, 31B, 31C,... Are output to the scanning lines SCNA of the pixel unit 22 by the buffer circuits 32A, 32B, 32C,. The vertical drive circuit 23B is configured in the same manner as the vertical drive circuit 23A except that the drive signal output from the timing generator 26 used for the transfer is different, so that the vertical drive circuit 23B will be described below. Description is omitted.

  That is, in this vertical drive circuit 23A, the shift register 31 is formed by connecting latch circuits 31A, 31B, 31C,... That latch and output an input signal with a predetermined clock in series, and is connected to the leading latch circuit 31A. The drive signal S1 generated by the timing generator 26 is input, and the drive signal S1 is sequentially transferred with reference to the clock to generate a drive signal for each scanning line SCNA.

  The buffer circuits 32A, 32B, 32C,... Drive the corresponding scanning line SCNA by the output signals of the latch circuits 31A, 31B, 31C,..., Respectively, and are formed by inverter circuits in this embodiment. Has been made. Here, the buffer circuits 32A, 32B, 32C,... Are configured identically except that the input signals are different, so that the first stage buffer circuit 32A will be described in detail below. The subsequent description of the buffer circuits 32B, 32C,.

  Here, the buffer circuit 32A connects the drain of the N-channel type transistor TR2 to the positive power supply Vcc1, and connects the drain of the similar N-channel type transistor TR1 to the source of the transistor TR2, and further the source of the transistor TR1. Is connected to the negative power source Vss. Thus, the buffer circuit 32A is configured such that transistors TR1 and TR2 of the same channel are connected in series and arranged between the positive power supply Vcc1 and the negative power supply Vss. In this embodiment, the negative power source Vss is set to ground.

  Further, as shown in FIG. 3, in the buffer circuit 32A, the input signal IN (FIG. 3A) from the corresponding latch circuit 31A is input to the gate of the transistor TR1 on the negative power source Vss side. The inverted signal INX (FIG. 3B) of the input signal IN is input to the gate of the transistor TR2 on the positive power supply Vcc1 side, and accordingly, the transistor TR1 according to the logic level of the input signal IN. And TR2 are complementarily turned on and off. The buffer circuit 32A outputs the connection midpoint output OUT of these transistors TR1 and TR2 to the corresponding scanning line SCNA. Note that the logic of the inverted signal INX is prevented so that the output signal OUT is not cut off when the transistors TR1 and TR2 are complementarily turned on and off in this way and the transistors TR1 and TR2 are set to the on state and the off state, respectively. At the H level, the positive power supply Vcc1 is set to a voltage higher than the threshold voltage Vth of the transistor TR2. Thereby, in the buffer circuit 32A, even when the scanning line SCNA having a large parasitic capacitance is driven, the transistors TR1 and TR2 are not enlarged and the high transient response characteristic is ensured, and the signal of the output signal OUT is obtained. The level is lowered enough to be able to start up. In addition, power consumption can be reduced.

  Further, in the buffer circuit 32A, such an inverted signal INX of the input signal IN is formed by the inverter circuit 33 by the transistors TR3 and TR4. That is, the inverter circuit 33 is configured such that N-channel transistors TR3 and TR4 are connected in series and arranged between the positive power supply Vcc3 and the negative power supply Vss, similarly to the transistors TR1 and TR2. The gate of the transistor TR3 is connected to a predetermined positive power source Vcc2, and the input signal IN is input to the gate of the transistor TR4 on the negative power source Vss side. The inverter circuit 33 outputs the connection midpoint output of these transistors TR3 and TR4 to the gate of the transistor TR2 as an inverted signal INX of the input signal IN. In the buffer circuit 32A, as described above, the positive power supplies Vcc2 and Vcc3 are set so that the logic H level of the inverted signal INX is set to a voltage higher than the threshold voltage Vth of the transistor TR2 with respect to the positive power supply Vcc1. Is set to be set.

  In the buffer circuit 32A, these transistors TR1 to TR4 are formed with a gate length of about 1000/7 [μm], similarly to a normal transistor.

  On the other hand, FIG. 4 is a block diagram showing the horizontal drive circuit 24. Here, in the pixel unit 22 of the display device 21, red, green, and blue pixels are sequentially and repeatedly repeated in the horizontal direction, and so-called vertical stripes in which the red, green, and blue pixels are continuous in the vertical direction. Thus, the red signal line SIGR for driving the red pixels, the signal line SIGG for driving the green pixels, and the signal line SIGB for driving the blue pixels are sequentially and cyclically repeated. Yes. The horizontal drive circuit 24 drives the signal lines SIGR, SIGG, and SIGB by combining three pixels of red, green, and blue that are continuous in the horizontal direction. For this reason, in this display device 21, gradation data D1 for instructing gradation for red pixels continues for one line, then gradation data D1 for instructing gradation for green pixels continues for one line, and The gradation data D1 for instructing the gradation for the blue pixel is continuous for one line, and these are repeated and input to the horizontal drive circuit 24.

  In the horizontal drive circuit 24, the latch circuits (R) 41A, 41B,... Are provided corresponding to a set of three pixels of red, green, and blue that are continuous in the horizontal direction. The tone data D1 is sequentially cyclically latched and output. The digital / analog conversion circuits (D / A) 42A, 42B,... Perform the digital / analog conversion processing on the latch results of the latch circuits 41A, 41B,. The transistors TRR, TRG, and TRB are controlled by select signals SELR, SELG, and SELB to sequentially turn on, and output signals from the digital / analog conversion circuits 42A, 42B,. Output to SIGG and SIGB. Thus, in the horizontal drive circuit 24, the latch circuits 41A, 41B,..., The digital / analog conversion circuits 42A, 42B,... Are shared by the three signal lines SIGR, SIGG, SIGB, and the configuration is simplified accordingly. It is made to become.

  However, in this way, the output signals of the digital / analog conversion circuits 42A, 42B,... Are distributed to the signal lines SIGR, SIGG, SIGB by the transistors TRR, TRG, TRB, thereby controlling these transistors TRR, TRG, TRB. In the select signals SELR, SELG, and SELB, it is necessary to drive a large number of transistors TRR, TRG, and TRB respectively provided corresponding to the red, green, and blue pixels that are continuous in the horizontal direction. For this reason, in this embodiment, the select signals SELR, SELG, and SELB are connected to the transistors TRR and TRG via the buffer circuits 43R, 43G, and 43B having the same configuration as that of the above-described inverter circuit for the vertical drive circuits 23A and 23B, respectively. , Supplied to the gate of TRB.

  That is, in the horizontal drive circuit 24, the reference signal SH that rises for a certain period at the start timing of each horizontal scanning period is sequentially transferred by the latch circuits 44R, 44G, and 44B, thereby generating the select signals SELR, SELG, and SELB. To do. The horizontal drive circuit 24 supplies the select signals SELR, SELG, and SELB to the gates of the transistors TRR, TRG, and TRB through the buffer circuits 43R, 43G, and 43B, respectively.

(2) Operation of Embodiment In the above configuration, the display device 21 (FIG. 2) drives the scanning lines SCNA and SCNB by the vertical drive circuits 23A and 23B, and the pixel unit 22 by the signal lines SIGR, SIGG and SIGB. The gradation of each pixel is set so that a desired image is displayed. In the display device 21 (FIG. 1), the driving signal OUT used for driving the scanning lines SCNA and SCNB is converted from the driving signal S1 output from the timing generator 26 to the latch circuits 31A, 31B, and 31C constituting the shift register 31. ,... Are sequentially transferred, and this drive signal is output to the scanning lines SCNA, SCNB via the buffer circuits 32A, 32B, 32C,.

  In the display device 21, the buffer circuits 32A, 32B, 32C,... Are connected in series between transistors TR1 and TR2, which are N-channel TFTs formed by connecting the source and drain, between the positive power supply Vcc1 and the negative power supply Vss. The transistors TR1 and TR2 are driven by a drive signal IN and a signal INX having a polarity opposite to that of the drive signal IN. Accordingly, in the display device 21, the transistors TR1 and TR2 are complementarily turned on and off to drive the scanning lines SCNA and SCNB, and the scanning lines SCNA and SCNB are turned on by turning on the transistor TR1 on the negative power supply Vss side. The charge held in the capacitor is discharged by the transistor TR2 to cause the scan lines SCNA and SCNB to fall to the L level. On the contrary, the transistor TR2 on the positive power supply Vcc1 side is turned on to turn on the scan line SCNA. The capacitors such as SCNB and transistor TR2 are charged by the transistor TR1, and the scanning lines SCNA and SCNB are raised to the H level.

  As a result, the display device 21 can sufficiently raise and lower the logic levels of the scanning lines SCNA and SCNB by ensuring sufficiently high-speed transient response characteristics without increasing the size of the transistors TR1 and TR2. Thus, the buffer circuit 32A, 32B, 32C,... Is applied to the output stage of the drive signal to the scanning lines SCNA, SCNB, thereby reducing the area provided for the layout of the buffer circuits 32A, 32B, 32C,. Has been made to be able to. Accordingly, the vertical drive circuits 23A and 23B can be formed with a small area, and the display device 21 can be narrowed accordingly.

  In addition, the transistors TR1 and TR2 are complementarily turned on and off to prevent the through current generated when both the transistors TR1 and TR2 are set to the on state. Can be reduced.

  In the display device 21 (FIG. 3), a plurality of signal lines SIGR, SIGG, and SIGB for red, green, and blue, which are a plurality of continuous signal lines, are combined into three signal lines SIGR, SIGG, and SIGB. One digital / analog conversion circuit 42A, 42B,... Is assigned, and the output signals of the digital / analog conversion circuits 42A, 42B,... Are sequentially distributed to the plurality of signal lines SIGR, SIGG, SIGB, and signal lines SIGR, SIGG are assigned. , SIGB is driven. In the display device 21, the distribution to the signal lines SIGR, SIGG, and SIGB is a drive signal through the buffer circuits 43R, 43G, and 43B of the transistors TRR, TRG, and TRB connected to the signal lines SIGR, SIGG, and SIGB, respectively. It is executed by the on / off control by.

  Thus, even when the transistors TRR, TRG, and TRB are provided in the signal lines SIGR, SIGG, and SIGB and the transistors TRR, TRG, and TRB are controlled on and off, the size of the pixel portion is increased. By increasing the resolution, the number of transistors used for driving increases, and the gates of the transistors TRR, TRG, TRB are raised and lowered by charging / discharging a load related to a large capacity, and these transistors TRR, TRG, TRB are controlled on / off. It becomes necessary to do.

  However, in this embodiment, the on / off control of these transistors TRR, TRG, TRB is similar to the buffer circuits 43R, 43G similar to the buffer circuits 32A, 32B,... Provided at the output stage of the vertical drive circuits 23A, 23B. 43B, the horizontal drive circuit 24 can also be narrowed by reducing the area used for the layout, and the power consumption can be reduced.

(3) Advantages of the embodiment According to the above configuration, the drain and source of one set of transistors of a single channel are connected and arranged between the positive power supply and the negative power supply, and these one set of transistors are complementary. By driving with a drive signal whose signal level changes, the area provided for the layout can be reduced and the power consumption can be reduced.

  In addition, the buffer circuit having such a configuration is provided with an inverter circuit with transistors of the same channel, and generates a signal having a polarity opposite to that of the drive signal, thereby simply supplying the drive signal to the buffer circuit. According to the configuration, the area used for the layout can be reduced and power consumption can be reduced.

  In addition, by applying such a buffer circuit to a vertical drive circuit that drives a scanning line, the vertical drive circuit can be created with a small area, and the display device can be narrowed. Further, the power consumption of the display device can be reduced. Can be reduced.

  In addition, the output signal of the digital-analog converter circuit is distributed to a plurality of signal lines by controlling the transistor, and this buffer circuit is applied to the output stage of the driving signal used for controlling the transistor, thereby reducing the area of the horizontal driving circuit. Thus, the display device can be narrowed and the power consumption of the display device can be reduced.

  In the above-described embodiment, the case where the present invention is applied when the inverted signal of the input signal is output by the buffer circuit by the inverter circuit is described. However, the present invention is not limited to this, and the signal having the same polarity as that of the input signal is described. It can be widely applied to output. In this case, in the buffer circuit, in the configuration shown in FIG. 1, the transistor TR2 on the positive power supply Vcc1 side is driven by the input signal, and the transistor TR1 on the negative power supply Vss side is driven by the output signal of the inverter circuit 33. The output signal OUT having the same polarity as the input signal IN can be output.

  In the above-described embodiment, the case where the inverter circuit provided in the buffer circuit generates a signal having a polarity opposite to that of the input signal has been described. However, the present invention is not limited to this. For example, when the inverter circuit is omitted by inputting the signal, signals having different polarities may be generated by each part of the vertical drive circuit, each part of the horizontal drive circuit, a timing generator, or the like.

  In the above-described embodiments, the case where the buffer circuit is formed only by the N-channel type transistor has been described. However, the present invention is not limited to this. For example, the buffer circuit may be formed only by the P-channel type transistor. Can be widely applied. In this case, the connection relationship between the source and the drain is opposite to that in the first embodiment.

  In the above-described embodiments, the case where the present invention is applied to a display device using an organic EL element has been described. However, the present invention is not limited to this, and is widely applied to a display device using liquid crystal and various drive circuits. be able to.

  In the above-described embodiments, the case where the present invention is applied to a buffer circuit using TFTs made of amorphous silicon has been described. However, the present invention is not limited to this, and is widely applied to buffer circuits and drive circuits made of polysilicon and single crystal silicon. can do.

  The present invention can be applied to a display device using an organic EL element, for example.

It is a connection diagram which shows the vertical drive circuit applied to the display apparatus which concerns on Example 1 of this invention. It is a block diagram which shows the display apparatus which concerns on Example 1 of this invention. 2 is a time chart for explaining the operation of a buffer circuit in the vertical drive circuit of FIG. 1. FIG. 3 is a connection diagram illustrating a horizontal drive circuit applied to the display device of FIG. 2. It is a block diagram which shows the conventional display apparatus. It is a connection diagram which shows the buffer circuit by the conventional TFT. 7 is a time chart for explaining the operation of the buffer circuit of FIG. 6.

Explanation of symbols

1, 21... Display device, 2, 22... Pixel unit, 3, 25... Glass substrate, 4A, 4B, 23A, 23B... Vertical drive circuit, 5, 24. 41A, 41B, 44R, 44G, 44B .... Latch circuit, 32A-32C, 43R, 43G, 43B ... Buffer circuit, 33 .... Inverter circuit, 42A, 42B ... Digital-analog conversion circuit, TR1-TR4, TRR, TRG, TRB …… Transistor

Claims (8)

A buffer circuit at the output stage of the drive signal,
A source or drain connected to the positive power supply, and a transistor on the positive power supply side in which the drain or source is set at the output end; and
A transistor on the negative power supply side of the same channel type as the transistor on the positive power supply side connected to the drain or source of the transistor on the positive power supply side and connected to the drain or source on the negative power supply. Have
Input the drive signal or a signal having the opposite polarity of the drive signal to the gate of the transistor on the positive power supply side,
A buffer circuit, wherein a signal having a polarity opposite to that of the drive signal or the drive signal is input to a gate of the transistor on the negative power supply side. An inverter circuit that generates a signal with a reverse polarity of the drive signal from the drive signal, or an inverter circuit that generates the drive signal from a signal with a reverse polarity of the drive signal;
The buffer circuit according to claim 1, wherein the inverter circuit is formed of a transistor of the same channel type as the transistor on the positive power supply side. In a drive circuit for a display device that drives a pixel portion in which pixels are arranged in a matrix,
A drive signal is output via a buffer circuit to the scanning line extending in the horizontal direction of the pixel portion,
The buffer circuit is
A source or drain connected to a positive power supply, and the drain or source is set to the output terminal of the drive signal;
A source or drain connected to the drain or source of the transistor on the positive power supply side, and a transistor on the negative power supply side of the same channel type as the transistor on the positive power supply side connected to the drain or source to the negative power supply. Have
Input the drive signal or a signal having the opposite polarity of the drive signal to the gate of the transistor on the positive power supply side,
A drive circuit for a display device, wherein a signal having a polarity opposite to that of the drive signal or the drive signal is input to a gate of the transistor on the negative power supply side. An inverter circuit that generates a signal with a reverse polarity of the drive signal from the drive signal, or an inverter circuit that generates the drive signal from a signal with a reverse polarity of the drive signal;
4. The display device driving circuit according to claim 3, wherein the inverter circuit is formed of a transistor of the same channel type as the transistor on the positive power supply side. In a drive circuit for a display device that drives a pixel portion in which pixels are arranged in a matrix,
With respect to the signal lines extending in the vertical direction of the pixel portion, one digital-analog conversion circuit is assigned to a predetermined number of continuous signal lines,
The signal line is driven by sequentially distributing the output signal of the digital-analog converter circuit to the predetermined number of signal lines,
The distribution to the signal line is executed by on / off control by a drive signal through a buffer circuit of a transistor connected to the signal line,
The buffer circuit is
A source or drain connected to a positive power supply, and the drain or source is set to the output terminal of the drive signal;
A source or drain connected to the drain or source of the transistor on the positive power supply side, and a transistor on the negative power supply side of the same channel type as the transistor on the positive power supply side connected to the drain or source to the negative power supply. Have
Input the drive signal or a signal having the opposite polarity of the drive signal to the gate of the transistor on the positive power supply side,
A drive circuit for a display device, wherein a signal having a polarity opposite to that of the drive signal or the drive signal is input to a gate of the transistor on the negative power supply side. An inverter circuit that generates a signal with a reverse polarity of the drive signal from the drive signal, or an inverter circuit that generates the drive signal from a signal with a reverse polarity of the drive signal;
The display device driving circuit according to claim 5, wherein the inverter circuit is formed of a transistor of the same channel type as the transistor on the positive power supply side. In a display device having a pixel portion in which pixels are arranged in a matrix and a driving circuit for driving the pixel portion,
The drive circuit is
A drive signal is output via a buffer circuit to the scanning line extending in the horizontal direction of the pixel portion,
The buffer circuit is
A source or drain connected to a positive power supply, and the drain or source is set to the output terminal of the drive signal;
A source or drain connected to the drain or source of the transistor on the positive power supply side, and a transistor on the negative power supply side of the same channel type as the transistor on the positive power supply side connected to the drain or source to the negative power supply. Have
Input the drive signal or a signal having the opposite polarity of the drive signal to the gate of the transistor on the positive power supply side,
A display device, wherein a signal having a polarity opposite to that of the drive signal or the drive signal is input to a gate of the transistor on the negative power supply side. In a display device having a pixel portion in which pixels are arranged in a matrix and a driving circuit for driving the pixel portion,
The drive circuit is
With respect to the signal lines extending in the vertical direction of the pixel portion, one digital-analog conversion circuit is assigned to a predetermined number of continuous signal lines,
The signal line is driven by sequentially distributing the output signal of the digital-analog converter circuit to the predetermined number of signal lines,
The distribution to the signal line is executed by on / off control by a drive signal through a buffer circuit of a transistor connected to the signal line,
The buffer circuit is
A source or drain connected to a positive power supply, and the drain or source is set to the output terminal of the drive signal;
A source or drain connected to the drain or source of the transistor on the positive power supply side, and a transistor on the negative power supply side of the same channel type as the transistor on the positive power supply side connected to the drain or source to the negative power supply. Have
Input the drive signal or a signal having the opposite polarity of the drive signal to the gate of the transistor on the positive power supply side,
A display device, wherein a signal having a polarity opposite to that of the drive signal or the drive signal is input to a gate of the transistor on the negative power supply side.

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