JPH10335726A - Driving method and circuit of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacture a driving semiconductor device relatively easily by a method wherein, when the space between a drain diffused layer and a well diffused layer is supplied with a current in the sequential direction, the semiconductor substrate is electrically disconnected by a semiconductor switching element. SOLUTION: An EL display panel 1 is formed of electrically insulated scanning line electrode 9 and data line electrode 8. The point of intersection of the two elecctrodes 9, 8 is to be a picture element. A large capacity is parasitized on respective picture elements of the EL panel 1 and a plasma display. An output CMOS array high potential side power supply terminal 69 and an output CMOS low potential side power supply terminal 70 as the high voltage base power supply source terminals are externally power supplied. In such a constitution, the output CMOS array high potential side power supply terminal 69 is periodically power-supplied between 70 V and grounding potential 0 V by a switching element 3S. Besides, the output CMOS array low potential side power supply terminal 70 is controlled at the grounding potential 12 or in the disconnected state by another switching element 71.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving method and a driving circuit of a semiconductor device, and more particularly to a semiconductor device for driving a capacitive load, such as an EL display or a plasma display, which emits light by applying an electric field. In a power supply control circuit for supplying power to the semiconductor device,
The present invention relates to a technique capable of reducing power consumption and reducing a manufacturing process of a semiconductor device.

[0002]

2. Description of the Related Art A conventional driving method for an EL display will be described with reference to FIGS. FIG. 4 shows EL
FIG. 5 is a sectional view of an output stage CMOS in a semiconductor device (2 in FIG. 4) for driving an EL display panel. FIG. 3 shows waveforms of related parts in the semiconductor device for driving an EL display panel (2 in FIG. 4).

In FIG. 4, an EL display panel 1 is shown.
The electrodes 8 and 9 are formed in a grid pattern at equal intervals in the vertical and horizontal directions. Each intersection is a pixel, and the EL display or the plasma display inevitably generates a large electric field between the vertical electrode 8 and the horizontal electrode 9 to emit light. I do.

In the driving semiconductor device 2, several tens of high-voltage CMOSs 10 are arranged in an array on one semiconductor chip. The logic control of the high-voltage CMOS 10 is performed by a low-voltage CMOS control circuit such as a shift register circuit and a latch circuit mixedly mounted on the same driving semiconductor device 2, but is not shown because it is not directly related to the present invention.
Incidentally, the parasitic bipolar transistor 4 is structurally present in the high breakdown voltage CMOS 10. The parasitic bipolar transistor 4 greatly affects the power consumption of the EL display device, and its principle will be described later.

Output stage CMOS 10 of driving semiconductor device 2
, The low-potential-side power supply 11 is supplied with the ground potential, and the high-potential-side power supply 6 is supplied with power from the power supply voltage control circuit 3. The power supply voltage control circuit 3 also has a high-withstand-voltage CMOS configuration. The low-potential-side power supply is connected to the ground potential 12, and the high-potential-side power supply is connected to the 70V constant voltage source 5.

FIG. 5 shows a driving semiconductor device (2 in FIG. 4).
3 is a cross-sectional view of the output stage CMOS in FIG. An N-type epitaxial layer 22 is formed on a P-type semiconductor substrate 20.
The type epitaxial layer 22 is separated by the P-type insulating separation layer 21 into a high-breakdown-voltage N-channel insulated-gate field-effect transistor 39 and a high-breakdown-voltage P-channel insulated-gate field-effect transistor 40. Although not shown in the figure, the low-voltage control circuit is also formed separately in the same semiconductor substrate by the P-type insulating separation layer 21.

The high-breakdown-voltage N-channel insulated-gate field effect transistor 39 has a VDMOS structure, and includes a P-type base diffusion layer 35, a gate electrode 32, a source electrode 30, and a drain electrode 29 as shown in the figure. It should be noted that the drain current depends on the high concentration N-type buried diffusion layer 23 and the high concentration N
It is drawn out by the mold drawing diffusion layer 25. Reference numeral 33 denotes an oxide film, and reference numeral 38 denotes a surface insulating film.

The high-breakdown-voltage PMOS 40 has a horizontal structure having a P-type drain diffusion layer 34 of a high-breakdown-voltage specification. The gate electrode 31, the source electrode 27, and the drain electrode 26 are configured as illustrated. On the other hand, the parasitic bipolar transistor 4 also shown in FIG. 4 is formed below the P-type drain diffusion layer 34 as shown. In order to suppress the current amplification factor hFE of the parasitic bipolar transistor 4, the high-concentration N-type buried diffusion layer 23 is also formed below the P-type drain diffusion layer 34, and the current amplification factor hFE is suppressed to about 0.05. I have. The reason why the current amplification factor hFE must be kept low will be described later.

FIG. 3 shows waveforms of related parts in the driving semiconductor device 2. Output CMOS array high potential side power supply terminal 6
, A periodic rectangular wave 50 is applied by the control circuit 3. At the i-th arbitrary output terminal 14 of the output terminals 13, 14, 15, 16 the logic state 5 of the CMOS
1 is determined by the image information. The voltage of the i-th output terminal 14 includes a periodic rectangular wave 50 applied to the high potential side power supply terminal 6, a logic state 51 of the i-th output CMOS, and
The waveform shown in FIG. 52 is obtained from the capacitive load. Here, 55 is a charging process to the load, and 56 is a discharging process from the load. 53 is a current waveform at the i-th output terminal 14. The positive direction is the direction going out of the output terminal. 5
Reference numeral 7 denotes a charging current to the vertical electrode 8 corresponding to the i-th output terminal 14, and reference numeral 58 denotes a discharge current from the vertical electrode 8 corresponding to the i-th output terminal 14.

The path of the charging current 57 in the charging process 55 is indicated by 17 in FIG. A current flows through a path from a high-voltage constant-voltage power supply 5 of 70 V to 17 and the vertical electrode 8 is charged.
On the other hand, at the time of discharging, the path of the discharging current 58 in the discharging process 56 is indicated by 18 in FIG. In this case, the voltage 50 applied to the high-potential-side power supply terminal 6 rapidly drops from 70 V to 0 V while the logic state 51 of the i-th output CMOS maintains the “H” state. 4
In the normal CMOS operation (in which the logic state changes from "H" to "L" under a constant power supply voltage) indicated by reference numeral 19, the current path flowing to the ground side is not taken, and the parasitic bipolar transistor 4 Route 18 to return to high-voltage constant-voltage power supply 5 because of existence
And the amplifying action of the parasitic bipolar transistor 4,
It takes a path branched into two, a path 61 flowing to the ground side 12.

Since the target electrode 8 of the EL display panel is charged from the high-voltage constant-voltage power supply 5, when discharging the discharge current to the ground side 12, the power stored in the capacitance component of the load is not recovered, but the discharge is performed. If the current can be returned to the high-voltage / constant-voltage power supply 5, the power accumulated in the capacitance component of the load can be recovered, and accordingly, the power consumption of the EL display device can be reduced. The ratio of the current component that can recover the power by returning the discharge current to the high-voltage constant-voltage power supply 5 and the current component that cannot recover the power by not returning the discharge current to the high-voltage constant-voltage power supply 5 is 1 to the current of the parasitic bipolar transistor 4. The amplification factor is hFE.

As described above, the current amplification factor hFE of the parasitic bipolar transistor 4 is suppressed to about 0.05 or less, and almost all the power stored in the capacitance component of the load can be recovered. The reason why the current amplification factor hFE of the parasitic bipolar must be small is described in pages 410 to 416 of "Fuji Times Vol. 69 No. 8 1996".

[0013]

The first problem is that with the conventional driving method of the EL display panel or the plasma display panel, in order to suppress the power consumption, a relatively large number of scanning line electrodes and data line electrodes of the panel are used. When recovering the power charged in the capacitive load having a large capacitance value at the time of discharging, in order to increase the power recovery efficiency, the driving semiconductor device requiring the buried diffusion layer 23 and the epitaxial layer 22 described above, However, there is a problem that a driving semiconductor device having a complicated manufacturing process, such as a driving semiconductor device employing an insulating isolation structure in which a complicated insulating film is embedded, must be used. The reason is that, when recovering the power stored in the capacitive load, the internal structure of the driving semiconductor device must be able to reduce as much as possible the ratio of the current flowing in the path where the power cannot be recovered. .

An object of the present invention is to reduce the power consumption of an EL display panel device or a plasma display panel device, and to drive electrodes of these display panels and to provide a driving semiconductor device which is a component of the display device. The present invention is compatible with a device that can be manufactured by a relatively simple manufacturing process.

[0015]

In order to solve the above-mentioned problems, in a method of driving a semiconductor device according to the present invention, a well layer of a second conductivity type is formed on a surface of a semiconductor substrate of a first conductivity type. In a semiconductor device in which a first conductivity type field effect transistor having a first conductivity type drain diffusion layer in a two conductivity type well diffusion layer, a first conductivity type drain diffusion layer and a second conductivity type drain diffusion layer are provided. A method of electrically opening a semiconductor substrate of the first conductivity type by a first semiconductor switching element connected in series to the semiconductor substrate of the first conductivity type when a forward current flows between the well substrate and the well diffusion layer. And Here, the semiconductor device is a driving semiconductor device for driving a capacitive load, and a period in which the first semiconductor switching element electrically opens the semiconductor substrate of the first conductivity type is a discharge period from the capacitive load. It is preferable to perform control so as to match with. In that case, a signal corresponding to a portion where a high-potential-side power supply of the power supply includes a high-voltage power supply for supplying power to the semiconductor device and periodically falls is used as a logic signal for turning off the first semiconductor switching element. You can also. Further, in the first semiconductor switching element,
An insulated gate field effect transistor can also be used. Further, the first semiconductor switching element can be formed on a semiconductor substrate of the first conductivity type. Furthermore, it is preferable that the semiconductor device has a self-separation structure that can be manufactured by introducing impurities only from the surface of the semiconductor substrate of the first conductivity type. On the other hand, in the drive circuit of the semiconductor device according to the present invention, the second conductivity type well diffusion layer formed on the surface of the first conductivity type semiconductor substrate and the second conductivity type well diffusion layer formed in the second conductivity type well diffusion layer are formed. A first conductivity type field effect transistor having a one conductivity type drain diffusion layer, and a first conductivity type drain diffusion layer and a second conductivity type well diffusion layer which are connected in series to the first conductivity type semiconductor substrate. And a first semiconductor switching element for electrically opening the semiconductor substrate of the first conductivity type when a forward current flows between the wells. A second semiconductor switching element for supplying a pulsed power supply voltage to the second semiconductor switching element, the second semiconductor switching element and the first semiconductor switching element are connected in series,
In addition, they are formed on the same semiconductor substrate. Here, the low potential side power supply terminal of the power supply for supplying power to the semiconductor device is
It may be configured to be connected to the ground potential via the first semiconductor switching element. Further, both the first semiconductor switching element and the second semiconductor switching element can be constituted by insulated gate field effect transistors. Further, the semiconductor device may be a driving semiconductor device for driving a capacitive load such as an EL display or a plasma display. Further, the semiconductor device preferably has a self-separation structure that can be manufactured by introducing impurities only from the surface of the semiconductor substrate of the first conductivity type.

When recovering the power charged in the EL display panel or the plasma display panel at the time of discharging,
The current flows in a forward direction through a parasitic diode formed between the drain and the source of the output stage transistor of the driving semiconductor device. At this time, as long as the simple self-separation method of the manufacturing process is adopted, the current amplification factor of the parasitic bipolar transistor (the parasitic diode in the drain and the well) composed of the drain and the well and the substrate of the transistor formed in the well is used. Because hFE is as large as about 4 or more,
In the conventional power supply voltage application method, a high voltage is applied between the well and the substrate, and the current flowing through the parasitic diode (between the drain and the well) is applied to the current amplification factor hFE of the parasitic bipolar transistor according to the operation principle of the bipolar transistor.
Multiplied by the current flows between the well and the semiconductor substrate, and almost no power can be recovered.

On the other hand, if the present invention is applied, even when a driving semiconductor device having a self-isolation structure having a relatively simple manufacturing process is employed, when a current flows through a parasitic diode during a discharging process,
Since the semiconductor substrate is electrically opened, no voltage is applied between the well and the semiconductor substrate, so that an ineffective current that cannot be collected can be prevented from flowing at all.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the present invention will be conceptually described with reference to FIGS. FIG. 1 is a configuration diagram of an EL display device to which the present invention is applied. The driving semiconductor device 62 has a self-isolation structure that can be manufactured by introducing impurities only from the surface of the semiconductor substrate. FIG. 2 is a cross-sectional view of the output stage CMOS. The high-voltage low-potential power supply terminal 70 is connected to the semiconductor switching element 7.
1 is connected to the ground potential 12. Note that the waveforms of the related parts in the driving semiconductor device of the EL display panel are the same as those of the related art (see FIG. 3).

When the discharge current from the load electrode 8 is taken in from the i-th output terminal 66 (period 56 in FIG. 3), the current path flows through the path indicated by 72. However, during this period, since the semiconductor substrate (75 in FIG. 2) is electrically floated by the semiconductor switching element 71, a current flows due to the operation of the bipolar transistor which is not a target of power recovery as shown by 73 in FIG. Can be eliminated.

Next, a more specific description will be given with reference to FIGS. FIG. 1 is a configuration diagram of an EL display device according to the present embodiment, FIG. 2 is a cross-sectional view of an output stage CMOS in a semiconductor device for driving an EL display panel employed in the embodiment shown in FIG. 1, and FIG. 7 is a waveform of a related portion in the panel driving semiconductor device, which is the same as the conventional one.

In FIG. 1, reference numeral 1 denotes an EL display panel, and scanning line electrodes 9 formed at equal intervals in the horizontal direction.
And the data line electrodes 8 formed at equal intervals in the vertical direction, and the scanning line electrodes 9 and the data line electrodes 8 are electrically insulated. The intersection between the scanning line electrode 9 and the data line electrode 8 becomes a pixel. Since the EL panel or the plasma display emits light in a high electric field state, a large capacitance 7 is parasitic on each pixel, and the capacitance per electrode (8, 9) is as small as 2 to 3 nF. Become.

In FIG. 1, reference numeral 62 denotes a self-separating EL device.
This is a semiconductor device for driving a display panel. here,
Output terminals 65 to 68 are formed for 40 outputs per semiconductor chip. An output CMOS array high potential side power supply terminal 69 and an output CMO
There is an S array low-potential-side power supply terminal 70 to which power is supplied from the outside. The output CMOS array high-potential-side power supply terminal 69 is connected to 70 V and ground potential 0 by a switching element (second semiconductor switching element) 3S constituting a power supply voltage control circuit.
V is periodically supplied.

The output CMOS array low-potential-side power supply terminal 70 is controlled to a ground potential 12 or an open state by a switching element (first semiconductor switching element) 71. Reference numeral 63 denotes a high voltage CMOS array rated at 80 V, which corresponds to each output. Numeral 64 denotes a parasitic bipolar transistor, which is a self-separation method with a simple manufacturing process, and has a large current amplification factor hFE of about 4 or more. Although not described in the driving semiconductor device 62, the shift register and the latch are provided on the same semiconductor chip of the driving semiconductor device 62 in order to control each logical state of the high voltage CMOS array 63 according to the image information. A 5V CMOS logic circuit such as a circuit is mounted.

FIG. 2 is a sectional view of an output stage CMOS in a semiconductor device for driving a self-separation type EL display panel, and corresponds to 63 in FIG. Resistivity 15Ωcm2
An N-type well diffusion layer (second conductivity type well diffusion layer) 86 having a depth of 10 μm or more is formed in a P-type semiconductor substrate (first conductivity type semiconductor substrate) 75. The N-channel insulated gate field effect transistor 76 is a P-type semiconductor substrate 7
5 is formed in a portion where the N-type well diffusion layer 86 does not exist.

The P-channel insulated gate field effect transistor (first conductivity type field effect transistor) 77
The N-type well diffusion layer 86 is formed on the N-type semiconductor substrate 75. Reference numerals 78 and 79 denote drain diffusion layers of the N-channel insulated gate field effect transistor 76 and the P-channel insulated gate field effect transistor 77, respectively, which have high breakdown voltage specifications.

Drain diffusion layer 79 and N-type well diffusion layer 86 of P-channel insulated gate field effect transistor 77
A parasitic bipolar transistor 64 serving as an emitter diffusion layer, a base diffusion layer, and a collector diffusion layer is formed between the P-type semiconductor substrate 75 and the P-type semiconductor substrate 75, respectively.

The current amplification factor hFE of the parasitic bipolar transistor 64 is such that the N-type well diffusion layer 86 is ion-implanted from the surface of the P-type semiconductor substrate 75 and is pushed and diffused. 10-15
that the P-channel insulated gate field effect transistor 77
Since the drain diffusion layer 79 is a drain diffusion layer having a high withstand voltage specification, there is a restriction on the electrical characteristics even if it is made shallow, so that it is at most about 4 μm. Therefore, the current amplification factor hFE of the parasitic bipolar transistor 64 is low. 4 ~
Up to about 6.

The voltage and current at the relevant terminals of the driving semiconductor device 62 are the same as in the prior art, and are as shown in FIG. The high-potential-side power supply terminal 69 of the high-voltage system is provided by the switching element 3S.
Is a rectangular wave as shown in FIG.
On the other hand, the logic state 51 of the i-th output terminal 66 is determined according to the image information. The voltage waveform at the i-th output terminal 66 is shown at 52 by the waveform 50 applied to the high potential side power supply terminal 69, the logic state 51 of the i-th output terminal 66 and 2-3 nF and a relatively large capacitive load. The waveform is as follows.

In the process of charging the load, 74 in FIG.
As shown in (1), a current flows and the load electrode is charged. This case corresponds to 55 and 57 in FIG.

Next, the load electrode is discharged, and its potential is reduced to 70.
Step of dropping from V to 0 V (in this case, 5 in FIG. 3)
6 and 58), but the current in this case is such that the switching element 71 opens the P-type semiconductor substrate at least only during the discharge period, so that the current indicated by the path 73 in FIG. Most of FIG.
2 can be flowed. In FIG. 1, a current flowing in a path indicated by 73 flows into the lowest potential in the device configuration, and thus cannot collect power. However, a current flowing in a path indicated by 72 in FIG. 1 is a current capable of collecting power.

By turning off the switching element 71 only in the discharging process, the current flowing to the ground potential 12 can be eliminated. This switching element 7
1 and its appropriate switching control, even in a driving semiconductor device having a self-separation structure with a simple manufacturing process, it is possible to recover almost all the power stored in the load capacitance and suppress the power consumption of the device.

On the other hand, although the switching element 71 is
About 1 to several pieces may be used for the L display device, the same specification as the N-channel insulated gate field effect transistor of the switching element 3S may be used, and the source potential may be made common to the ground potential 12; Can be easily formed on the same chip as the existing switching element 3S. Therefore, there is almost no disadvantage such as an increase in the number of parts.

The switching element 71 may be turned off at a portion where the high-potential power supply of the high-voltage power supply periodically drops from 70 V to 0 V (see 50 in FIG. 3), and this logic signal exists in the device. Since the logic signal can be used with almost no processing, no particularly complicated control circuit is required.

[0034]

In order to suppress the power consumption of an EL display device or a plasma display device, a driving method for recovering, at the time of erasing, the power charged to the electrodes of the display panel, which is a capacitive load, is generally used. . For this reason, a semiconductor device for driving a junction isolation structure or a dielectric isolation structure, which has a structure in which a parasitic element that is a hindrance is suppressed, has been used to improve the recovery efficiency. However, realizing these structures requires complicated manufacturing processes. In the present invention, when a forward current flows between the drain diffusion layer and the well diffusion layer, the concept is adopted that the semiconductor substrate is electrically opened by the semiconductor switching element, thereby simplifying the manufacturing process. Even with the use of a driving semiconductor device having a self-separating structure, it is possible to obtain the same level of power recovery efficiency as in the past.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an EL display device according to the present invention.

FIG. 2 is a cross-sectional view of an output stage CMOS in a semiconductor device for driving a self-separation type EL display panel.

FIG. 3 is a waveform diagram of a relevant portion in a semiconductor device for driving an EL display panel.

FIG. 4 is a configuration diagram of a conventional EL display device.

FIG. 5 is a cross-sectional view of an output stage CMOS in a conventional semiconductor device for driving an EL display panel of a junction separation type.

[Explanation of symbols]

Reference Signs List 1 EL display panel 2 Driving semiconductor device 3 High voltage power supply control circuit 3S Switching element (second switching element) 4 Parasitic bipolar transistor 5 High voltage constant voltage power supply (70V) 6 High potential side power supply terminal 7 Capacitance parasitic on pixel 8 EL Vertical electrode of display panel 9 Horizontal electrode of EL display panel 10 Output stage CMOS in driving semiconductor device 11 Low potential side power supply terminal 12 Ground potential (0 V) 13, 15, 16 Output terminal 14 i-th output terminal 17 Target Current flowing when charging the electrode 18 Current flowing when discharging the target electrode 19 Normal discharge current from the target electrode 20 P-type semiconductor substrate 21 P-type insulating diffusion layer 22 N-type epitaxial layer 23 High-concentration N-type buried diffusion Layer 25 High-concentration N-type lead-out diffusion layer 26, 29 27, 30 Source electrode 31, 32 Gate electrode 33 Oxide film 34 Drain diffusion layer 35 Base diffusion layer 36 P-type diffusion layer 37 N-type diffusion layer 38 Surface insulating film 39 N-channel insulated gate field-effect transistor 40 P-channel insulated gate Field effect transistor 50 Voltage waveform 51 Logic state of i-th output CMOS 52 Output voltage waveform of i-th output 53 Output current waveform of i-th output 55 Charge process to electrode wire 56 Discharge process from electrode wire 57 Electrode Charge current to line 58 Discharge current from electrode line 59 High-potential power supply line 60 Low-potential power supply line 61 Current flowing by operation of parasitic bipolar transistor 62 Driving semiconductor device 63 Output CMOS in driving semiconductor device 64 Parasitic bipolar transistor 65, 67, 68 Output terminal 66 No. i output Terminal 69 High-potential-side power supply terminal 70 Low-potential-side power supply terminal 71 Switching element (first semiconductor switching element) 72 Current flowing when discharging the target electrode 73 Collector current when the parasitic bipolar transistor operates 74 Target electrode Current flowing when charging 75 P-type semiconductor substrate (first conductivity type semiconductor substrate) 76 N-channel insulated gate field effect transistor 77 P-channel insulated gate field effect transistor 78, 79 Drain diffusion layer 80, 83 Source electrode 81 , 84 Drain electrode 82, 85 Gate electrode 86 N-type well diffusion layer

Claims (11)

[Claims] A second conductive type well diffusion layer formed on a surface of a first conductive type semiconductor substrate, wherein a first conductive type drain diffusion layer is provided in the second conductive type well diffusion layer; 1
In a semiconductor device including a conductive type field effect transistor, the first conductive type drain diffusion layer and the second conductive type
When a forward current flows between the conductive type well diffusion layer and the conductive type well diffusion layer, the first semiconductor type semiconductor substrate is connected in series to the first conductive type semiconductor substrate. A method for driving a semiconductor device, comprising: 2. The semiconductor device according to claim 1, wherein the semiconductor device is a driving semiconductor device that drives a capacitive load, and the semiconductor device of the first conductivity type is electrically opened by the first semiconductor switching element. 2. The method of driving a semiconductor device according to claim 1, wherein the driving period is set to be equal to a discharge period from the reactive load. 3. A logic that includes a high-voltage power supply that supplies power to the semiconductor device, and outputs a signal corresponding to a portion where the high-potential-side power supply of the power supply periodically drops to turn off the first semiconductor switching element. 3. The method for driving a semiconductor device according to claim 1, wherein the method is used as a signal. 4. The first semiconductor switching element according to claim 1,
4. The method of driving a semiconductor device according to claim 1, wherein an insulated gate field effect transistor is used. 5. The first semiconductor switching element according to claim 1,
The method according to claim 1, wherein the semiconductor device is formed on the first conductivity type semiconductor substrate. 6. The semiconductor device according to claim 1, wherein said semiconductor device has a self-separation structure which can be manufactured by introducing impurities only from a surface of said first conductivity type semiconductor substrate.
6. The method for driving a semiconductor device according to claim 5. 7. A second conductivity type well diffusion layer formed on a surface of a first conductivity type semiconductor substrate, and a first conductivity type drain diffusion layer formed in the second conductivity type well diffusion layer. A first conductivity type field effect transistor having:
A first conductive type semiconductor substrate which is connected in series to a conductive type semiconductor substrate, and when a forward current flows between the first conductive type drain diffusion layer and the second conductive type well diffusion layer; And a first semiconductor switching element for electrically opening the second semiconductor switching element, the second semiconductor switching element for supplying a pulsed power supply voltage to the second conductivity type well diffusion layer. A driving circuit for a semiconductor device, wherein the second semiconductor switching element and the first semiconductor switching element are connected in series and formed on the same semiconductor substrate. 8. The semiconductor device according to claim 7, wherein a low-potential-side power supply terminal of a power supply for supplying power to said semiconductor device is connected to a ground potential via said first semiconductor switching element. Drive circuit. 9. The semiconductor device according to claim 7, wherein the first semiconductor switching element and the second semiconductor switching element are both insulated gate field effect transistors.
Or a driving circuit for a semiconductor device according to item 8. 10. The semiconductor device according to claim 7, wherein the semiconductor device is a driving semiconductor device for driving a capacitive load such as an EL display or a plasma display.
A driving circuit of the semiconductor device according to the above. 11. The semiconductor device according to claim 7, wherein the semiconductor device has a self-isolation structure that can be manufactured by introducing impurities only from the surface of the semiconductor substrate of the first conductivity type.
11. The drive circuit for a semiconductor device according to any one of claims 10 to 10.