JP2000196089A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To resolve a problem caused by changes in a source voltage in MISFET transistors which are connected in series. SOLUTION: In a semiconductor device, in which a back gate electrode 10 is formed in supporting substrate 5 facing opposite a channel region 4 in a gate array comprising a completely depleted SOI-MISFET, the back gate electrode 10 is electrically isolated from the back gate electrode of an adjacent transistor, and a back gate voltage is applied independently to each transistor. Thus, the semiconductor device can control the transistors.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a MISFET formed on a semiconductor layer on an insulating substrate, that is, a so-called SOI-MISFET (Silicon on insulator-Metal Ins).
The present invention relates to a semiconductor device formed by a semiconductor device.

[0002]

2. Description of the Related Art SOI-MISFETs, that is, MISFETs formed on a semiconductor layer formed on an insulating substrate, are, for example, compared with MISFETs formed on a bulk semiconductor substrate, in that, for example, the source / drain regions and the substrate are not connected to each other. Since the junction capacitance can be reduced, it is expected as a low power consumption and high speed device.

[0003] In particular, a so-called fully depleted SOI layer whose SOI layer has a thickness equal to or less than the thickness of a depletion layer in a channel region during operation.
The I-MISFET can eliminate or suppress undesired phenomena such as a kink characteristic and a current overshoot effect, which are problems in the so-called partially depleted SOI-MISFET in which the SOI layer is larger than the thickness of the depletion layer in the channel region during operation.

Further, the fully depleted SOI-MISFET has various advantages such as suppression of short channel effect, improvement of punch-through breakdown voltage, improvement of sub-threshold coefficient, and increase of channel mobility.

[0005]

FIG. 21 is a sectional view of a conventional semiconductor device in which MISFET transistors Qn1 and Qn2 formed on an SOI substrate are formed in a gate array structure.
The back gate electrode 1 is formed in the support substrate 5 facing the SOI layer region where the gate array is formed. As an example of a method of forming the back gate electrode 1, an n-type silicon region is formed by ion-implanting an n-type impurity such as phosphorus, arsenic, or antimony into a support substrate 5 made of p-type silicon facing the transistor region. Form. Then, by forming a voltage node 18 to the back gate electrode 1, it becomes possible to apply a voltage to the back gate electrode. Therefore, according to the structure of FIG.
It is possible to apply a back gate voltage equal to the SFET transistors Qn1 and Qn2.

However, the back gate electrode 1 shown in FIG.
In the structure described above, there is a problem that the parasitic capacitance CD with the drain electrode 15 is large. Also, the MISFET transistors Qn1 and
An independent back gate voltage cannot be applied to Qn2. Therefore, it is impossible to individually control the back gate voltage of the transistor.

Next, a description will be given of problems that occur in the circuit in the semiconductor device shown in FIG. FIG. 22 is a circuit diagram showing a NAND circuit. In FIG. 22, Qn1 and Qn2 are n-type
This is an MISFET, and Qp1 and Qp2 are p-type MISFETs. A common back gate electrode is provided for each of Qn1 and Qn2 and Qp1 and Qp2, and an n-type MISFET and a p-type MISFET are provided.
The back gate voltages VB1 and VB2 can be applied to each of the FETs.

In this circuit configuration, the source electrode of Qn2 is connected in series to the drain electrode of Qn1. Therefore, when the input voltages of Qn1 and Qn2 are conducted at VDD, the voltage of the source electrode of Qn2 increases by, for example, Vs due to the series resistance of Qn1. On the other hand, the voltage of the source electrode of Qn1 is 0 V because it is grounded. The source voltage of Qn2 rises higher than the source voltage of Qn1.

For this reason, the gate voltage input to Qn2 is
Vgs2 = (VDD-Vs), and the gate voltage of Qn1, Vg
s1 = less than VDD. Similarly, the back gate voltage of Qn2 also becomes VBS2 = (VB2−Vs), which is smaller than the back gate voltage of Qn1 VBS1 = VB1.

For this reason, even if this circuit is formed by transistors having Qn1 and Qn2 having the same threshold value, the same current driving capability or the same threshold value cannot be obtained. Therefore, there arises a problem that the delay times of Qn1 and Qn2 are different, which is a problem in circuit timing design.

The present invention provides a SOI-MISFET semiconductor device having a back gate electrode which solves such a problem, and particularly provides a SOI-MISFET semiconductor device having a gate array structure.

[0012]

According to a first aspect of the present invention, there is provided an insulating film, a first impurity region of a first conductivity type formed on the insulating film, and an insulating film adjacent to the first impurity region. A first channel region of the second conductivity type formed, a second impurity region of the first conductivity type formed adjacent to the first channel region, and a second impurity region of the second conductivity type. A second channel region of the second conductivity type formed, a third impurity region of the first conductivity type formed adjacent to the second channel region, and a second impurity region formed on the first channel region. The first
A second gate insulating film formed on the second channel region; a first gate electrode formed on the first gate insulating film; and a second gate insulating film formed on the second gate region. A second gate electrode formed on the film, a first back gate electrode of a first conductivity type formed below the first channel region via the insulating film, and the second channel region And a second back gate electrode of a first conductivity type formed under the insulating film with the insulating film interposed therebetween.

According to a second aspect of the present invention, there is provided a semiconductor device according to the first aspect of the present invention, comprising a first semiconductor region of a second conductivity type covering the first and second back gate electrodes. is there.

[0014] The third invention of the present application is the first invention, wherein a first power supply for supplying a first potential to the first back gate electrode;
And a second power supply for supplying a second potential different from the first potential to the back gate electrode of the first aspect of the present invention.

According to a fourth aspect of the present invention, there is provided an insulating film, a first impurity region of a first conductivity type formed on the insulating film, and a second conductive region formed adjacent to the first impurity region. Channel region, a first conductivity type second impurity region formed adjacent to the first channel region, and a second conductive region formed adjacent to the second impurity region. The second of the mold
A first conductive type third impurity region formed adjacent to the second channel region;
A first gate insulating film formed on the first channel region; a second gate insulating film formed on the second channel region; and a first gate insulating film formed on the first gate insulating film. A gate electrode, a second gate electrode formed on the second gate insulating film, and a first conductive type fourth impurity region formed under the second impurity region via an insulating film. And a fifth impurity region of the second conductivity type in one of a pair sandwiching the fourth impurity region.

According to a fifth aspect of the present invention, there is provided an insulating film, a first impurity region of a first conductivity type formed on the insulating film, and a second conductive region formed adjacent to the first impurity region. Channel region, a first conductivity type second impurity region formed adjacent to the first channel region, and a second conductive region formed adjacent to the second impurity region. The second of the mold
A first conductive type third impurity region formed adjacent to the second channel region;
A first gate insulating film formed on the first channel region; a second gate insulating film formed on the second channel region; and a first gate insulating film formed on the first gate insulating film. A gate electrode, a second gate electrode formed on the second gate insulating film, and a first conductive type fourth impurity region formed under the second impurity region via an insulating film. And fifth and sixth impurity regions of the second conductivity type facing each other with the fourth impurity region interposed therebetween, and a first power supply for supplying a first potential to the fifth impurity region. , The sixth
A second power supply for supplying a second potential different from the first potential to the impurity region.

According to a sixth aspect of the present invention, there is provided an insulating film, a first impurity region of the first conductivity type formed on the insulating film, and a second conductive region formed adjacent to the first impurity region. Channel region, a first conductivity type second impurity region formed adjacent to the first channel region, and a second conductive region formed adjacent to the second impurity region. The second of the mold
A first conductive type third impurity region formed adjacent to the second channel region;
A first gate insulating film formed on the first channel region; a second gate insulating film formed on the second channel region; and a first gate insulating film formed on the first gate insulating film. A gate electrode, a second gate electrode formed on the second gate insulating film, and the second gate electrode between at least one of the first impurity region and the third impurity region and the insulating film. A semiconductor device comprising a fourth impurity region of a second conductivity type having a higher impurity concentration than the first and second channel regions.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. 1 is a sectional view of the semiconductor device according to the first embodiment, FIG. 2 is a sectional view, FIG. 3 is a plan view, and FIG. 4 is a circuit diagram. 1 and 2 show cross-sectional structures along AA 'and BB' in FIG. 3, respectively. FIG. 4 shows a circuit diagram including a NAND circuit. FIG. 2 does not include a contact electrode (17) to the gate and a contact electrode (18) to the back gate formed on the A-side extension of the BB ′ cross section, It is illustrated for explanation.

Next, reference numerals used in this embodiment will be described. 1 is an n-type region, 2 is a p-type region, 3 is an insulating film on a gate side wall, 4 is a channel region, 5 is a support substrate, 6 is SO
I is a buried insulating film, 9 is a gate insulating film, 10 is a gate electrode, 11 is a source / drain region, 12 is an interlayer insulating film, 13 is an element isolation insulating film, 14 is a contact, and 15 is a transistor connected in series. The source / drain regions 16 and 16 'are contacts for the SOI Si film, 16''is a contact for the gate electrode 10, 17 is an electrode for the SOI Si film, and 18 is an electrode for the support substrate 5.

Hereinafter, a specific configuration example will be described. Here, the configuration of the n-type MISFET will be described. For example, P, As, Sb doped with 10 ¹⁵ to 10 ¹⁸ cm ^-3 , for example, Si
Alternatively, a buried insulating film 6 made of, for example, a silicon oxide film or a silicon nitride film is formed to a thickness of 10 to 1000 nm on a support substrate 5 made of an n-type semiconductor made of SiGe. Then, on the buried insulating film 6, for example, p-type silicon or boron to which boron or indium is added at 10 ¹⁵ to 10 ¹⁸ cm ^-3
A SOI substrate is formed from a semiconductor layer made of p-type SiGe and having a thickness of 1 to 300 nm. Then, for example, a silicon oxide film is formed on the semiconductor layer including the channel region 4,
A gate insulating film 9 made of a silicon nitride film, a silicon oxynitride film, a tantalum oxide film, a titanium oxide film, or a strontium titanium oxide film and having a thickness of 1 to 200 nm. Doped polycrystalline silicon film or TiN, TaN, W, Al
A gate electrode 10 formed by depositing a thickness of about 300 nm is formed.
The gate electrode 10 is formed with a width of, for example, 0.01 to 1 μm. Then, in the semiconductor layer on which the channel region 4 is formed,
For example, n-type source / drain regions 11, 11 ', and 11''to which P, As, or Sb is added at 10 ¹⁶ to 10 ²¹ cm ^-3 are formed on both sides of the gate, and these gate electrodes 10, channel regions 4, And the source / drain regions 11, 11 ', 11''
Transistors Qn1 and Qn2 are formed. In order to improve the electrical separation between the gate electrode 10 and the source / drain regions 11, 11 ', 11'', an insulating film made of, for example, a silicon oxide film or a nitride film is provided on the steep side surface of the gate region. Membrane 3
Is formed with a side thickness of 5 to 200 nm.

The drain region of Qn1 and the source region of Qn2 are composed of the same n-type impurity region 11 '(15 in FIG. 3), forming a gate array structure in which two transistors are connected in series. ing.

In the support substrate 5, for example, B or In
A p-type region 2 doped with 10 ¹⁶ to 10 ¹⁸ cm ⁻³ is formed. this
The p-type impurity region 2 is in contact with the buried insulating film 6. Then, for example, P, As or Sb is added to the region facing the channel region of Qn1 and Qn2 in the p-type impurity region 2 by 10 ¹⁶ to 10 ²¹ cm.
^The back gate electrodes 1, 1 'made of the n-type impurity added with ^-3 are formed. The back gate electrodes 1 and 1 ′ are formed in contact with the buried insulating film 6 and have channel regions 4 and 4 of the SOI layer.
The potential of 4 ′ can be changed by adjusting the potential of the back gate electrode. Then, the voltage node 18 of FIG. 2 is formed on the back gate electrodes 1, 1 ',
It is possible to apply a voltage. Further, the back gate electrodes 1 and 1 ′ are each surrounded by the p-type impurity region 2 and do not come into contact with the n-type support substrate 5. Thus, a reverse bias is applied between the p-type region 2 and the back gate electrode 1 and between the p-type region 2 and the back gate electrode 1 ′, so that they are electrically separated. Therefore, different voltages can be applied to the back gate electrode 1 and the back gate electrode 1 '.

Further, the p-type region 2 forms a pn junction with the n-type support substrate 5 and applies a reverse bias between them, thereby forming a pn junction between the support substrate 5 and the p-type region 2. Electrical isolation can be provided. This allows the p-type region
2 can be set independently of the support substrate 5, and the voltage can be set independently of the support substrate 5 so as to reduce the capacitance between the back gate electrode 1 and the p-type region 2. Therefore, in the present embodiment, it is important that the forward bias condition is not applied between the back gate electrode 1 or 1 'and the p-type region 2, but these back gate voltages are positive or negative with respect to the source voltage. Even if biased, the voltage of p-type region 2 is made more negative than the voltages of regions 1 and 1 ', and further adjusted to be more negative than 0V, so that the forward bias condition is maintained while the potential of substrate 5 is kept at 0V. Can be avoided. Therefore, the capacitive coupling between the back gate and the substrate is weakened, so that a voltage change due to the capacitive coupling between the back gates and a latch-up effect due to minority carrier injection can be reduced. Further, since there is no need to bias the supporting substrate 5 having a large capacitance between the substrate and the package, power consumption of the substrate bias circuit can be suppressed.

According to the configuration of the semiconductor structure of the present embodiment,
In a semiconductor device having a gate array structure, a back gate electrode 1 is provided on a support substrate 5 facing a channel region 4 of each transistor, and independent back gate voltages VB1 and VB2 can be applied to each. Therefore, the threshold value of each transistor can be controlled by the back gate voltage. Further, the back gate electrode is formed in the support substrate region facing the channel region, and the source / drain regions 11, 11 ', 11''
A p-type region 2 having a conductivity type opposite to the conductivity type of the source / drain regions 11, 11 ', and 11''is formed opposite to the p-type region. When a potential is applied to the source / drain regions 11, 11 ', 11'', the p-type region 2 and the n-type source / drain regions 11, 11', 1
1 '', the depletion layer is formed in the region 2 where the concentration of the p-type impurity is low. Therefore, the parasitic capacitance between the source / drain region 11 and the back gate can be reduced as compared with the structure using the back gate electrode shown in FIG. Further, since the parasitic capacitance can be reduced, the impedance of the signal transmitted from the drain electrode to the support substrate 5 and the back gate electrodes 1, 1 'can be reduced, and the crosstalk between devices can be further reduced.

Next, an example will be described in which a problem on the circuit is solved by back gate control in the semiconductor device of this embodiment. FIG. 4 shows a circuit diagram of a so-called NAND circuit, which includes two p-type MISFET transistors Qp1 and Qp2 connected in parallel and two n-type MISFET transistors Qn1 and Qn2 connected in series. The above-mentioned back gate electrode is formed on the n-type MISFETs Qn1 and Qn2, and the back gate voltages VB1 and VB2 can be applied to Qn1 and Qn2, respectively.

In this circuit configuration, the source voltage of Qn2 rises from 0V by Vs when Qn1 and Qn2 are conducting due to the series resistance of Qn1. On the other hand, the source voltage of Qn1 is grounded and is 0V. Therefore, the source voltage of Qn2 becomes higher than that of Qn1.

For this reason, for example, in the circuit configuration of FIG.
When a back gate voltage (VB1 = VB2) equal to Qn1 and Qn2 is applied from a voltage source, the back gate potential measured from the source potential applied to each of the transistors Qn1 and Qn2 is QB1 (= VB2). However, Qn2 is (VB2 −V
s), and the back gate voltage of Qn2 becomes smaller than that of Qn1.

By the way, the threshold value of the fully depleted SOI-MISFET is expressed by the following formula when the region of the channel region in contact with the buried oxide film of the SOI layer (hereinafter referred to as back surface) is depleted. .

Vth1, depl2 = Vth1, acc2-CSiCOX2 (VG2-VG2, acc) / {Cox1 (CSi + COX2)} (1) where VG2, acc <VG2 <VG2, inv In the equation (1), Vth1, acc2 Indicates the threshold of the transistor when the back surface is in the accumulation state, and Csi,
Cox1 and Cox2 are the capacitance of the SOI layer, gate insulating film and buried insulating film, respectively, Vg2 is the back gate voltage, and VG2, ac
c, VG2, inv indicate the back gate voltage when the back surface is accumulated and inverted.

FIG. 7 is a graph showing the dependence of the threshold voltage on the back gate voltage in the fully depleted MISFET. The threshold value of the fully depleted MISFET can be changed in a range from the accumulation to the inversion state of the back surface of the SOI layer by applying a back gate voltage.

Therefore, in the circuit configuration of FIG. 4, Qn1, Qn
2 is composed of transistors with the same threshold, and when the back gate voltages (VB1 = VB2) equal to each other are input from the voltage source, the effective back gate voltage of Qn2 is the potential difference between the source electrode and the back gate voltage. I.e.
Vg2 = (VB1-Vs), and the back gate voltage of Qn1 is
VB1. Therefore, the threshold value of Qn2 becomes larger than the threshold value of Qn1 by CsiCox2Vs / {Cox1 (Csi + Cox2)}, which causes a problem that the transistor operation differs between Qn1 and Qn2.

In the structure of this embodiment, the back gate voltage can be independently applied to each transistor. Therefore, such a problem is solved by using the structure of the present embodiment. That is, by controlling the back gate voltages of Qn1 and Qn2, it is possible to equalize the threshold values of Qn1 and Qn2.

Specifically, the back gate voltage VB2 applied to Qn2 is changed to the back gate voltage VB applied to Qn1.
For 1, VB2 = VB1 + Vs (2) where VG2, acc <VB2 <VG2, inv. As a result, the potential difference between the source electrode of Qn2 and the back gate electrode becomes equal to that of Qn1.
The thresholds of 1 and Qn2 are equal. That is, by adding the increase in the source voltage of Qn2 to the back gate voltage, Qn2
Can achieve the same threshold value as Qn1. Therefore, the amount of change in the threshold value with respect to the SOI film thickness change can be made the same for Qn1 and Qn2, and a transistor integrated circuit with more uniform characteristics can be realized. FIG. 8 shows Qn
2 is a graph showing the relationship between a change in the source voltage Vs and a back gate voltage VB2 that realizes no change in the threshold value with respect to a change in the source voltage Vs. VB2 corresponding to the straight line in the graph against the source voltage Vs
Is input to the back gate to make the thresholds of Qn1 and Qn2 equal. By inputting VB2 larger than this straight line to the back gate, the threshold value of Qn2 becomes smaller than that of Qn1.

Further, by providing a control circuit for controlling the back gate voltage as shown in FIG. 5, it is possible to suppress a threshold variation due to a change in the source voltage of Qn2. FIG. 5 is a circuit diagram of a semiconductor device having a voltage supply control circuit 8 for setting a back gate voltage to be applied by feedback-controlling the source voltage Vs of Qn2. The control circuit 8 monitors the source voltage Vs of Qn2, sets the back gate voltage VB2 satisfying the equation (2), and sets the transistor Qn2.
Input to the back gate electrode. With this control circuit, fluctuations in the threshold value of Qn2 can be suppressed by back gate voltage control.

By the way, since the source voltage of Qn2 becomes Vs, the effective gate voltage input to Qn2 is also (VDD−V
s), which is lower than the Qn1 gate voltage VDD.
This causes a problem that the current driving capability of Qn2 decreases and the gate delay time increases.

The drain current Idsat in the saturation region is represented by the following equation. Idsat = 1/2 · W / L · µeff · Cox · (Vgs-Vth) 1.3-2 (3) In equation (3), W is the gate width, L is the gate length, and μef
f is the mobility, Cox is the capacitance of the gate insulating film, Vgs is the gate voltage with reference to the source potential, and Vth is the threshold value of the transistor.

As can be seen from equation (3), the current driving capability of the transistor is represented by a function of the gate voltage. As the gate voltage increases, the current driving capability also increases. Therefore, in the circuit configuration of FIG. 22, when Qn1 and Qn2 perform the same threshold value operation, the gate voltage of Qn2 decreases by Vs as described above, and the current driving capability is lower than that of Qn1.

The signal propagation delay time τ is expressed by the following equation. τ = Cload · VDD / Idsat (4) In Equation (4), Cload represents a load capacity.

The propagation delay time τ is the saturation drain current Idsat
The delay time increases as the saturation drain current decreases. Thus, when VB1 = VB2 in FIG. 22, that is, when VB1 = VB2 in FIG. 4, the current drive capability of Qn2 is smaller than that of Qn1, so that the transition time until Qn2 is turned on is longer than that of Qn1. The occurrence of a difference in transition time due to such a difference in input terminals poses a problem in circuit timing design.

Hereinafter, a back gate control method for solving such a problem in the present embodiment will be described. As mentioned above,
The current drive capability is proportional to (Vgs-Vth) 1.3-2. Therefore, when the threshold values of Qn1 and Qn2 are equal (Vth1 = Vth2) in the circuit configuration of FIG. 4, the current driving capability of Qn2 is smaller than that of Qn1 because the gate voltage is smaller than that of Qn1 by Vs. Become smaller.

Therefore, in order to make the current driving capabilities of Qn1 and Qn2 equal, the reduction is achieved by compensating the decrease Vs of the gate voltage input to Qn2 with a threshold value. In other words, the threshold Vth2 of Qn2 is set to Vth2 'by back gate voltage control.
= Vth 1−Vs to realize a current driving capability equal to Qn1. The back gate voltage VB2 ′ required to realize Vth 2 ′ = Vth 1−Vs satisfies the following equation.

VB2 '(Vs) = Vs / γ + VB1 (5) In equation (5), γ is γ = CsiCox2 / {Cox1 (Csi +
Cox2)}, which can be approximated as tox1 / tox2. tox1 and tox2 represent the thicknesses of the gate insulating film and the buried insulating film. Therefore, the back gate voltage VB2 'for keeping the current driving capability constant is determined by the source voltage Vs and the thickness ratio of the gate insulating film and the buried insulating film.

FIG. 9 is a graph showing the relationship between the source voltage Vs of Qn2 and the back gate voltage VB2 'necessary to make the current driving capability equal to Qn1. In a circuit in which Qn1 and Qn2 are formed with equal threshold values, it is possible to make the current driving capabilities substantially equal by applying the back gate voltage VB2 'satisfying the expression (5). In other words, in FIG. 9, by applying the back gate voltage VB2 ′ corresponding to the straight line in the graph to Vs, it is possible to make the current driving capabilities substantially equal. However, the transistor control is performed in a range where the back surface is in a depleted state, that is, when the back gate voltage VB2 ′ is VG2, acc <VB2 ′ <VG2, inv
It is possible within the range.

The above-described control circuit 8 shown in FIG. 5 may be used as a control circuit for keeping the current driving capability constant. That is, the source voltage Vs of Qn2 is fed back, and a back gate voltage VB2 'satisfying FIG. 9 is set and applied to Qn2. Thereby, it is possible to form a semiconductor device in which the current driving capability does not change with respect to the Vs fluctuation.

Here, it can be seen that VB2 <VB1 should be satisfied in order to improve the effect of either of the equations (2) and (5), that is, to improve the current driving capability of Qn2 as compared with the conventional example. Here, to control VB2, as shown in FIG. 4 (b), Qn1 and
A back gate voltage VB2 may be obtained from a source voltage obtained by a dummy circuit formed by connecting transistors Qn1 ′ and Qn2 ′ equivalent to Qn2 in series, and VB2 may be commonly used for a plurality of NAND circuits.
You may give 2.

According to the structure of this embodiment, the following effects can be obtained. (1) As shown in FIG. 1, in the present embodiment, a back gate electrode is provided in a support substrate facing a channel region of each transistor in a semiconductor device having a gate array structure. Is such that a depletion layer is formed on the supporting substrate. Therefore, since the parasitic capacitance between the source / drain region and the supporting substrate is reduced, for example, the operation power consumption is reduced and the S factor is reduced. Then, the signal propagation delay time can be reduced. Thus, it greatly contributes to low power consumption and high speed.

(2) Since the back gate electrode provided for each transistor is formed electrically separated from the back gate electrode of an adjacent transistor, the transistors are controlled by individually applying a back gate voltage. It is possible.

Further, according to the control example of the present embodiment, the following effects can be obtained. (3) As shown in FIG. 8, by controlling the back gate voltage of Qn2, it is possible to suppress the increase in the threshold value due to the increase in the source voltage of Qn2 and make it equal to the threshold value of Qn1. Therefore, for example, the delay time in the triode operation can be shortened, and the margin of the operation time of the logic circuit in the triode operation is reduced, and high-speed operation is realized. Further, as shown in the circuit configuration of FIG. 5, by controlling the back gate voltage by feeding back the change in the source voltage of Qn2, a semiconductor device with small threshold variation can be realized.

(4) As shown in FIG. 9, by controlling the back gate voltage of Qn2, it is possible to suppress a decrease in current driving capability due to a decrease in the source voltage of Qn2.
Therefore, the signal propagation delay time is suppressed in the logic circuit,
Achieve high-speed operation. In addition, the difference between the maximum value and the minimum value of the switching time can be suppressed, and the operation speed of the circuit can be made more uniform.

FIG. 10 is a structural plan view of a second embodiment of the present invention. FIG. 10 is a top view in which a wiring layer and a contact layer are omitted, and FIGS. 11, 12 and 13 are cross-sectional views taken along arrows AA ', BB', and CC 'in FIG. 10, respectively. The same parts as those in the first embodiment are denoted by the same reference numerals, and detailed description is omitted. This embodiment differs from the first embodiment in the method of controlling the threshold value and the back gate structure of the transistors connected in series, and discloses a so-called gate array configuration method. In the present embodiment, the support substrate 5 is formed of a p-type semiconductor, and an n-type region 2 and an n-type region 2 ′ are formed in the support substrate 5. They are,
10 are electrically isolated from each other by the p-type region 5 of FIG.

As shown in FIG. 11, a p-type region 1 is formed so as to be surrounded by an n-type region 2. This p-type region 1
Is electrically separated from the supporting substrate 5 by the n-type region 2. These p-type region 1 and n-type region 2
It works as the back gate electrode of SFET.

A plurality of p-type MISFETs are formed for one semiconductor island region facing the p-type region 1 and the n-type region 2 acting as a back gate electrode with the insulating film 6 interposed therebetween. In the present embodiment, an example is shown in which two semiconductor island regions are formed, but more semiconductor island regions may be formed. Here, the adjacent p-type MISFET formed in one semiconductor island region is connected to the source / drain region 15 made of the p-type semiconductor shared by the transistors connected in series.
It has. Further, a region 11 made of a p-type semiconductor is formed facing the p-type region 15 with the gate electrode 10 interposed therebetween. These regions 15 and 11 are p-type MISFETs.
The source region and the drain region, or the drain region and the source region. Further, the region 4 made of n-type or p-type impurity addition of 1016 cm−3 or less
It is formed with a gate electrode 10 and a gate insulating film 9 interposed
This is the channel region of the MISFET.

As shown in FIG. 12, a p-type region 1 'is formed so as to be surrounded by an n-type region 2'. This p-type region 1 '
Is electrically separated from the supporting substrate 5 by an n-type region 2 '. These p-type regions 1 'and n-type regions 2'
It works as a back gate electrode of SFET.

A plurality of n-type MISFETs are formed for one semiconductor island region facing the p-type region 1 'and the n-type region 2' acting as a back gate electrode with the insulating film 6 interposed therebetween. . In the present embodiment, an example is shown in which two semiconductor island regions are formed, but more semiconductor island regions may be formed. Here, the adjacent n-type MISFET formed in one island-shaped semiconductor region is a source-drain region 1 made of an n-type semiconductor shared by the transistors connected in series.
5 '. Furthermore, n
A region 11 'made of an n-type semiconductor is opposed to the mold region 15'.
Are formed. These regions 15 and 11 '
Forms a source region and a drain region or a drain region and a source region of an n-type MISFET. Further, a region 4 'made of p-type or doped with n-type impurity of 10 ¹⁶ cm ^-3 or less is formed with the gate electrode 10' and the gate insulating film 9 interposed therebetween, and serves as a channel region of the n-type MISFET.

Here, it is desirable that the n-type MISFET and the p-type MISFET are formed in an array as shown in FIG. 10 in order to form a multi-stage logic circuit by connecting metal wirings. In this case, by forming the structure of FIG. 10 in an array on the left and right sides of the paper, the semiconductor regions 1, 1 ′ serving as a back gate are formed.
2, 2 'are connected in series, and without forming a voltage application terminal at the back gate of each individual array, for example, by forming a voltage application terminal at the end of the array, all of the continuously formed A voltage can be applied to the back gate of the array.

Here, the gate electrodes 10 and 10 'may be semiconductors having different conductivity types for controlling the threshold. Specifically, as the gate electrode 10, 10
¹⁹ cm ^-3 or more B is a polysilicon electrode added with, as the gate electrode 10 'may be an polysilicon electrode added with 10 ¹⁹ cm ^-3 or more P or As.

On the side surfaces of the gate electrodes 10 and 10 ', an insulating film 3 is formed from, for example, a silicon oxide film or a silicon nitride film. This is to maintain good electrical insulation between the gate electrode 10 and the source / drain region 15 or the source / drain region 11. Furthermore, an element isolation insulating film 13 made of, for example, a silicon oxide film is formed between the semiconductor island regions. Further, an interlayer insulating film 1 made of, for example, a silicon oxide film is formed on the MISFET.
2 are formed.

The feature of this embodiment is that, in the p-type MISFET as shown in FIG. 11, the source / drain region 11 is formed on the support substrate 5 opposed to the channel region 4 via the insulating film 6.
Region 2 having the opposite conductivity to that of the source / drain region 11 is formed on the supporting substrate 5 opposed to the source / drain region 15 shared by the adjacent transistors via the insulating film 6. That is, the p-type region 1 is formed.

Further, complementarily, as shown in FIG.
In the ET, a p-type region 2 'having conductivity opposite to that of the source / drain region 11' is formed on a support substrate 5 opposed to a channel region 4 'via an insulating film 6, and a source shared by adjacent transistors is formed. The source / drain region 1 is provided on the support substrate 5 facing the drain region 15 ′ via the insulating film 6.
This means that an n-type region 1 'having the same conductivity as 1' is formed.

With such a structure, two transistors whose threshold values change depending on the direction of the current flowing through the source and the drain can be formed in series.
First, referring to FIG. 14, the present back gate structure
Indicates that the threshold changes. FIG. 14A is a cross-sectional view corresponding to the extraction of one n-type MISFET of the present embodiment. The electrodes 17a and 17b are connected to the source / drain regions 11'a and 11'b, respectively. ing. Further, a p-type region 1 'is formed below 11'a and below the channel region via an insulating film 6. here,
The p-type region 1 ′ is electrically connected to the electrode 18 through the high-concentration p-type region 1 ″.
Reference numeral 8 is connected to a voltage source, and the p-type region 1 'is controlled to have a constant voltage. Further, under 11'b, the insulating film 6
An n-type region 2 'is formed via the substrate. Here, the n-type region 2 ′ is electrically connected to the electrode 18 ′ through the high-concentration n-type region 2 ″.
8 'is connected to a voltage source, and the n-type region 2' is controlled to have a constant voltage. Here, in order to prevent a large leak current from flowing through the p-type region 1 ′ and the n-type region 2 ′ in order to suppress the power consumption of the voltage source, the n-type region 2 ′ is compared with the p-type region 1 ′. It is necessary to bias it positively or to bias it below the forward voltage. Therefore, under such conditions, the potential DD ′ on the back gate surface is as shown in FIG.
And the conduction band Ec and the valence band Ev have a structure in which the n-type region 2 ′ is bent downward by the depletion layer including the boundary between the region 1 ′ and the region 2 ′. Therefore, the D side, that is, 11'a
The interface between the channel 4 'and the insulating film 6 close to the
(accumulation) state, and the D 'side, that is, the interface between the channel 4' near 11'b and the insulating film 6 is inverted (inv) of the p-type layer.
ersion) state. Therefore, as shown in FIG. 14 (c), when the electrode 17b is used as the drain electrode and the electrode 17a is used as the source electrode, the pentode threshold value is determined by the maximum point of the potential of the channel portion which determines the threshold value. 1 in 4 '
Since it is formed on the 17a side than on the 7b side, it is difficult to form an inversion layer, and a high threshold value is obtained. On the other hand, FIG.
As shown in (d), when the electrode 17a is used as the drain electrode and the electrode 17b is used as the source electrode, the pentode threshold value is such that the maximum point of the potential of the channel portion that determines the threshold value is:
Since the channel 4 'is formed on the 17b side rather than the 17a side, an inversion layer is easily formed and the threshold value is low. As described above, the threshold value differs depending on the direction of the source / drain electrode even under the same voltage applied to the back gate. In particular, when the transistor is a fully depleted transistor, the depletion layer extending from the back gate portion reaches the channel portion, so that the threshold value greatly changes depending on the back gate potential, which is a desirable mode for this embodiment.

Hereinafter, the direction is indicated by a black circle on the side of the source electrode under the condition that the threshold value becomes higher when the source electrode is used as the source electrode. As apparent from the above description, in order to form a difference in the threshold value, the potential of the back gate electrode facing the channel 4 'only needs to be asymmetric with respect to the source and drain. Therefore, the boundary between the p-type region 1 'and the n-type region 2' may be formed not at the position facing the source region but at the position facing the channel 4 '. Similarly, for the p-type MISFET, the boundary between the p-type region 1 and the n-type region 2 may be formed not at the position facing the source region but at the position facing the channel 4.

Next, an example of a logic circuit using the transistor of this embodiment is shown in FIG. FIG. 15 (a) shows the static
FIG. 15B is a circuit diagram for a 2-input NAND, and FIG. 15B is a circuit diagram for a static 2-input NOR. Further, FIG.
6 (a) is a static 2-input NA corresponding to FIG. 15 (a).
10 shows a layout of a wiring layer with respect to ND, and uses the transistor arrangement of FIG. FIG. 16 (b)
FIG. 16A shows a layout of a wiring layer corresponding to the static 2-input NOR corresponding to FIG. 16A, and uses the transistor arrangement of FIG.

First, in FIGS. 15 (a) and 16 (a), Qn1 and Qn2 are n-type MISFETs having different thresholds according to the above-mentioned current directions, and Qp1 and Qp2 are threshold currents according to the above-described current directions. Are different p-type MISFETs. They are,
It is desirable that they are formed facing each other as shown in FIG. In FIG. 16A, 1
7, 17 'and 17 "denote metal wires made of W, Cu or Al, 17' is connected to VDD, and 17" is
Connected to 0V. 26 indicates a contact electrode for the p-type source / drain electrode 11 or 15, 26 ′ indicates a contact electrode for the n-type source / drain electrode 11 ′ or the source / drain electrode 15 ′, and 26 ″ indicates A contact electrode for the gate electrode 10 or 10 ', 10''is shown.

Here, the drain electrode on the side other than the common electrode of Qn2 is connected to the output node. Further, a source electrode serving as a common electrode of Qn2 is connected to a drain electrode of Qn1. In addition, the source electrode of Qn1 is connected to GND and
5 is connected to the indicated voltage node 17 ″ having 0V. Further, the gate electrode of Qn1 is connected to the gate electrode of Qp1, and serves as a first voltage input terminal (IN1). Further, the gate electrode of Qn2 is connected to the gate electrode of Qn1, and serves as a second voltage input terminal (IN2). Further, the source electrodes of Qp1 and Qn1 are both connected to a voltage node having a voltage of VDD, for example, and the drain electrodes are connected to an output node. In other words, this configuration shows a logic circuit of a two-input NAND, and IN1, IN2,
OUT operates to have a voltage corresponding to two logical values of approximately 0V and approximately VDD. In FIG. 15, the voltages V1, V2, V3, and V4 are applied to the regions 2 ', 1', 2, 1 as the back gate, respectively. Here, in order to prevent a current from flowing due to a forward bias between the back gates, satisfy the conditions of V3> V4-Vi and V1> V2-Vi with the built-in voltage between the back gates as Vi. Is required.

In this circuit configuration, the source electrode of Qn2 is connected to the input voltage of Qn1 and Qn2 because of the series resistance of Qn1.
When conducting at VDD, it rises by Vs from 0V. On the other hand, the source electrode of Qn1 is connected to 0V,
The source voltage of Qn2 is higher than that of 1. For this reason,
When a transistor having a threshold value equal to Qn1 and Qn2 is used, the current driving capability of Qn2 is reduced as compared with the current driving capability of Qn1 by reducing the gate voltage by (VDD-Vs). Therefore, the transition time when turning on Qn2 is
The transition time is longer than the transition time when Qn1 is turned on, and the transition time differs due to the difference between the input terminals, which is a problem in circuit timing design.

Here, as described in the first embodiment, in order to suppress the decrease in the current driving capability of Qn2 with respect to Qn1 due to the increase in the source voltage, the threshold value Vth2 of Qn2 is set to
A condition for lowering the threshold value Vth1 of Qn1 is required. In particular, if Vth2 = Vth1-Vs, the current driving capabilities of Qn2 and Qn1 become almost equal, and the delay time can be made almost equal regardless of the input terminal.

Here, in the present embodiment, the current direction of Qn2 is the direction in which the threshold value becomes lower, and the current direction of Qn1 is the direction in which the threshold value becomes higher. This condition can be satisfied by adjusting the voltages V1 and V2. At this time, the p-type MISFET Qp1
In Qp2 and Qp2, current flows in the direction in which the threshold value increases. Therefore, the transition times when the two p-type MISFETs are turned on are substantially equal, and the difference between the transition times caused by the difference between the input terminals does not change even when the back gate voltages V1 and V2 are changed. That is, to reduce the difference between the input terminals of the delay time of the two-input NAND circuit, the transition time when Qn1 is turned on is reduced.
V1 and Qn2 are set to be almost equal to the transition time when
What is necessary is just to control V2.

On the other hand, in FIGS. 15 (b) and 16 (b), Qn1 and Qn2 are n-type MISFETs having different thresholds according to the above-mentioned current directions, and Qp1 and Qp2 are threshold currents according to the above-described current directions. Are different p-type MISFETs. They are,
It is desirable that they are formed facing each other as shown in FIG. In FIG. 16 (b), 1
7, 17 'and 17 "denote metal wires made of W, Cu or Al, 17' is connected to VDD, and 17" is
Connected to 0V. The drain electrode of Qp2 is connected to the output node. The source electrode of Qp2 is connected to the drain electrode of Qp1. Further, the source electrode of Qp1 is connected to a voltage node having, for example, VDD. Further, the gate electrode of Qp1 is connected to the gate electrode of Qn1, and serves as a first voltage input terminal (IN1). Further, the gate electrode of Qp2 is connected to the gate electrode of Qn2 and serves as a second voltage input terminal (IN2). Further, the source electrodes of Qn1 and Qn2 both
And the drain electrode is connected to the output node. In other words, this configuration shows a two-input NOR logic circuit, and includes IN1, IN2, OU
T operates to have a voltage corresponding to two logical values of approximately 0V and approximately VDD.

In FIG. 15, voltages V1, V2, V3, and V4 are applied to regions 2 ', 1', 2, and 1 as a back gate, respectively. Here, in order to prevent the current from flowing due to the forward bias between the back gates,
Assuming that the built-in voltage is Vi, it is necessary to satisfy the conditions of V3> V4-Vi and V1> V2-Vi.

In this circuit configuration, the source electrode of Qp2 is connected to the input voltage of Qp1 and Qp2 because of the series resistance of Qp1.
In the state of conduction at 0V, the voltage drops by Vs below VDD. On the other hand, the source electrode of Qp1 is connected to 0V,
The source voltage of Qp2 is lower than that of 1. For this reason,
When a transistor having a threshold value equal to Qp1 and Qp2 is used, the current driving capability of Qp2 is reduced as compared with the current driving capability of Qp1 by increasing the gate voltage by Vs. Therefore, the transition time when turning on Qp2 is
The transition time is longer than the transition time when Qp1 is turned on, and a difference in the transition time occurs due to the difference between the input terminals, which is a problem in circuit timing design.

Here, as described in the first embodiment, in order to suppress the decrease in the current driving capability of Qp2 with respect to Qp1 due to the increase in the source voltage, the threshold value Vth3 of Qp2 must be changed.
A condition for lowering the threshold value Vth4 of Qp1 is required. In particular, if Vth4 = Vth3-Vs, the current driving capabilities of Qp2 and Qp1 become almost equal, and the delay times can be made almost equal regardless of the input terminal.

In this embodiment, since the current direction of Qp2 is the direction in which the threshold value decreases and the current direction of Qp1 is the direction in which the threshold value increases, the back gate of the p-type MISFET is This condition can be satisfied by adjusting the voltages V3 and V4. At this time, n-type MISFET Qn1
A current flows in both Qn2 and Qn2 in the direction in which the threshold value increases. Therefore, the transition times for turning on the two n-type MISFETs are substantially equal, and the difference in transition time caused by the difference between the input terminals does not change even when the back gate voltages V3 and V4 are changed. In other words, to reduce the difference between the input terminals of the delay time of the two-input NOR circuit, the transition time when Qp1 is turned on is changed to Qp2.
V3 and V4 may be controlled so as to be substantially equal to the transition time at the time of ON.

As described above, the NAND circuit of this embodiment and the NO
Even if the R circuit is formed on the same substrate and shares the back gate terminal, the difference in transition time caused by the difference between the input terminals can be minimized by controlling V1, V2, V3 and V4 independently. can do. Therefore, in a logic circuit in which these are combined with a one-input inverter, it is possible to minimize a delay time shift caused by a difference between input terminals.

FIG. 17B is a circuit diagram for a clocked inverter, and FIG. 17A shows a layout of a wiring layer for the clocked inverter corresponding to FIG. The arrangement is used. In FIGS. 17 (a) and 17 (b), Qn1 and Qn2 are n-type MISFETs having different thresholds depending on the current direction described above, and Qp1 and Qp2 are p-type MISFETs having different thresholds depending on the current direction described above. It is. These are desirably formed to face each other as shown in FIG. 17A in order to suppress wiring delay. In FIG. 17 (a), 17, 17 'and 1
7 "indicates a metal wiring made of W, Cu or Al, and 17 '
Is connected to VDD, and 17 "is connected to 0 V. Here, the drain electrode on the side other than the common electrode of Qn2 is connected to the output node. Also, the source electrode serving as the common electrode of Qn2 is connected to the output node. , Qn1. The source electrode of Qn1 is connected to GND and a voltage node 17 ″ having 0 V shown in FIG. 15. Further, the non-common electrode of Qp2 is connected to GND. The drain electrode of Qp1 is connected to the output node, the source electrode serving as the common electrode of Qp2 is connected to the drain electrode of Qp1, and the source electrode of Qp1 is denoted by GND in FIG. Connected to a voltage node 17 ″ having 0V.

The gate electrode of Qn2 is connected to the gate electrode of Qp2 and serves as a voltage input terminal (IN) of the inverter. In addition, the gate electrode of Qn1
The gate electrode of Qp1 is connected to the inverted input of the clock input / fai. In other words, this configuration is
When fai is VDD and / fai is 0V, inverted output of IN is obtained.
The logic circuit of a clocked inverter whose output is in a high impedance state when i is 0 V and / fai is VDD,
IN, fai, / fai, and OUT operate to have voltages corresponding to two logical values of approximately 0 V and approximately VDD. In FIG. 15, the regions 2 ′, 1 ′,
The voltages V1, V2, V3, and V4 are applied to 2,1, respectively. Here, in order to prevent forward current due to forward bias between back gates, build-in between back gates
Assuming that the voltage is Vi, it is necessary to satisfy the conditions of V3> V4-Vi and V1> V2-Vi.

In this circuit configuration, the source electrode of Qn2 is connected to the input voltage of Qn1 and Qn2 because of the series resistance of Qn1.
When conducting at VDD, it rises by Vs from 0V. For this reason, the current driving capability of Qn2 is reduced correspondingly to the fact that the gate voltage is reduced by (VDD-Vs) as compared with the case where the source electrode of Qn2 is grounded to 0V. On the other hand, the source electrode of Qp2 becomes lower than VDD by Vs when the input voltages of Qp1 and Qp2 are conducting at 0V due to the series resistance of Qp1. Therefore, the current driving capability of Qp2 is reduced, corresponding to increasing the gate voltage by Vs, as compared with the case where the source electrode of Qp2 is connected to VDD. Therefore, as compared with a normal inverter in which the source electrode of Qp2 is connected to VDD and the source electrode of Qn2 is connected to 0V, the delay time of this inverter is longer even with the same transistor dimensions. Also, Qp2
The clock signal fa
As compared with the inputs to i and / fai, the delay time of the output signal with respect to the signal applied to IN increases, which causes a problem in circuit timing design.

Here, as described in the first embodiment, in order to suppress the decrease in the current driving capability of Qn2 with respect to Qn1 due to the increase in the source voltage, the threshold value Vth2 of Qn2 is set to
A condition for lowering the threshold value Vth1 of Qn1 is required. In particular, if Vth2 = Vth1-Vs, the current driving capabilities of Qn2 and Qn1 become almost equal, and the delay time can be made almost equal regardless of the input terminal. Furthermore, Qp2
In order to suppress the decrease in current drive capability with respect to Qp1, Qp2
Is required to make the threshold value Vth3 of Qp1 lower than the threshold value Vth4 of Qp1. In particular, if Vth4 = Vth3-Vs, Qp2
And Qp1 have almost the same current driving capability, and the delay time can be made almost equal regardless of the input terminal.

In this embodiment, since the current direction of Qn2 is the direction in which the threshold value decreases and the current direction of Qn1 is the direction in which the threshold value increases, the back gate of the n-type MISFET is This condition can be satisfied by adjusting the voltages V1 and V2. Further, in the present embodiment,
The current direction of Qp2 is the direction in which the threshold decreases,
Since the current direction of 1 is the direction in which the threshold increases,
This condition can be satisfied by adjusting the back gate voltages V3 and V4 of the p-type MISFET.

From the above, the output delay time of the input IN is compared with the output delay time for the clock inputs fai and / fai.
It can be equal or shorter, and a faster switching inverter can be formed.

The feature of suppressing the deterioration of the current driving capability when cascade-connected transistors whose thresholds differ depending on the direction of current flow is not limited to the static logic circuit described above, but also to a multi-input circuit. The present invention can also be used for a logic circuit or a dynamic circuit, and can reduce the difference in delay time depending on the input terminal.

According to the present embodiment, the following effects can be obtained. (1) The regions 1, 1 ', 2, 2' acting as a back gate electrode of the transistor are electrically isolated from the supporting substrate 5. Therefore, the region to which the back gate is applied can be smaller than the entire chip, and the capacitance of the regions 1, 1 ', 2, 2' can be reduced. Therefore, a power supply having a smaller capacity can be used as the substrate bias power supply connected to the regions 1, 1 ', 2, 2', and the circuit area and power consumption of the substrate bias power supply can be reduced. Further, the influence of noise through the substrate is reduced, and a low-noise circuit can be stably realized.

(2) By controlling the voltage of the n-type region 2 and the voltage of the p-type region 1 acting as the back gate electrode in FIG. 11, the threshold value of the p-type MISFET and the source and drain currents The difference in threshold value depending on the direction can be controlled. Further, by controlling the voltages of the n-type region 2 'and the p-type region 1' acting as the back gate electrode in FIG. 12, the threshold value of the n-type MISFET and the threshold value according to the current direction of the source and drain are controlled. Can be controlled independently. Therefore, for example, after the semiconductor element is formed up to the wiring layer and enters an actual operation state, the difference in threshold value can be controlled by external voltage input, and the delay time of the logic circuit can be optimized.

(3) The difference between the maximum delay and the minimum delay of the NOR or NAND circuit and the clocked inverter logic circuit can be reduced without changing the wiring layout pattern. Therefore, the time required for the synchronization margin of the logic circuit can be further reduced, and the logic circuit can be operated at higher speed.

(4) As a back gate of the MISFET, a back gate of the same conductivity type as the source / drain region is formed on the entire lower surface of the source / drain layer and the channel layer. The capacitance of one of the source / drain layers on which the back gate is formed with respect to the back gate can be reduced. In particular, when a back gate of the opposite conductivity type is formed in the drain region,
When the drain voltage is high, the back gate region is depleted, so that the drain capacitance with respect to the back gate is reduced, the load capacitance of the output of the logic circuit connected to the drain is reduced, and high-speed operation can be performed.

On the other hand, the depletion of the back gate region facing the channel is smaller than in the case where the back gate of the conductivity type opposite to that of the source / drain region is formed on the entire lower surface of the source / drain layer and the channel layer. The channel potential can be kept constant, and the threshold value does not easily decrease even when the gate length is reduced.

(5) As shown by regions 1 and 2 'in FIG. 10, a semiconductor region having one conductivity type serving as a back gate can be shared by two transistors. Therefore, even if the gate length is shorter than the length of the source / drain region along the gate length, the length of the regions 1 ′ and 2 ′ in the channel direction can be secured wider than the gate length.
For this reason, the design rule for the back gate can be relaxed compared to the design rule for the gate, and the back gate can be formed using an inexpensive lithography apparatus with lower resolution. In addition, since the widths of the regions 1 ′ and 2 ′ can be kept wide, the back gate resistance can be kept small, and a stable back gate voltage can be applied even if the channel width increases.

FIG. 18 is a plan view showing the structure of the third embodiment of the present invention. FIG. 18 is a top view in which the wiring layer and the contact layer are omitted, and FIGS. 19 (a) and 19 (b) are cross-sectional views taken along arrows AA 'and BB' in FIG. 10, respectively. First and second
The same reference numerals are given to the same portions as those of the embodiment, and the detailed description is omitted. This embodiment is partially different from the second embodiment in the method of controlling the threshold value of the transistors connected in series and the element isolation structure. In FIG. 19, two p-type MISFETs are connected in series, and two n-type MISFETs are connected.
Two Ts in series are formed.

An adjacent p-type MISFET formed in one semiconductor island region shown in FIG. 19A has a source / drain region 15 made of a p-type semiconductor shared by transistors connected in series. Further, a region 11 made of a p-type semiconductor is opposed to the p-type region 15 with the gate electrode 10 interposed therebetween.
Are formed. These regions 15 and 11 are:
A source region and a drain region or a drain region and a source region of the p-type MISFET are formed. further,
A region 4 under the gate electrode 10 and the gate insulating film 9 and doped with an n-type impurity is a channel region of the p-type MISFET. Here, an undepleted region (dotted line in FIG. 19) below the channel region is referred to as a body region 20.

Further, the p-type source / drain regions 11 and n
Below or on the side of the junction with the mold body region 20, for example
A region 19 to which P, As, or Sb is added as an 10 ¹⁸ to 10 ²⁰ cm ⁻³ n-type impurity is formed, and the region 19 is set so as to increase the tunnel leakage current of the pn junction. Here, the region 19 is selectively formed in contact with the source / drain region 11, and is not formed in the shared source / drain region 15 or the dummy source / drain region 11 ″ ′. In addition, area 11
On the side surface on which the gate electrode 10 is not formed, a dummy gate electrode 10 ″ for performing field shield separation is formed. The dummy gate has a dummy source / drain region 11 ′ ″ having the same conductivity type as the dummy 11 in a portion in contact with the element isolation 13 made of, for example, an oxide film.
This is a gate for electrically separating the source / drain region 11 from the source / drain region 11.
This is to reduce the influence of the side leakage along the element isolation 13 and is normally connected to VDD and is in a cutoff state. The dummy gate 10 ″ at the center of the figure is for separating the source / drain regions 11 of the two p-type MISFETs from each other in a field shield, and is normally connected to VDD and is in a cut-off state. FIG. 19 shows four p-type MISs used as circuit elements for one semiconductor island region.
An example in which FETs, that is, Qp1, Qp2, Qp3, and Qp4 are formed is shown. However, by extending the semiconductor island region in the AA ′ direction,
More field shield gates may be formed.

On the other hand, the adjacent n-type MISFET formed in one semiconductor island region shown in FIG. 19B has a source / drain region 15 ′ made of an n-type semiconductor shared by transistors connected in series. I have. In addition, the gate electrode
A source / drain region 11 'made of an n-type semiconductor is formed opposite to the n-type source / drain region 15' with the 10 'interposed therebetween. These regions 15 'and 11'
A source region and a drain region or a drain region and a source region of the n-type MISFET are formed. further,
A region 4 'formed by adding a p-type impurity under the gate electrode 10' and the gate insulating film 9 is a channel region of the n-type MISFET.

Further, n-type source / drain regions 11 'and
'Under or side of the bond and, for example, 10 ¹⁸ to 10 ²⁰ cm as ^-3 n-type impurity B or regions 19 added an In,' p-type body region 20 is formed, the pn junction tunneling leakage The current is set to increase. Here, area 1
9 'is selectively formed in contact with the source / drain region 11', and is not formed in the shared source / drain region 15 'or the dummy source / drain region 11 "". In addition, 1
On the side surface on which the gate electrode 10 'of 1' is not formed, a dummy gate electrode 1 for performing field shield isolation is provided.
0 '' is formed. This dummy gate electrode 10 ''
For example, a dummy source / drain region 11 ″ ″ having the same conductivity type as the dummy 11 ′ in a portion in contact with the side surface of the element isolation 13 made of an oxide film is electrically separated from the source / drain region 11 ′. The gate is for reducing the influence of side leakage along the element isolation 13 between the dummy source / drain region 11 '''' and the substrate 4 ', and is normally connected to 0 V and is in a cutoff state . The dummy gate electrode 10 ″ in the center of the figure is for separating the source / drain regions 11 of the two n-type MISFETs from each other in a field shield, and is normally connected to 0 V and is in a cutoff state.
In FIG. 19, four n-type MISFETs used as circuit elements, ie, Qn1 and Qn
2, an example in which Qn3 and Qn4 are formed is shown, but more may be formed by extending the semiconductor island region in the BB 'direction and forming a field shield gate.

Here, it is desirable that the n-type MISFET and the p-type MISFET are formed in an array as shown in FIG. 18 in order to form a multi-stage logic circuit by connecting metal wirings. Here, the gate electrodes 10 and 10 ′ may be semiconductors having different conductivity types to control the threshold. Specifically, the gate electrode 10 is a polysilicon electrode to which B is added at 10 ¹⁹ cm ⁻³ or more, and the gate electrode 1
As 0 ′, a polysilicon electrode to which P or As is added to 10 ¹⁹ cm ⁻³ or more may be used.

On the side surfaces of the gate electrodes 10 and 10 ', an insulating film 3 is formed of, for example, a silicon oxide film or a silicon nitride film. This is to maintain good electrical insulation between the gate electrode 10 and the source / drain region 15 or the source / drain region 11. Furthermore, an element isolation insulating film 13 made of, for example, a silicon oxide film is formed between the semiconductor island regions. Further, an interlayer insulating film 1 made of, for example, a silicon oxide film is formed on the MISFET.
2 are formed.

The feature of this embodiment is that FIG.
2A, the same conductivity as that of the body region 20 is provided so as to be in contact with the lower portion or the side surface of the p-type source / drain region 11 opposed to the p-type source / drain region 15 shared by the adjacent transistors with the gate electrode 10 interposed therebetween. An n-type semiconductor region 19 having a high impurity concentration is formed, and the resistance at the time of reverse bias between the body region 20 and the source / drain region 11 is smaller than the resistance between the body region 20 and the source / drain region 15. That is what we are doing.

Further, in FIG. 19B, an n-type source / drain region 15 'shared by adjacent transistors
And the body region so as to be in contact with the lower portion or side surface of the n-type source / drain region
A p-type semiconductor region 19 'having the same conductivity as that of the body region 20' is formed. That is, it is smaller than the resistance.

In this way, the current driving capability can be made different depending on the direction of the source and the drain. In order to explain this, for example, Qn in FIG.
In the n-type MISFET described as 1, when 11 'is grounded to 0V and becomes a source region, and 15' becomes VDD and becomes a drain electrode, the resistance between the region 11 'and the body region 20' becomes the region 15 '. Is lower than the resistance between the '
The voltage of the body becomes close to 0V by resistance division. Conversely, 1
If 5 'is grounded to 0V and becomes the source region, and 11' becomes VDD and becomes the drain electrode, the region 11 'and the body region
Since the resistance between the region 20 'and the region 20' is lower than the resistance between the region 15 'and the body region 20', the voltage of the body becomes close to VDD due to the resistance division. Here, in the n-type MISFET, when the voltage of the body decreases, the threshold value increases due to the substrate bias effect.
Becomes lower than that of the drain region. In particular, when the transistor is a partially depleted transistor, an electrically neutral body region is formed, which is a desirable mode for the present embodiment.

From the above, it is clear that a logic circuit similar to that described in the second embodiment can be formed by using a transistor whose threshold value changes depending on the direction of current flow. For example, FIG. 20 (b) shows a static 2-input NA
FIG. 20A shows a circuit diagram for ND, and FIG. 20A shows a layout of a wiring layer for a static two-input NAND corresponding to FIG. 20B. These use the transistor arrangement of FIG. p-type MISFET field shield gate 10 ''
Contact 26 ″ with the VDD power supply line 17 ′,
The circuit and layout can be configured in the same manner as in FIGS. 16 (a) and 15 (a) except for the connection contact 26 '' for connecting the VDD power supply line 17 '' to the field shield gate 10 '' of the n-type MISFET. Although not shown in the drawing, it is apparent that other logic elements, a two-input NOR and a clocked gate of the second embodiment can be formed in the same manner.

In this embodiment, the regions 19 and 19 'are
For example, Ar or N2, Ge, F2 and 10 ¹³ ~10 ¹⁶ cm ^-2 implanted formed region, the depletion layer region 11 and 11 'and, in an alternative form in the diffusion length of the minority carriers from the body Is also good.
Such ions form a defect at the junction between the source / drain layer and the body electrode, which is a generation center, and increase the reverse current, so that the same effect can be obtained.

In this embodiment, (3) of the second embodiment
In addition to the effects described above, the following effects can be obtained. (1) By adjusting the amount and position of impurity addition in 19, the difference in threshold value depending on the current direction of the source and drain of the p-type MISFET can be controlled. Also, 1
By adjusting the doping amount and position of 9 ',
The difference in threshold value depending on the current direction of the source and drain of the n-type MISFET can be controlled independently of the p-type MISFET.

(2) The region 11 or 11 'having poor junction characteristics becomes a drain only when transistors are formed in series, and usually 15 or 15' having good junction characteristics.
Region can be used as a drain. Therefore,
The drain withstand voltage can be improved as compared with the case where 19 'is formed in all the source / drain regions. further,
When a current flows through the transistors connected in series, the voltage applied between the drain and the source of each transistor decreases because voltage distribution occurs by the plurality of transistors. Therefore, in this case, the probability of generation of electron-hole pairs is reduced, and deterioration due to hot electrons is less likely to occur.

[0101]

As described above, according to the present invention, a back gate electrode is provided in a support substrate facing a channel region of each transistor in a semiconductor device having a gate array structure, and a position facing a drain is provided. , A depletion layer is formed on the supporting substrate. Therefore, the parasitic capacitance between the source / drain electrodes and the supporting substrate is reduced.

[Brief description of the drawings]

FIG. 1 shows an SOI-MISF according to a first embodiment of the present invention.
FIG. 2 is a schematic sectional view of the ET.

FIG. 2 shows an SOI-MISF according to the first embodiment of the present invention.
FIG. 2 is a schematic sectional view of the ET.

FIG. 3 shows an SOI-MISF according to the first embodiment of the present invention.
The schematic plan view of ET.

FIG. 4 is an SOI-MISF according to the first embodiment of the present invention.
Schematic circuit diagram of ET.

FIG. 5 shows an SOI-MISF according to the first embodiment of the present invention.
Schematic circuit diagram of ET.

FIG. 6 shows an SOI-MISF according to the first embodiment of the present invention.
Schematic circuit diagram of ET.

FIG. 7 is a graph of the back gate voltage dependence of the threshold value according to the first embodiment of the present invention.

FIG. 8 is a graph of a back gate voltage for realizing no threshold fluctuation according to the first embodiment of the present invention.

FIG. 9 is a graph of a back gate voltage for realizing a constant current driving capability according to the first embodiment of the present invention.

FIG. 10 shows an SOI-MI according to a second embodiment of the present invention.
FIG. 2 is a schematic plan view of an SFET.

FIG. 11 shows SOI-MI according to a second embodiment of the present invention.
FIG. 2 is a schematic sectional view of an SFET.

FIG. 12 shows an SOI-MI according to a second embodiment of the present invention.
FIG. 2 is a schematic sectional view of an SFET.

FIG. 13 shows an SOI-MI according to the second embodiment of the present invention.
FIG. 2 is a schematic sectional view of an SFET.

FIG. 14 is a diagram illustrating a change in a threshold value according to a source / drain direction of a transistor according to a second embodiment of the present invention.

FIG. 15 shows an SOI-MI according to the second embodiment of the present invention.
FIG. 2 is a schematic circuit diagram of an SFET.

FIG. 16 shows SOI-MI according to the second embodiment of the present invention.
FIG. 2 is a schematic plan view of an SFET.

FIG. 17 shows an SOI-MI according to the second embodiment of the present invention.
1 is a schematic plan view and a circuit diagram of an SFET.

FIG. 18 shows an SOI-MI according to a third embodiment of the present invention.
FIG. 2 is a schematic plan view of an SFET.

FIG. 19 shows an SOI-MI according to the third embodiment of the present invention.
FIG. 2 is a schematic sectional view of an SFET.

FIG. 20 shows an SOI-MI according to the third embodiment of the present invention.
1 is a schematic plan view and a circuit diagram of an SFET.

FIG. 21 is a schematic sectional view of a conventional SOI-MISFET.

FIG. 22 is a schematic circuit diagram of a conventional SOI-MISFET.

[Explanation of symbols]

1: n-type region 2: p-type region 3: insulating film 4: channel region 5: support substrate 6: insulating film 7: voltage source 8: control circuit for supplying voltage 9: gate insulating film 10: gate electrode 11: source electrode Drain region 12: Interlayer insulating film 13: Element isolation insulating film 14: Contact 15: Source / drain region shared by transistors connected in series 16: Contact 17 and 18: Electrode 19: P-type semiconductor region 20: Body region

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F110 AA02 AA08 AA09 AA30 BB02 BB04 CC02 CC10 DD05 DD13 DD14 DD22 EE03 EE04 EE09 EE28 EE30 EE31 EE50 FF01 FF02 FF03 FF04 GG01 GG22 GG32 GG34 HJ01 HL04 NN

Claims (6)

[Claims] An insulating film, a first impurity region of a first conductivity type formed on the insulating film, and a first impurity region of a second conductivity type formed adjacent to the first impurity region. A channel region; a second conductivity type second impurity region formed adjacent to the first channel region; and a second conductivity type second impurity region formed adjacent to the second impurity region. A channel region; a third impurity region of a first conductivity type formed adjacent to the second channel region; a first gate insulating film formed on the first channel region; A second gate insulating film formed on a second channel region; a first gate electrode formed on the first gate insulating film; and a second gate insulating film formed on the second gate insulating film. And a second gate electrode formed under the first channel region via the insulating film. A first back gate electrode of a first conductivity type; and a second back gate electrode of a first conductivity type formed under the second channel region via the insulating film. Semiconductor device. 2. The semiconductor device according to claim 1, further comprising a first semiconductor region of a second conductivity type covering said first and second back gate electrodes. 3. A first power supply for supplying a first potential to the first back gate electrode, and a second power supply for supplying a second potential different from the first potential to the second back gate electrode. The semiconductor device according to claim 1, further comprising two power supplies. 4. An insulating film, a first conductive type first impurity region formed on the insulating film, and a second conductive type first impurity region formed adjacent to the first impurity region. A channel region; a second conductivity type second impurity region formed adjacent to the first channel region; and a second conductivity type second impurity region formed adjacent to the second impurity region. A channel region; a third impurity region of a first conductivity type formed adjacent to the second channel region; a first gate insulating film formed on the first channel region; A second gate insulating film formed on a second channel region; a first gate electrode formed on the first gate insulating film; and a second gate insulating film formed on the second gate insulating film. And a first conductive layer formed under the second impurity region with an insulating film interposed therebetween. A fourth impurity region of the mold, of a pair sandwiching the fourth impurity region, the semiconductor device characterized by In any or the other and a second conductivity type fifth impurity regions. 5. An insulating film, a first conductive type first impurity region formed on the insulating film, and a second conductive type first impurity region formed adjacent to the first impurity region. A channel region; a second conductivity type second impurity region formed adjacent to the first channel region; and a second conductivity type second impurity region formed adjacent to the second impurity region. A channel region; a third impurity region of a first conductivity type formed adjacent to the second channel region; a first gate insulating film formed on the first channel region; A second gate insulating film formed on a second channel region; a first gate electrode formed on the first gate insulating film; and a second gate insulating film formed on the second gate insulating film. And a first conductive layer formed under the second impurity region with an insulating film interposed therebetween. A fourth potential region, a fifth and a sixth impurity regions of a second conductivity type facing each other with the fourth impurity region interposed therebetween, and a first potential applied to the fifth impurity region. A first power supply to be supplied; and a second power supply different from the first potential to the sixth impurity region.
And a second power supply for supplying a potential of the semiconductor device. 6. An insulating film, a first conductive type first impurity region formed on the insulating film, and a second conductive type first impurity region formed adjacent to the first impurity region. A channel region; a first conductivity type second impurity region formed adjacent to the first channel region; and a second conductivity type second impurity region formed adjacent to the second impurity region. A channel region; a third impurity region of a first conductivity type formed adjacent to the second channel region; a first gate insulating film formed on the first channel region; A second gate insulating film formed on a second channel region; a first gate electrode formed on the first gate insulating film; and a second gate insulating film formed on the second gate insulating film. 2 gate electrodes, at least one of the first impurity region and the third impurity region. Wherein a is also provided with one and the first to fourth impurity region of the second high second conductivity type impurity concentration than the channel region between the insulating film.