JP2011166116A - Circuit of uniform transistors on seoi with buried back control gate beneath insulating film - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that occurs due to variability existing in lithography pattern transfer, to save space by making a structure stricter without using STI, and to provide a more regular and finer structure to be transferred. <P>SOLUTION: A semiconductor device formed on a SeOI substrate includes an array of patterns formed of a field-effect transistor and disposed in the form of a row, and includes a front control gate region formed above a channel region of the field-effect transistor. A source and a drain region included in each row also have the same dimensions and are spaced apart by the front control gate region having a predetermined dimension. At least one transistor of T<SB>1</SB>to T<SB>4</SB>included in a pattern has a back control gate region formed in the base substrate existing below the channel region, and the back control gate region is capable of being biased by shifting the threshold voltage of the transistor. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

Field of Invention

  The field of the invention is that of microelectronics.

  More particularly, the present invention relates to a semiconductor device manufactured on a SeOI (semiconductor-on-insulator) substrate based on a component having a homogenized pattern.

Background of the Invention

  A general trend in the field of application of the present invention is that attempts have been made to simplify lithography in order to solve the problems of distortion and deformation of the lithographic structure to be transferred onto the wafer.

  For this reason, the prior art recommends avoiding corners as much as possible in the same lithography plane. However, it is common practice to use transistors of various widths to construct a circuit.

  The channel length of a MOSFET transistor is currently typically about 30 nm, but its channel width W is typically much larger than its length. Today, this width determines the transistor current density for a given source voltage, drain voltage and gate voltage.

  In general, it is possible to design electronic circuits in which different transistors have different widths. However, as a practical matter, it is difficult to obtain various widths with a certain accuracy due to the resolution limit of lithography. In fact, while it is relatively easy to produce elongate strips by lithography, short strips with fairly controlled dimensions are particularly difficult to achieve.

  Patent Document 1 teaches a manufacturing process aimed at preventing performance non-uniformity between various transistors included in a circuit. To do so, this specification proposes to equalize the impact of the environment on the various transistors. More particularly, this specification provides that an array of FET transistors is arranged in a plurality of long strips. To that end, the drain and source regions of every strip have the same dimensions, and the regions are separated by the width of a gate region having a predetermined dimension.

  Thus, it should be appreciated that the resolution limit of lithography attempts to force the use of such long strips of transistors having the same dimensions.

  However, this leads to a loss of flexibility in designing electronic circuits. This is because it is no longer possible to change the geometric width of the transistors in order to adjust the performance of the various transistors.

US Patent No. US2008 / 0251848

  In this context, the object of the invention is to solve the problems caused by the variability inherent in lithographic pattern transfer (random variability due to line structuring, and line / space / line variability). To save space by avoiding the need for shallow trench isolation (STI) and by tightening the structure (active area, gate lines, wiring, etc.) To simplify lithography by proposing a more regular and precise structure.

  To this end, the present invention provides, according to a first aspect, a semiconductor device formed on a semiconductor-on-insulator substrate comprising a thin film of semiconductor material separated from a base substrate by an insulating film, The semiconductor device comprises an array of patterns each formed from at least one field effect transistor, each field effect transistor having a source region, a drain region, and a channel region defined by the source region and the drain region. In the thin film, it also has a front control gate region formed above the channel region, the patterns are arranged in rows, and the source and drain regions contained in any row have the same dimensions. And have a predetermined dimension separated by the width of the front control gate area And at least one transistor included in the pattern has a back control gate region formed in the base substrate below the channel region, and the threshold voltage of the transistor is shifted to increase the channel width of the transistor. Back control, as if it had changed, or to force the transistor to remain off or on whatever the voltage applied to the transistor's front control gate Providing a semiconductor device characterized in that the gate region can be biased;

Specific, but not limited, specific embodiments of this device include:
-Some of the patterns in the row were formed on the same active area of the thin film of the semiconductor-on-insulator substrate, and the isolation area defined an adjacent pattern, and the isolation area was formed above the active area A front isolation gate and a back isolation gate formed in a base substrate existing below the active region.
A back isolation line connects each back isolation gate of the isolation region present in any row.
-The back isolation line is common to several rows.
The back isolation gate has a conductivity type opposite to that of the active region.
A back gate line connects the back control gate region (s) of one or more transistors;
The back gate line connects the back control gate region (s) to ground or a nominal supply voltage.
The back gate line connects the back control gate region (s) to an analog adjustable potential.
The back control gate region is separated from the base substrate by a well having opposite conductivity.
The back control gate region has the same type of conductivity as that of the transistor channel.
The back control gate region has a conductivity type opposite to that of the transistor channel;

  According to another aspect, the invention relates to a method of driving a device according to the first aspect of the invention, wherein the back control gate region is used to shift the threshold voltage of the transistor. Biased positively or negatively, and more particularly, the back control gate region is biased by an analog adjustable potential.

  According to a further aspect, the present invention relates to a method for driving a device according to the first aspect of the present invention, in which the transistor is whatever the voltage applied to the front control gate of the transistor. The threshold voltage shift is controlled to be maintained in the off state or the on state. In particular, the threshold voltage shift is programmed by a memory cell that stores and supplies a predetermined voltage to the back control gate region.

  According to a further aspect, the present invention relates to a reprogrammable circuit, which is alternately inserted into a row of memory cells that store and supply a predetermined voltage to a back control gate region. A device according to the first aspect of

  Other aspects, objects and advantages of the present invention will become more apparent from an understanding of the detailed description of the preferred embodiments of the invention provided below, by way of non-limiting example, with reference to the accompanying drawings. It will be something.

It is a figure which shows the circuit by a prior art. FIG. 5 illustrates how the threshold voltage of a transistor is controlled by biasing the back control gate. FIG. 2 is a diagram illustrating an active region present below an insulating film of the same circuit as shown in FIG. 1 according to an embodiment of the present invention. FIG. 2 is a diagram illustrating an active region present below an insulating film of the same circuit as shown in FIG. 1 according to an embodiment of the present invention. FIG. 2 is a diagram illustrating an active region present below an insulating film of the same circuit as shown in FIG. 1 according to an embodiment of the present invention. FIG. 2 is a diagram illustrating an active region present below an insulating film of the same circuit as shown in FIG. 1 according to an embodiment of the present invention. FIG. 2 is a diagram illustrating an active region present below an insulating film of the same circuit as shown in FIG. 1 according to an embodiment of the present invention. FIG. 8 is a cross-sectional view showing a portion of a row of transistors included in the circuit shown in FIG. FIG. 6 illustrates an example of a logic circuit that can be reconfigured to cover all two-input Boolean functions with appropriate voltages applied to the back gates of various transistors. 10 is a truth table of the reconfigurable logic circuit shown in FIG. FIG. 2 shows a possible arrangement of logic cells and memory cells used to store logic cell programming and to supply appropriate voltages to the back gates of the logic cell transistors.

  FIG. 1 shows a prior art CMOS electronic circuit as taught by US Pat. No. US2008 / 0251848.

  The circuit comprises an array of several patterns, each pattern being formed from at least one field effect transistor and arranged in a row, the source and drain regions of each transistor in every row. The front control gate regions WL1 to WL7 having the same dimensions and predetermined dimensions are separated by a width.

  Thus, only wide strips (horizontal rows and vertical front control gate regions) are formed during the lithography process. And the channel widths of the various transistors are the same and are defined by the area between two orthogonal strips.

  Note that there is no STI isolation trench between adjacent transistors in any strip. In practice, however, such isolation trenches exist along the strip to isolate the transistors from each other.

From left to right in FIG. 1, the circuit comprises the following pattern: logic gate NOR2, three inverters INV ₁ , INV ₂ and INV ₃ , and logic gate NAND2.

  More specifically, the circuit in this example comprises nine buses made of metal 2, with p-FET transistors arranged along buses 2 and 3, and n-FET transistors along buses 7 and 8. Be placed. Buses 4-6 are used to make input / output connections to these patterns and are used to connect these various patterns to each other. Obviously, other combinations with suitable 8-12 metal 2 buses are possible.

Metal 1 supply lines BL _P1 , BL _P2 , BL _N1 , BL _N2 serve to determine the potentials of the drain regions of some transistors.

Therefore, the drain of the first p-FET transistor of the logic gate NOR2, and the drain of the p-FET transistor of the inverter INV ₁ and INV ₂ are connected to the line _{BL P1.} In contrast, the drain of the p-FET transistor of the inverter INV _3, and the drain of the p-FET transistor of the logic gate NAND2 are connected to the line _{BL P2.}

Drains, and n-FET transistor of the inverter INV ₁ and INV ₂ of n-FET transistor of the logic gate NOR2 is connected to the line _{BL N1.} In contrast, the drain of the first n-FET transistor of the drain, and logic gates NAND2 the n-FET transistor of the inverter INV ₃ is connected to the line _{BL N2.}

Lines _BLP1 and _BLP2 are typically used to provide a nominal supply voltage V _DD . On the other hand, the lines BL _N1 and BL _N2 are typically connected to the ground GND.

A pattern along the row is formed on the same active area of the substrate, thus providing an isolation region between adjacent patterns. These isolation regions, each having a front isolation gate formed above the active region, will in the following have the signs I _{P1 to} I _P6 for the isolation region coupled to the p-FET transistor, and The isolation region coupled to the n-FET transistor has the symbols I _N1 -I _N6 .

The front isolation gates of the isolation regions are biased by isolation gate supply lines B1 _P and B1 _N for isolation regions between p-FET patterns and isolation regions between n-FET patterns, respectively. These lines Bl _P and Bl _N is typically (typically polycrystalline silicon) of polycrystalline semiconductor material is formed from.

  In general, the present invention transfers a circuit with an isomorphic environment of the type shown in FIG. 1 onto a SeOI substrate (with a thin film of semiconductor material separated from the base substrate by an insulating film). It is suggested to do. In this context, the present invention proposes to arrange a back control gate in the base substrate facing the channel of at least one transistor. By biasing the back control gate of the transistor positively or negatively (typically by + vdd or -vdd), the characteristics of the transistor may be changed individually. In particular, the threshold voltage of the transistor may be shifted. As a result, changing the threshold voltage is equivalent to changing the physical width of the channel.

  Thus, in the context of the present invention, for all transistors, the physical width of the channel is defined only once. However, it can be seen that by choosing how the back control gate is driven, the apparent (effective) width of the channel of the transistor can be changed individually for each transistor. Since the voltage applied to the back control gate may be changed, the present invention thereby provides the advantage of dynamically changing the effective channel width.

  A transistor having a channel having n-type conductivity and a back control gate having p-type conductivity (for this reason, in the description herein, the back control gate has a work function). Have a very high threshold voltage. The threshold voltage can be reduced by applying a positive voltage to the back control gate.

  A transistor in which the channel has n-type conductivity and the back control gate has n-type conductivity (for this reason, in this description, the back control gate has a work function. Has a nominal threshold voltage that can be reduced by applying a positive voltage to the back control gate.

This variation in the threshold voltage of the transistor through the back control gate may be formulated as V _th = V _t0 −αV _BG . Where V _th represents the threshold voltage of the transistor, V _BG represents the voltage applied to the back control gate, and V _t0 is the nominal threshold voltage (this is the n-type back control). May be shifted by a work function depending on whether a gate or a p-type back control gate is used). Α represents a coefficient related to the geometry of the transistor.

Provence in June 2009, described in the paper that the Aix-Marseille was claimed by Germain Bossu in University I "Architectures innovantes de memoire non-volative embarquee sur film mince de silicium" Innovative non-volatile memory architectures on thin silicon films. "" As can be _seen , the coefficient α may be approximated as, among other things, α = 3t _OX1 / (t _Si + 3t _OX2 ), where t _OX1 is the dielectric gate film that separates the front control gate from the channel. Thickness (typically 1-2 nm) Taste _{and, t OX2} (if the SeOI substrate, typically, 5 to 20 nm) of the back control gate thickness of the insulating film which separates from the channel means, _{and, t Si} is of the thin film thickness Means.

  Thus, the back control gate doping type associated with the transistor may or may not shift the nominal threshold voltage, and the threshold voltage is adjusted by biasing the back control gate. It will be understood that it is possible to do.

Thus, the conduction current I _ON in the on-state of the transistor (by reducing the threshold voltage) is increased, and, a small leakage current I _OFF in the off-state of the transistor (by increasing the threshold voltage) decreases You can benefit from doing that.

  Further, by reducing the leakage current in the isolation region (insulating region) that separates adjacent patterns along the row, it is possible to contribute to the insulating function of the isolation region.

  FIG. 2 shows that the threshold voltage of the transistor formed on the SeOI substrate is determined by biasing the back control gate formed in the base substrate under the insulating film facing the transistor channel. It is for explaining how it is controlled.

In FIG. 2, the center curve C _N represents the nominal characteristic log (I _D (V _G )) (in the case of a transistor without a back control gate).

The upper curve C _VT− represents the nominal characteristic log (I _D (V _G )) under the influence of the back control gate driven by a voltage smaller than the nominal supply voltage V _DD of the circuit. This upper curve shows an increase in threshold voltage and a decrease in currents I _ON and I _OFF .

The lower curve C _{VT +} represents the nominal characteristic log (I _D (V _G )) under the influence of the back control gate driven by the nominal supply voltage V _DD . This lower curve shows a decrease in threshold voltage and an increase in currents I _ON and I _OFF .

Therefore, by changing the bias of the back control gate, it is possible to cover the entire region that exists between the lower curve C _VT− and the upper curve C _{VT +} , thereby reducing the transistor's _resistance. It will be appreciated that the threshold voltage and the transistor's characteristic currents I _ON and I _OFF can be adjusted.

The following equation relates, inter alia, the current _ID in the channel to the channel width W and the threshold voltage _Vth .

First, let us consider a gate voltage and a drain voltage (V _GS = V _DS = 0.9 V) of 0.9 V together with λ = 0.05 and a threshold voltage V _th = 0.3 V.

By changing the threshold voltage so that the threshold voltage of the transistor is between 0.05V and 0.6V, the physical width of the channel can be changed as if it were changed. . In theory, the effective width of the transistor channel is, in fact, present in the range of from 0.25 times the physical width W ₀ of the channel up to 2.01 times.

  In another example, consider a lower gate and drain voltage, ie 0.7V. In this case as well, the threshold voltage is changed so that the threshold voltage of the transistor becomes a value existing between 0.05V and 0.6V, so that the effective width of the channel is theoretically the channel. It exists in the range from 0.06 times to 2.64 times the physical width of.

  Thus, the present invention allows for a reduction / increase of the effective channel width, which is very important as the supply voltage is lowered.

  In this regard, it should be noted that the trend in the technical field of the present invention is an attempt to use increasingly lower supply voltages for the next generation of electronic components. Thus, it can be seen that the present invention is itself a very interesting pioneer for the next generation.

  3-7 illustrate an active region that resides below an insulating film of the same circuit as shown in FIG. 1 according to various embodiments of the present invention.

In FIG.
The p-doped back control gate region includes isolation regions I _{P1 to} I _P6 , two p-FETs and n-FET transistors of inverter INV ₂ , and two n-FET transistors of logic gate NAND 2 Related. Also,
The n-doped back control gate region is associated with the isolation regions I _{N1 to} I _N6 and the two p-FET and n-FET transistors of the inverter INV ₃ .

Back gate line BG _P and a back gate line BG _N, respectively, forms a role of connecting p- doped back gate regions and the n- doped back gate regions collectively at the same potential.

Thus, the line BG _P associated with the p- doped back gates (typically, are connected to the potential V _DD) high state may be, whereas, n- doped back gate the relevant line BG _N (typically, is connected to the ground GND) low state may be.

In this way, the isolation region experiences a higher threshold voltage and, as a result, experiences a smaller leakage current I _OFF , thereby providing better isolation between adjacent patterns along any row. Help maintain.

With respect to the inverter INV _2, the back control gate of the back control gate and n-FET transistors of the p-FET transistor are in the high state _{V DD.} conduction current _{I ON} in the n-FET transistor is increased. On the other hand, the conduction current of the p-FET transistor decreases. Thus, INV ₂ has a low p-FET and a high n-FET.

For inverter INV ₃ , this has a high p-FET and a low n-FET (the back control gate of the p-FET transistor and the back control gate of the n-FET transistor are in the low state GND. is there).

  With respect to logic gate NAND2, the p-FET transistor does not have a back control gate. Accordingly, these p-FET transistors operate in a nominal manner. The n-FET transistor does not have a back control gate in the high state. These n-FET transistors have a larger conduction current.

  FIG. 4 shows a further embodiment, in which four different voltage levels are used to provide greater flexibility.

In FIG.
- p-doped back control gate regions collectively connected to a high state back gate line _{BG PH} includes a separation region _I P1 _{~I P6,} associated with the p-FET transistor of the inverter INV ₂ ,
The p-doped back control gate region connected to the back gate line BG _PL in the low state is associated with the p-FET transistor of the inverter INV ₃ ;
The n-doped back control gate region connected to the back gate line BG _NL in the low state is related to the isolation regions I _{N1 to} I _N6 and the n-FET transistor of the inverter INV ₃ And
- n-doped back control gate region connected to a back gate line _{BG NH} in a high state is associated with the n-FET transistor of the inverter INV _2.

  Therefore, as in the example shown in FIG. 3, the leakage current in the isolation region decreases.

Inverter INV ₂ has a low p-FET transistor (p-doped back control gate in the high state) and a high n-FET transistor (n-doped back control gate in the high state). .

Inverter INV ₃ has a high p-FET transistor (p-doped back control gate in the low state) and a low n-FET transistor (n-doped back control gate in the low state). .

  FIG. 5 shows a further embodiment in which the back control gate associated with the transistor is connected to a back gate line specific to this embodiment. It will be appreciated that such an embodiment allows the potential applied to the back gate line dedicated to a single transistor to be adjusted.

In FIG. 5,
- p-doped back control gate regions collectively connected to a high state back gate line _{BG PH} includes a separation region _I P1 _{~I P6,} associated with the p-FET transistor of the inverter INV ₂ ,
The p-doped back control gate region connected to the individual back gate line BG _PA whose voltage can be adjusted is associated with the p-FET transistor of the inverter INV ₃ ;
The n-doped back control gate region connected to the back gate line BG _NL in the low state is associated with the isolation regions I _{N1 to} I _N6 and the n-FET transistor, and
- n-doped back control gate region connected to an individual back gate line _{BG NA} capable of modulating voltage is related to the n-FET transistor of the inverter INV _2.

Therefore, the inverter INV ₂ is addressed by lines _{BG NA,} which can adjust the low-p-FET transistor (in the high state p- doped back control gate), and adjustable n-FET transistor (the potential Individual n-doped back control gates).

For inverter INV ₃ , this is achieved by a low n-FET transistor (n-doped back control gate in the low state) and an adjustable p-FET transistor (line BG _PA with adjustable potential). With individual p-doped back control gates addressed).

  FIG. 6 shows an alternative embodiment of the example of FIG.

In FIG. 6,
- p-doped back control gate regions collectively connected to a high state back gate line _{BG PH} is associated with the isolation region _I P1 _{~I P6,}
- associated with the p- doped back control gate region connected together to a low state back gate line _{BG PL} includes a p-FET transistor of the inverter INV _2, and p-FET transistor of the inverter INV ₃ And
The n-doped back control gate region connected together to the back gate line BG _NH in the high state is associated with the isolation regions I _{N1 to} I _N6 and the n-FET transistor of the inverter INV ₃ And
- n-doped back control gate region connected to a back gate line _{BG NL} in a low state is associated with the n-FET transistor of the inverter INV _2.

Thus, inverter INV ₂ has a high p-FET transistor (p-doped back control gate in the low state) and a low n-FET transistor (n-doped back control gate in the low state). Have

Inverter INV ₃ has a high p-FET transistor (p-doped back control gate in the low state) and a high n-FET transistor (n-doped back control gate in the high state). .

  FIG. 7 shows a preferred embodiment, in which the isolation region is associated with a back control gate region having the opposite type of conductivity. Accordingly, the leakage current in these isolation regions is further reduced.

More specifically, in FIG.
The n-doped back control gate regions connected together to the back gate line BG _NH in the high state are the n-FET transistors included in the isolation regions I _{P1 to} I _P6 and the logic gate NOR ₂ In relation to any one and the p-FET transistor of inverter INV ₂ ;
The p-doped back control gate region connected to the individual back gate line BG _PA1 whose voltage can be adjusted (to any intermediate value selected by the person skilled in the art) is the p of the inverter INV ₃ -Relating to FET transistors,
- p-doped back control gate regions collectively connected to a low state back gate line _{BG PL} includes a separation region _I N1 _{~I N6,} any p-FET transistor included in the logic gate NAND2 And one of the n-FET transistors of the inverter INV ₃ ,
The p-doped back control gate region connected to the individual back gate line BG _PA2 whose voltage can be adjusted (to any intermediate value selected by the person skilled in the art) is the n of the inverter INV ₁ -Relating to FET transistors,
The n-doped back control gate region connected to the individual back gate line BG _{NA1 (} which can be adjusted to any intermediate value selected by the person skilled in the art) is connected to the n of the inverter INV ₂ -Relating to FET transistors, and
- (optional to an intermediate value selected by the skilled artisan) voltage n- doped back control gate region connected to an individual back gate line BG _NA2 capable of modulating is connected to the BG _PL Not related to the p-FET transistor of the logic gate NAND2.

Thus, isolation regions I _P1 -I _P6 have a p-channel with a p-type back control gate in the high state (typically V _DD ). These regions have a maximum threshold voltage and, as a result, have a minimum leakage current.

Isolation regions I _N1 -I _N6 have an n-channel with an n-type back control gate that is in its low state (typically GND). These regions have a maximum threshold voltage and, as a result, have a minimum leakage current.

Also, one of the n-FET transistor included in the logic gate NOR _2, has a n- channel comprises an n-type back control gate in a high state. This n-FET transistor has a minimum threshold voltage and, as a result, has maximum performance characteristics (in terms of conduction current _ION ).

The n-FET transistor of the inverter INV ₁ has an n-channel with a p-type back control gate that can regulate the voltage. Therefore, this transistor has a performance characteristic that exists between the minimum performance characteristic and the intermediate performance characteristic, depending on the voltage applied to the individual line BG _PA2 .

The p-FET transistor of inverter INV ₁ does not have a back control gate, so that it operates in a nominal manner.

The n-FET transistor of the inverter INV ₂ has an n-channel with an n-type back control gate that can regulate the voltage. Therefore, this transistor has a performance characteristic that exists between the intermediate performance characteristic and the maximum performance characteristic, depending on the voltage applied to the individual line _BGNA1 .

The p-FET transistor of the inverter INV ₃ has a p-channel with a p-type back control gate that can regulate the voltage. Therefore, this transistor has a performance characteristic that exists between the minimum performance characteristic and the intermediate performance characteristic, depending on the voltage applied to the individual line BG _PA1 .

The p-FET transistor of the logic gate NAND2, which does not have an n-type back control gate whose voltage can be adjusted by the individual line _BGNA2 , has a performance characteristic that exists between the intermediate performance characteristic and the maximum performance characteristic. Have

P-FET transistor of the logic gate NAND2 which voltage by the line BG _PL has a p-type back control gate in a low state, itself, has a minimum threshold voltage and maximum performance characteristics.

The upper part of FIG. 8 shows two lines 7 and 8 made of metal 2, along which the FET transistors of the circuit shown in FIG. 7 are arranged. The lower part of FIG. 8 shows a cross-sectional view of a part of the line 8 made of metal 2. This part includes isolation regions I _{N1 to} I _N3 , NOR2 (T ₁ and T ₂ ), INV ₁ (T ₃ ). And n-FET transistors T _{1 to} T ₄ included in the INV ₂ (T ₄ ) pattern. In this cross-sectional view, the insulating film has a symbol BOX.

  In FIG. 8, the transistor channel is fully depleted, and the source and drain regions are in contact with the insulating film.

  However, the present invention may also be applied to partially depleted techniques where the source and drain regions do not extend into the entire thin film. In this case, since the back control gate is farther away from the channel region that exists between the source and drain regions, the back control gate is not very efficient overall. Please be careful.

As explained so far, the isolation regions I _{N1 to} I _N3 have n-channels, each of which is a p ⁺ -type back control gate G _P1 ˜ (which is in the low state by the line BG _PL ). _GP3 .

While _{T 1} is the n-FET transistor included in the logic gate NOR2 has (in the high state by the line _{BG NH)} have a ^{n +} -type back control gate _{G N1,} whereas the logic gate NOR2 T ₂ is the other of n-FET transistors included does not have a back control gate.

The n-FET transistor T ₃ of the inverter INV ₁ has a p ⁺ type buck control gate GP _{4 (} which can be adjusted by the individual line BG _PA ² ).

N-FET transistor _{T 4} of the inverter INV ₂ has a (can be adjusted by the individual line _{BG NA1)} ^{n +} -type back control gate _{G N2.}

  As shown in FIG. 8, the associated back control gate is localized to extend only to the opposite side of the transistor channel. For example, the back control gate is formed by implanting a dopant below the insulating film BOX.

The back control gate is a well C _N1 , C _P1 , C _N2 , C _P2 (p ⁺ type back control gates G _P1 , G _P2 , G _P3) having conductivity opposite to that of the control gate. , of n for _{G P4} ^- -type well _{C N1} and _C N2; ^- by type well _{C P1} and _{C P2),} is separated from the base substrate p for the ^{n +} -type back control gate _{G N1} and _{G N2} .

The well voltage is selected such that the diode formed by the electrical node between the back control gate and the well is always reverse biased, so that the diode causes the back control gate to And from anything that may be included (especially other back control gates). Of course, in practice, a well common to several back control gates having the same type, as in the case of well _CN2 that separates back control gates _GP2 , _GP3 and _GP4 together. Can be provided.

Returning to FIG. 7, reference numeral C _P and C _N, respectively, show the well to isolate the n-type back control gate and the p-type back control gate. Well _CP is typically in the low state GND, while well _CN is typically in the high state V _DD .

  According to another embodiment (not shown), the second insulating film disposed in the base substrate below the insulating film BOX completely or partially separates the back control gate from the base substrate. You may contribute to

  The device according to the invention has the following advantages.

  A wide performance range for p-FET and n-FET transistors can be obtained using only one physical channel width. Typically, there are three types of performance:

-Normal performance in the absence of a back control gate.
As a result, the transistor is a normal SeOI transistor, and there is no need to change the existing circuit design.

-Enhanced performance to increase transistor conduction with "ON" back control gate.
As a result, the transistor operates as if the channel width is wider than it actually is, or the transistor has a smaller footprint per performance unit (speed, I _ON ).

-Reduced performance, reducing transistor conduction with "OFF" back control gate.
As a result, the transistor behaves as if the channel width is narrower than it actually is. This turns out to be advantageous when a performance ratio is desired (eg in the case of flip-flop type latches). This is because there is no need to increase the channel width of other devices. Also, the leakage current is considerably reduced. Thus, as long as the transistor does not switch (no ratio to be considered), this type of performance may be used in the off state, thereby reducing the leakage current I _OFF .

  However, the present invention is in no way limited to these three types of performance. In fact, the performance characteristics may be adjusted dynamically by applying an analog adjustable bias to the transistor back control gate. Thereby, any kind of performance that exists between the aforementioned “reduced performance” and “enhanced performance” can be realized.

  In a particular variation, the back control gate may be biased by any one of a plurality of predetermined voltages. These multiple voltages are typically voltages available in the environment of the device, eg, Vdd, various fractions of Vdd (such as Vdd × 2, Vdd / 4), (Vdd−Vtp, Various combinations of available voltages (such as Vdd-Vtn).

  Thus, the ratio between the p-FET transistor and the n-FET transistor can be adjusted without changing the channel width.

  Thus, it will be appreciated that the device according to the present invention eliminates the need in the general design that the transistor must have various dimensions. Effectively, only one physical width and a simplified model and parameters of the transistor are used. Note that the transistor model is actually a complex equation with many secondary (parasitic) or tertiary edge effects. Most of these effects depend on the dimensions of the transistor, and in the case of modern technology, on the environment (proximity stress). In the context of the present invention, there is only one topology, so the model can be greatly simplified (this results in faster availability, shorter development times, etc.) )

  Furthermore, very low variability exists because of the high level of regularity and because only the polysilicon silicon roughness remains. In contrast, it should be noted that when a fully depleted structure is formed, there is no dopant level variation.

  Also, the device according to the present invention is not affected by the edge rounding effect of the pattern. This is because all channels have the same physical width. The active area strip is effectively a long polygon that is not rounded near the polycrystalline silicon connection line. Also, the 90 ° corners of such lines are far away from the active strip (which exists at both the top and bottom of the structure) and do not interact with the active strip.

  Furthermore, the device according to the invention is not affected by the cross-coupling effect.

  This is because, in typical designs, the polycrystalline silicon connection is often in close proximity to the drains of other logic gates. The two nodes are then capacitively coupled and interfered with each other, resulting in communication delays in general. Since cell-to-cell adjacency cannot be predicted, this combination cannot be taken into account in each cell model and is therefore found relatively late in the design of the application. In the context of the present invention, the interaction between the active strip and the polycrystalline silicon connection is the same for every situation, thereby solving the disadvantages encountered in common designs. In particular, coupling modeling is still valid after circuit manufacturing.

  Furthermore, the device according to the invention has a reduced power consumption by associating a back control gate with the isolation region in order to reduce the leakage current in the isolation region and to further reduce the leakage current. And the ability to dynamically act on the back control gate associated with the transistor in the off state.

  To illustrate the effectiveness of the present invention, it will be recalled that a standard CMOS cell library may comprise twelve inverters with different performance characteristics.

The present invention allows only three inverters (INV ₁ , INV ₄ and INV ₈ ) to be used when applied to fully depleted technology. This is because the effective channel width may be adjusted by +/− 50% of the physical width.

In partially depleted technology, four inverters (INV ₁ , INV ₄ , INV ₆ and INV ₉ ) are required. This is because the effective channel width may be adjusted by +/− 30% of the physical width.

  As a result, the standard cell library is greatly simplified and, in fact, is generally reduced to ½.

  Thus, although about 100 design rules are used today, the present invention allows only about 50 of them to be used.

  In this regard, it should be noted that in the past, design rule manuals included approximately 100-200 rules. Currently, the technology is generally less than 100 nm. For this reason, many physical effects have emerged that lead to new rules, which prevent the simple and easy application of an initial set of rules consisting of 100-200. In the 32 nm technology node, the design rule manual has about 800-1,000 rules, in which most of the new rules represent complex combinations of topologies in a complex way. This is accompanied by a loss of efficiency from a footprint perspective. In contrast, the efficiency of the present invention is generally kept constant. Thus, in view of the footprint used in the 45nm technology node, if the present invention and the general approach are nearly equivalent, the present invention will be increasingly in subsequent technology nodes, It should be more efficient.

  Furthermore, as long as the set of design rules is an extremely reduced subset of the normal set of rules, and since these rules apply uniquely in relation to those rules, lithography is the first Therefore, it is possible to design a transistor with less than what is possible. In particular, it is possible to optimize the contact width and the distance of many contacts (for example, replacing two nominal square contacts with one rectangular, somewhat narrower contact). By).

  Furthermore, it should be noted that the back control gate has the advantage that it is buried under the insulating film and as a result does not affect the footprint.

  Furthermore, it should be noted that the footprint may be reduced by about 10-15% as large conduction currents can be generated with the help of "enhanced" cells according to the present invention.

  Finally, the extreme regularity of the so-called “front-end” structure of the transistor is what makes the so-called “back-end” relative to the so-called “standard” cell (ie the cell pre-designed for general use). “Note that metallization is particularly suitable for normal use.

  This is because standard cells are interconnected (routed) to each other by metallization levels that are alternately horizontal and vertical at a constant pitch. The reduction in the number of design rules makes it very easy to close-off front end and back end constraints (transistor repeat pitch and routing pitch are made the same). This makes it easier to use standard cells. This is because, depending on the structure, the inputs / outputs are placed on the metal routing grid. In the general case, this is not always very easy, and it is necessary to take into account, among other things, the possibility of representing cells along the vertical and / or horizontal axis. However, maintaining routing grid inputs / outputs often means increasing the standard cell footprint. In the case of the present invention, all these considerations are eliminated by simplifying and pre-positioning the strips of transistors as a whole.

  Furthermore, the invention is not limited to devices according to the first aspect of the invention, but extends to a method for driving such a device, wherein the back control gate region is , Biased positively or negatively to shift the threshold voltage of the transistor. Advantageously, the p-type back isolation gate is connected to ground and the n-type back isolation gate is connected to a nominal supply voltage.

  As described above, applying a back gate voltage to the FDSOI transistor changes the electrical characteristics of the device. Simply put, a higher voltage on the back gate will decrease the threshold voltage of the N-channel device, and a lower voltage will increase the threshold voltage. The same is true for P-channel devices in absolute values.

  This effect can be saturated by applying a very high voltage to the back gate. For example, a very high voltage applied to an N-channel transistor reduces the transistor's threshold to a negative value and keeps the transistor on regardless of the voltage level applied to the front gate of the transistor. To do. Conversely, a (very high) negative voltage on the back gate will increase the threshold to a level beyond the power supply Vdd, at which all applied to the front gate of the transistor. With respect to the voltage (0 to Vdd), the transistor is maintained in the OFF state. Due to symmetry, the same is true for complementary P-channel devices.

In other words, the transistor can be changed to “open” and “short-circuited” by appropriately controlling the back gate. This feature has been found to be particularly effective in generating reconfigurable logic. 9, as shown in the truth table of FIG. 10, depending on the voltage applied to the back gate BG1~BG4 of various transistors T ₁ through T _4, is converted to all 2-input Boolean functions An example of a reconfigurable logic circuit that can be used is shown.

  With respect to FIG. 9, A and B indicate the two inputs of the reconfigurable logic circuit, and OUT indicates the output of the reconfigurable logic circuit. With respect to FIG. 10, Vpp forces the threshold voltage to a negative value (transistor is always on) or higher than the supply voltage Vdd (transistor is always off), respectively, for an N-channel transistor. A sufficiently high voltage is shown, and in the case of a P-channel transistor, it is high enough to force the threshold voltage to a positive or absolute value greater than Vdd. It should be appreciated that this principle of reconfigurable logic can be easily extended to more than two inputs.

  It turns out that changing the transistor to “open” and “short” by appropriately controlling the back gate is of interest to a reprogrammable circuit such as, for example, an FPGA. In this case, the back gate is not used to adjust the strength of the transistors, but is used to establish or break electrical coupling between the transistors included in the group. It is interesting that the reprogrammable cell layout is unique for every function.

  The voltages applied to the various back gates are preferably input from external circuitry and, if possible, from adjacent circuits such as SRAM cells or Flash cells. The programming of the various functions that can be realized by the reprogrammable circuits is stored in these circuits. Since any Boolean function can be programmed with this type of cell, only one and predefined back end wiring can be defined as well. As a result, the predefined chip may be fully processed and programmed by the end user. For example, FIG. 11 illustrates a reprogrammable logic circuit according to the present invention that stores a possible arrangement of logic cells LC (each logic cell corresponds to, for example, the circuit of FIG. 9) and logic cell programming. And a possible arrangement of the memory cell MC (SRAM or Flash) used to supply the appropriate voltage to the back gate. In FIG. 11, the strips of logic cells LC are alternately inserted into the rows of memory cells MC. For clarity, the logic cell LC is schematically illustrated by the box of FIG. 11, and the arrow emanating from the memory cell MC controls the back gate voltage of the logic cell LC by the memory cell MC. It shows that

  Since the dimensions are provided by the pitch of the transistors in the logic region LC, the memory cell MC uses only a metal 1 layer and a metal 2 layer with a relatively large pitch. Referring to FIG. 11, M1-MC indicates the metal 1 layer used to select a row of memory cells MC, and M2-MC is used to select a column of memory cells. A layer of metal 2 is shown. More particularly, there are sufficient resources at the metal 2 level to connect the various inputs and outputs of the logic cell LC to a predefined network constituted by the upper metal layer. With respect to FIG. 11, M2-LC indicates the metal 2 layer used to interconnect the tracks of the logic cell LC, and M3-LC is used to interconnect the tracks of the logic cell LC. A layer of metal 3 is shown.

NOR2, NAND2 logic gates _INV 1 INV ₃ inverter _I P1 _~I P6 p-FET transistor coupled to the isolation regions _I N1 _~I N6 n-FET transistor coupled the isolation region WL1~WL7 front control gate region BL _P1 , BL _P2 , BL _N1 , BL _N2 Metal 1 providing line Bl _P , Bl _N isolation gate providing lines BG1 to BG4 Back gates BG _P , BG _N , BG _PH , BG _PL , BG _NH , BG _NL , BG _PA1 , a layer of _{BG PA2, BG NA1, BG NA2} back gate line _T 1 through T ₄ transistor layer of LC logic cell MC memory cells M1-MC metal 1 layer M2-MC metal 2 M3-MC metal 3

Claims (16)

A semiconductor device formed on a semiconductor-on-insulator substrate comprising a thin film of semiconductor material separated from a base substrate by an insulating film,
The semiconductor device comprises an array of patterns each formed from at least one field effect transistor, each of the field effect transistors defined by a source region, a drain region, and the source region and the drain region. A channel region in the thin film, and further comprising a front control gate region formed above the channel region, wherein the pattern is arranged in rows, and the source included in any row A region and the drain region also have the same dimensions and are separated by the front control gate region having a predetermined dimension;
At least one of the transistors included in the pattern has a back control gate region formed in the base substrate below the channel region, and shifts a threshold voltage of the transistor, To force the transistor to the off or on state, as if it had changed the channel width of the transistor, or whatever voltage is applied to the front control gate of the transistor In order to maintain, the back control gate region can be biased,
A semiconductor device characterized by that.   Some of the patterns in the row are formed on the same active region of the thin film of the semiconductor-on-insulator substrate, and an isolation region defines the adjacent pattern, and the isolation region is the active region The semiconductor device according to claim 1, further comprising: a front isolation gate formed above and a back isolation gate formed in the base substrate that exists below the active region.   The semiconductor device according to claim 2, wherein a back isolation line connects the back isolation gates of the isolation regions existing in any of the rows.   The semiconductor device according to claim 3, wherein the back isolation line is common to some of the rows.   The semiconductor device according to claim 2, wherein the back isolation gate has a conductivity type opposite to that of the active region.   The semiconductor device of claim 1, wherein a back gate line connects the back control gate region (s) of one or more of the transistors.   7. The semiconductor device of claim 6, wherein the back gate line connects the back control gate region (s) to ground or a nominal supply voltage.   The semiconductor device of claim 6, wherein the back gate line connects the back control gate region (s) to an analog adjustable potential.   The semiconductor device of claim 1, wherein the back control gate region is separated from the base substrate by a well having opposite conductivity.   The semiconductor device of claim 1, wherein the back control gate region has the same type of conductivity as the conductivity of the transistor channel.   The semiconductor device of claim 1 wherein the back control gate region has a conductivity type opposite to that of the transistor channel.   The method of driving a semiconductor device according to claim 1, wherein the back control gate region is biased positively or negatively to shift the threshold voltage of the transistor.   The method of claim 12, wherein the back control gate region is biased by an analog adjustable potential.   2. The method of driving a semiconductor device according to claim 1, wherein the transistor is maintained in an off state or an on state whatever the voltage applied to the front control gate of the transistor. A method in which the threshold voltage shift is controlled.   15. The method of claim 14, wherein the threshold voltage shift is programmed by a memory cell that stores and supplies a predetermined voltage to the back control gate region.   2. A reprogrammable circuit comprising a semiconductor device according to claim 1 inserted alternately in a row of memory cells storing and supplying a predetermined voltage to said back control gate region.

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