JPH02264466A - Semiconductor device - Google Patents

Abstract

PURPOSE:To select an isolating position after the formation of gate electrodes by a method a transistor is provided to a region surrounded by a LOCOS and the transistor itself is used as an interelement isolation device. CONSTITUTION:Gate electrodes 102 and source and drain regions 103 are provided to a block composed of two or more transistors surrounded by a LOCOS 101. A voltage which turns the transistor OFF is applied to the gate electrode of the transistor required to be isolated from other elements to carry out interelement isolation in a wiring process after the formation of the gate electrodes. By this constitution, an interelement isolation position can be chosen in a wiring process after the formation of gate electrodes, so that a semiconductor device of this design can be improved in degree of integration.

Description

[Detailed description of the invention] [Industrial application fields] The present invention relates to pattern layout of semiconductor devices.

[Problem to be solved by the invention] In the conventional isolation between elements using LOooS, L000S
During the formation process, the isolation position between elements is fixed. Therefore, when selecting a circuit in a wiring process after the gate electrode forming process, as in the case of a gate array, it is not possible to change the position of isolation between elements. Therefore, it has been difficult to achieve high integration.

Therefore, the present invention solves the problem that conventionally the element isolation was performed using LOOO8, which made it impossible to change the element isolation position after the gate electrode formation process, making it difficult to achieve high integration. The purpose of the present invention is to provide a semiconductor device that solves the problem by being used as a semiconductor device.

[Means for Solving the Problems] The semiconductor device of the present invention has a plurality of transistors in a region recessed and separated by LOOOS, and the transistors themselves in this region are used as inter-element isolation elements. 1. A feature is that the isolation position between elements can be selected after the gate electrode forming step.

[The fact that the active co-transistor is off means that the source and drain of the transistor are insulated. Therefore, isolation between elements is possible by turning off the transistors between the elements to be isolated. In addition, since the transistor to be turned off can be selected after the gate electrode formation step,
The location of the isolation element can be selected.

[Embodiment 2] A semiconductor device of the present invention basically has the structure shown in FIG.

101 is LOOOS, 102 is a gate electrode, 10
3 is a source and drain region.

The present invention will be explained in detail below.

First, LoooSlol is used to surround blocks and separate the blocks. Here, the block refers to a region made up of a plurality of transistors and surrounded by LOOO31011C.

Next, in the block, a gate electrode 102, a source,
A drain region 103 is formed.

Isolation between elements within a block is performed in a wiring process after the gate electrode formation process by applying a voltage that turns off the transistor to the gate electrode of the transistor whose elements are to be isolated.

As a result of the isolation between elements as described above, the isolation position between elements within a block can be selected after the gate electrode forming step, and higher integration can be achieved than in the conventional structure shown in FIG.

[Effects of the Invention] According to the present invention described above, the isolation position between elements can be selected in the wiring process after the gate electrode forming process. Therefore, when a circuit is selected in the wiring process after the gate electrode forming process, as in the case of a gate array, high integration can be achieved.

[Brief explanation of drawings]

FIG. 1 is a plan view showing a semiconductor device of the present invention. FIG. 2 is a plan view showing a conventional semiconductor device. 1 0 1 --------------------- L OOOB10
2...... Gate electrode 10)... Source, drain region 20
1 ・・・・・・・・・LOOC）J202・・・・
. . . Gate electrode 203 . . . Source, drain region ladder i-
Applicant: Seiko Epson Co., Ltd. Agent Patent attorney: Kizobe Suzuki (and 1 other person) Yoz Ig

Claims (1)

[Claims] (1) LOCOS (Local Oxidation of Silicon, hereinafter LOCO)
By having a plurality of transistors in a region surrounded and separated by a region (abbreviated as S) and using the transistor itself in this region as an element isolation element, the element isolation position can be changed after the gate electrode forming process. A semiconductor device characterized by being selectable.