JPH10125064A - Memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To speed up operation of a sense amplifier through amplification of signal read from a memory cell by boosting up a threshold voltage using a voltage setting circuit to control a substrate voltage of a transistor forming the sense amplifier. SOLUTION: A sense amplifier S/A is activated by the signals SAP and /SAN under the condition that the potential of substrate terminals of four transistors Qn1, Qn1, Qp1, Qp2 is 0.5 × VCC. In this case, the sense amplifier S/A senses and amplifies only a light change of voltage of the bit line explained above and also amplifies the potentials of the bit line pair BL and/BL respectively to H and L levels. As explained above, data is read from the memory cell.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a sense amplifier for amplifying a signal read from a memory cell in a semiconductor memory device.

[0002]

2. Description of the Related Art A conventional sense amplifier circuit will be described in detail with reference to the drawings. FIG. 1 shows a conventional DRAM cell and a sense amplifier unit. As shown in FIG. 1, a memory cell MC is connected to the intersection of the bit line pair BL and / BL and the word line WL. However, here, the bit line / BL means an inverted signal of the bit line BL.

In FIG. 1, transistors Qn1, Qn
Reference numeral 2 denotes an N-channel transistor constituting the sense amplifier section, and transistors Qp1 and Qp2 represent P-channel transistors constituting the sense amplifier section.

The sources of the transistors Qn1 and Qn2 are connected to a control signal / SAN, and the sources of Qp1 and Qp2 are connected to a control signal SAP. The drains of Qn1 and Qp1 are connected to BL, and the drains of Qn2 and Qp2 are connected to bit line / BL. The gates of Qn1 and Qp1 are connected to / BL, and the gates of Qn2 and Qp2 are connected to B.
L. The back gates of Qn1 and Qn2 are set to Vnwell, and the back gates of Qp1 and Qp2 are set to Vp.
Connected to the well.

Next, the operation of this circuit will be described. FIG.
Indicates the timing. First, when WL goes high and the transistor of the memory cell MC turns on, cell information is transmitted to the bit line to BL.

Now, assume that "1" has been written in the cell. As a result, the voltage of bit line BL slightly increases. Next, by setting SAP high and / SAN low, the sense amplifier unit is activated.

In this case, since the voltage of BL is slightly higher than / BL, the current driving capability of Qn2 becomes larger than the current driving capability of Qn1, and therefore / BL is pulled down to the voltage of / SAN, that is, Low. . Similarly, since the current driving capability of Qp1 is larger than the current driving capability of Qp2,
BL becomes the voltage of SAP, that is, High. Thus, the signal is amplified by the BL pair.

[0008]

Next, the leakage current of the MOS transistor used in the sense amplifier will be described in detail with reference to the drawings. FIG. 3 shows an N-channel MOS transistor, which is the Q-channel MOS transistor of FIG.
n1 is schematically shown.

S, G, D, and B denote a source terminal, a gate terminal, a drain terminal, and a substrate terminal (back gate), respectively.
G, VD, and VB. Also, the contacts A and B shown in FIG.
Correspond to A and B in FIG.

Due to the structure of the MOS transistor, a PN junction is formed between the source S and the substrate B and between the drain D and the substrate (see FIG. 3). A forward voltage (VS <
When VB) is applied, a leak current flows between the source S and the substrate B. The same applies between the drain D and the substrate.

Therefore, when using N-type transistors, the voltage of the substrate must be set so that no leak current flows between them. That is, a reverse voltage (VS> VB, VD> VB) may be applied to the PN junction.

Now, assuming that this DRAM is a 0.5 × VCC precharge type DRAM, since the drain terminal D is connected to the bit line, the potential amplitude of the contact A becomes
0.5 VCC to 0.5 × VCC + dV. On the other hand, since the source terminal S is connected to the control signal / SAN, the potential amplitude of the contact B is between VSS and 0.5 × VCC.
Becomes

Therefore, normally, in an N-type transistor, a leak current can be prevented by applying a negative voltage (for example, VB = -1 V) to the substrate voltage VB. If a negative voltage is applied to the gate terminal to prevent a leak current, the threshold voltage of the MOS transistor will increase.

On the other hand, the power supply voltage in recent years has been reduced. Therefore, the ratio of the threshold voltage to the power supply voltage is relatively increasing. As a result, Qn1, Qn2, Qp
1. The operation of Qp2 becomes slow or the threshold voltage becomes 1 /
If it exceeds 2 VCC, there is a problem that it does not operate at all. An object of the present invention is to provide a semiconductor memory device that operates stably even when the power supply voltage decreases.

[0015]

According to the present invention, in order to achieve the above object, the potential of the back gate of two P-type transistors constituting a sense amplifier is set to a first initial potential. After setting the potentials of the back gates of the two N-type transistors to the second initial potential, the back gates of the four transistors are electrically connected to each other, and the potentials of the back gates are set to a predetermined value. A voltage setting circuit for setting a voltage.

That is, the voltage setting circuit sets the potential of the substrate terminal (back gate) of the transistor constituting the sense amplifier so as to increase the threshold voltage so that the leakage current does not become a problem.

As described above, the potential setting circuit controls the substrate voltage of the transistor constituting the sense amplifier,
Since the threshold voltage is increased, the transistor is easily turned on. This can solve problems such as a delay in the operation of the sense amplifier. The details will be described below.

[0018]

FIG. 4 shows a first embodiment according to the present invention. FIG. 5 shows the operation waveform. First, the connection relations of the circuits and the like will be described.

As shown in FIG. 4, a gate terminal of a memory cell including a transistor and a capacitor is connected to a word line WL, and one end of a current path of the memory cell is connected to a bit line BL. A desired word line WL and bit line BL are selected by an address signal, / RAS, / CAS or the like input from outside the storage device. However, / RAS means an inverted signal of RAS, and the same applies to / CAS.

A sense amplifier S / A is connected to each pair of bit lines BL and / BL. The sense amplifier S / A has a function of sensing and amplifying data to be written to a memory cell or data read from the memory cell via a bit line.

As shown in FIG. 4, a current path of two N-type transistors Qn1 and Qn2 connected in series is connected between a pair of bit lines BL and / BL. Also,
The gate terminal of transistor Qn1 is connected to / BL, and the gate terminal of transistor Qn2 is connected to BL.
Further, the substrate terminals of the transistors Qn1 and Qn2 are connected to the contact V
n.

Similarly, a current path of two P-type transistors Qp1 and Qp2 connected in series is connected between a pair of bit lines BL and / BL. Also, the transistor Q
The gate terminal of p1 is connected to / BL, and the gate terminal of transistor Qn2 is connected to BL. Further, the substrate terminals of the transistors Qp1 and Qp2 are connected to the contact point Vp.

The above four transistors constitute a sense amplifier S / A. In addition, control signals / SAN and SAP
Are connected to the contacts Sn and Sp, respectively, and control the operation of the sense amplifier S / A.

The voltage setting circuit comprises five transistors Qn3, Qn4, Qn5, Qp3, Qp4 and an inverter I. The current path of the transistor Qn5 is connected between the contacts Vn and Vp, and a signal SW1 for controlling ON or OFF of the transistor is supplied to the gate terminal.

The current path of the transistor Qn3 is connected between the control signal line / SAN and the contact Vn, and a control signal SW2 is supplied to its gate terminal. The current path of the transistor Qp3 is connected between the contact point VP and the control signal line SAP, and its gate terminal is supplied with the control signal / SW2.

The current path of the transistor Qn4 is connected between the contact point Vn and the low power supply voltage VSS, the current path of the transistor Qp4 is connected between the contact point Vp and the public power supply voltage VCC, and the transistors Qn4 and Qp4 The gate terminal is connected via the inverter I. The control signal SW3 is supplied to the gate terminal of the transistor Qn4.

Next, the operation of this circuit will be described with reference to the drawings. FIG. 5 shows operation waveforms. As can be seen from FIG. 5, "1" data is stored in the memory cell, and the data is read as an example.

(Operation During Period T1) During this time, the storage device is in a precharge state (standby state). That is,
Bit line pair BL and / BL and sense amplifier control signal S
AP and / SAN are all precharge potentials (for example,
0.5 × VCC). However, in this case, 0.5 × V
A CC precharge method is assumed. Also, during this period, the signal SW3 is at H, so that the transistors Qn4 and Qp4 are ON. Therefore, the potential of the contact Vn becomes VSS, and the potential of the contact Vp becomes VCC.

Since the contact Vn is connected to the substrate terminals of the transistors Qn1 and Qn2, VSS is applied to those substrate terminals. On the other hand, since the contact point Vp is connected to the substrate terminals of the transistors Qp1 and Qp2, VCC is applied to those substrate terminals.

(Operation During Period T2) Next, the signal SW3
Changes from H to L, the transistors Qn4 and Qp4 are turned off.

Next, the signal SW1 changes from L to H, and the transistor Qn5 turns ON. Therefore, since the contact point Vn and the contact point Vp are short-circuited, the potential of both Vn and Vp becomes 0.5 × VCC due to the movement of the electric charge. That is, the substrate terminals of the four transistors Qn1, Qn1, Qp1, and Qp2 are all 0.5 × VCC.

As described above, in order to prevent leakage current,
Conventionally, an N-type transistor Qn forming a sense amplifier
1 and Qn2 have a low power supply voltage VSS on their substrate terminals, and P-type transistors Qp1 and Qp2 have a high power supply voltage V
Although CC was applied, in the sense amplifier according to the present invention, the substrate terminals of the four transistors were all set to 0.5 × V
It should be noted that the voltage is applied to CC (precharge voltage).

At almost the same time, the signal / RAS
Changes from L to H, the word line is selected and the selected word line W
The potential of L changes from L to H. A bit line pair is selected by a signal / CAS (not shown), and the potential of the bit line BL slightly rises from the precharge potential due to data stored in the memory cell.

Then, the four transistors Qn1, Qn
1. The potentials of the substrate terminals of Qp1 and Qp2 are all 0.5 × V
In the state of CC, the sense amplifier S / A is activated by the signals SAP and / SAN. At this time, the sense amplifier S /
A senses the above-mentioned slight change in the potential of the bit line and amplifies it, and the potentials of the bit line pair BL and / BL are amplified to H and L, respectively. As described above, data is read from the memory cell.

(Operation During Period T3) Next, the signal / RA
S changes from L to H, and the signal / CAS (not shown) also changes to L.
To H, and the storage device enters a standby state. Thus, a series of read operations is completed.

In this embodiment, as described above, the substrate voltages of the two N-type transistors constituting the sense amplifier are set to a predetermined potential. The predetermined potential is set so that the substrate voltage of the transistor is such that an inversion layer is easily formed and a leak current does not flow between the substrate terminal and the diffusion layer. For example, if a precharge potential (0.5 × VCC) is used as the predetermined potential, it is not necessary to set a voltage dedicated to the predetermined voltage. Of course, as long as the above condition is satisfied, the potential need not be the precharge potential. The same applies to the case of two P-type transistors constituting a sense amplifier.

Further, as shown in FIG. 6, it is preferable that the above-mentioned voltage generating circuit is disposed adjacent to the sense amplifier, for example, in the same direction as the direction parallel to the bit line pair. This is because the occupied area can be reduced.

Since the present embodiment is configured as described above, the substrate voltage of the transistor constituting the sense amplifier is set to such a level that the inversion layer is easily formed and the leakage current does not flow between the substrate terminal and the diffusion layer. Since the potential is set, the sensing operation can be performed at high speed and with low power consumption.

Further, if the substrate voltage of the transistor constituting the sense amplifier is set to the precharge voltage, no new dedicated voltage is required. If the voltage generation circuit is arranged in the same direction as the direction parallel to the bit line pair, the occupied area can be reduced.

Next, a second embodiment will be described in detail with reference to the drawings. FIG. 7 shows a second embodiment according to the present invention. FIG. 8 shows the operation waveform. First, the connection relations of the circuits and the like will be described.

The difference from the first embodiment is that the current path of the transistor Qn5 is connected to the contacts Vn and Vp via the diode-connected transistors Qn6 and Qp5, respectively. Hereinafter, this will be described in more detail.

As shown in FIG. 7, the gate terminal of a memory cell composed of a transistor and a capacitor is connected to a word line WL, and one end of a current path of the memory cell is connected to a bit line BL. A desired word line WL and bit line BL are selected by an address signal, / RAS, / CAS or the like input from outside the storage device. However, / RAS means an inverted signal of RAS, and the same applies to / CAS.

A sense amplifier S / A is connected to each pair of bit lines BL and / BL. The sense amplifier S / A has a function of sensing and amplifying data to be written to a memory cell or data read from the memory cell via a bit line.

As shown in FIG. 7, a current path of two N-type transistors Qn1 and Qn2 connected in series is connected between a pair of bit lines BL and / BL. Also,
The gate terminal of transistor Qn1 is connected to / BL, and the gate terminal of transistor Qn2 is connected to BL.
Further, the substrate terminals of the transistors Qn1 and Qn2 are connected to the contact V
n.

Similarly, a current path of two P-type transistors Qp1 and Qp2 connected in series is connected between a pair of bit lines BL and / BL. Also, the transistor Q
The gate terminal of p1 is connected to / BL, and the gate terminal of transistor Qn2 is connected to BL. Further, the substrate terminals of the transistors Qp1 and Qp2 are connected to the contact point Vp.

The sense amplifier S / A is constituted by the above four transistors. In addition, control signals / SAN and SAP
Are connected to the contacts Sn and Sp, respectively, and control the operation of the sense amplifier S / A.

The voltage setting circuit includes five transistors Qn3, Qn4, Qn5, Qp3, Qp4, Qn6,
Qp6 and inverter I. Transistor Q
One end of the current path n5 is connected to a contact Vn via a diode-connected transistor Qn5, the other end is connected between contacts Vp via a diode-connected transistor Qn6, and the gate terminal is turned on or off of the transistor.
Signal SW1 is supplied to control

The current path of the transistor Qn3 is connected between the control signal line / SAN and the contact Vn, and the control signal SW2 is supplied to its gate terminal. The current path of the transistor Qp3 is connected between the contact point VP and the control signal line SAP, and its gate terminal is supplied with the control signal / SW2.

The current path of the transistor Qn4 is connected between the contact point Vn and the low power supply voltage VSS, the current path of the transistor Qp4 is connected between the contact point Vp and the public power supply voltage VCC, and the transistors Qn4 and Qp4 The gate terminal is connected via the inverter I. The control signal SW3 is supplied to the gate terminal of the transistor Qn4.

Next, the operation of this circuit will be described with reference to the drawings. FIG. 8 shows operation waveforms. As can be seen from FIG. 8, "1" data is stored in the memory cell, and the data is read as an example.

The difference from the first embodiment is that the presence of diode-connected transistors Qn6 and Qp5
The potentials of the contacts Vn and Vp are controlled. The details will be described below.

(Operation During Period T1) During this time, the storage device is in the precharge state (standby state). That is,
Bit line pair BL and / BL and sense amplifier control signal S
AP and / SAN are all precharge potentials (for example,
0.5 × VCC). However, in this case, 0.5 × V
A CC precharge method is assumed. Also, during this period, the signal SW3 is at H, so that the transistors Qn4 and Qp4 are ON. Therefore, the potential of the contact Vn becomes VSS and the potential of the contact Vp becomes VCC.

Since the contact Vn is connected to the substrate terminals of the transistors Qn1 and Qn2, VSS is applied to those substrate terminals. On the other hand, since the contact Vp is connected to the substrate terminals of the transistors Qp1 and Qp2, the voltage of VCC is applied to those substrate terminals.

(Operation During Period T2) Next, the signal SW3
Changes from H to L, the transistors Qn4 and Qp4 are turned off.

Next, the signal SW1 changes from L to H, and the transistor Qn5 turns ON. Therefore, the contact Vn and the contact Vp are short-circuited via the transistors Qn5, Qn6 and Qp5, so that the electric charge moves. In this case, the contacts Vn and V
transistors Qn6, Qp diode-connected between
When the potential corresponding to the voltage drop of 5 is generated and the time elapses, the potentials of both the contacts Vn and Vp become 0.5 × VCC.

This embodiment is characterized in that the sensing operation is completed before the potentials of the contacts Vn and Vp reach a balanced value of 0.5 × VCC. This state is shown in a portion X in FIG. The potential of the contact point Vp is 0.5 × VC from VCC
C, and the potential of the contact Vn is VS.
The sensing operation is performed at the potential V2 before rising from S to 0.5 × VCC.

At almost the same time, the signal /
RAS changes from L to H to select a word line, and the potential of the selected word line WL changes from L to H. A bit line pair is selected by a signal / CAS (not shown), and the potential of the bit line BL slightly rises from the precharge potential due to data stored in the memory cell.

Then, with the potentials of the substrate terminals of the transistors Qn1 and Qn1 forming the sense amplifier at V1 and the potentials of the substrate terminals of the transistors Qp1 and Qp2 at V2, the sense amplifier S / S is generated by the signals SAP and / SAN.
A is activated.

At this time, the sense amplifier S / A senses the slight change in the potential of the bit line and amplifies it, and the potentials of the bit line pair BL and / BL are amplified to H and L, respectively. As described above, data is read from the memory cell.

(Operation During Period T3) Next, the signal / RA
S changes from L to H, and the signal / CAS (not shown) also changes to L.
To H, and the storage device enters a standby state. Thus, a series of read operations is completed.

In the first embodiment, at the time of sensing, the potential of the bit line and the potential of the substrate of the transistor constituting the sense amplifier are substantially equal to 0.5 × VCC. In some cases, it is necessary to apply a certain amount of reverse bias between the diffusion layer used as the source and the drain and the substrate terminal.

Therefore, in the present embodiment, the reverse bias can be created by utilizing the potential difference between the diode-connected transistors Qn6 and Qp5, and the leak current can be reliably prevented.

As shown in FIG. 7, it is preferable that the above-mentioned voltage generating circuit be disposed adjacent to the sense amplifier, for example, in the same direction as the direction parallel to the bit line pair. This is because the occupied area can be reduced.

Since the present embodiment is configured as described above, the substrate voltage of the transistor constituting the sense amplifier can be easily controlled by the inversion layer, and the leak current can be reliably prevented between the substrate terminal and the diffusion layer. Since the potential is at about the same level, the sensing operation can be realized at high speed and with low power consumption.

In addition, since the substrate voltage of the transistor constituting the sense amplifier is set to a desired potential by transferring the electric charge, a new dedicated voltage is not required. If the voltage generation circuit is arranged in the same direction as the direction parallel to the bit line pair, the occupied area can be reduced.

Next, a third embodiment will be described in detail with reference to the drawings. As shown in FIG. 9, resistors R1 and R2 are used instead of the transistors Qn6 and Qp5 shown in FIG.
You are using Others are exactly the same as the second embodiment.

As described above, in this embodiment, as in the second embodiment, the substrate voltage is generated by utilizing the movement of electric charges. Therefore, the equilibrium state is established after a certain period of time, and the sensing operation is performed before the equilibrium state is reached. That is, the sensing operation is performed using the resistance component and the capacitance component of the wiring while the time until the equilibrium state is obtained. The operation waveform is exactly the same as in FIG.

Next, a method of setting the values of the resistors R1 and R2 will be described. At the time of the sensing operation, that is, at the timing when the potential of the bit line changes by the minute potential dV, the time constant is set so that the potential of the contact Vn <0.5 × VCC−dV and the potential of the contact Vp> 0.5 × VCC + dV. Are set, and the resistance values R1 and R2 are set from this time constant.

Since the present embodiment is configured as described above, the sense amplifier includes transistors Qn1, Qn2, Qn
Leakage current at p1 and Qp2 can be avoided, and
High-speed sensing operation becomes possible.

Next, a fourth embodiment will be described in detail with reference to the drawings. FIG. 10 shows a detailed circuit diagram according to the fourth embodiment, and FIG. 11 shows operation waveforms thereof.

As shown in FIG. 10, the gate terminals of the memory cells MC2 and MC3 each comprising a transistor and a capacitor are connected to a word line WL, and one end of the current path of the memory cell is connected to a bit line BL. In addition, an address signal, / RAS,
/ CAS or the like, the desired word line WL and bit line B
L is selected. However, / RAS means an inverted signal of RAS, and the same applies to / CAS.

Further, sense amplifiers S / A2 and S / A3 are connected to each pair of bit lines BL and / BL. The sense amplifiers S / A2 and S / A3 have a function of sensing and amplifying data to be written to or read from a memory cell via a bit line.

In this sense amplifier S / A2, two N-type transistors Qn1, Qn1,
The current path of Qn2 is connected between bit line pair BL, / BL. The gate terminal of the transistor Qn1 is /
The gate terminal of transistor Qn2 is connected to BL, respectively. Further, the substrate terminals of the transistors Qn1 and Qn2 are connected to the contact Vn.

Similarly, in the sense amplifier S / A3, two P-type transistors Qp1,
The current path of Qp2 is connected between bit line pair BL, / BL. The gate terminal of the transistor Qp1 is /
The gate terminal of transistor Qn2 is connected to BL, respectively. Further, the substrate terminals of the transistors Qp1 and Qp2 are connected to the contact point Vp.

The voltage setting circuit includes a transistor Qn5
To Qn7 and Qp5 to Qp8. In this voltage setting circuit, a low power supply voltage VS is connected to a contact Vn.
S is connected via transistor Qn6.

The high power supply voltage VCC is connected to the contact point Vp via the transistor Qp5. The current path of the transistor Qn5 is connected between the contact N1 and the power supply voltage VSS, and the control signal / SEN is connected to the gate terminal, and the contact Vn is connected to the substrate terminal.

The current path of the transistor Qp5 is connected between the contact N2 and the power supply voltage VCC. The control signal / SEP is connected to the gate terminal, and the contact Vp is connected to the substrate terminal. The current path of the transistor Qn6 is connected between the contact point Vn and the power supply voltage VSS, and the signal S
W2 is input. The current path of the transistor Qp7 is connected between the contact point Vp and the power supply voltage VCC, and the signal / SW2 is input to the gate terminal.

The current path of the transistor Qn7 is connected between the contact point Vn and the contact point N1, and the signal SW3 is input to the gate terminal. The current path of the transistor Qp8 is connected between the contact point Vp and the contact point N2, and the signal / SW3 is input to the gate terminal.

Further, the current path of the transistor Qp6 is connected between the contact point N1 and the contact point N2, and the signal SW1 is input to the gate terminal. Next, the operation of this circuit will be described with reference to the drawings. FIG. 11 shows operation waveforms. As can be seen from FIG. 11, "1" data is stored in the memory cell, and the data is read as an example.

(Operation During Period T1) During this time, the storage device is in the precharge state (standby state). That is,
Bit line pair BL and / BL and sense amplifier control signal S
AP and / SAN are all precharge potentials (for example,
0.5 × VCC). However, in this case, 0.5 × V
A CC precharge method is assumed. Also, during this period, the signal SW2 is at H, so that the transistors Qn6 and Qp7 are ON. Therefore, the potential of the contact Vn becomes VSS, and the potential of the contact Vp becomes VCC.

The contact Vn is connected to the transistors Qn1, Qn
Since they are connected to the substrate terminals of n2, Qn3, and Qn4, VSS is applied to those substrate terminals. On the other hand, the contacts Vp are connected to the transistors Qp1, Qp2, Qp
3, since they are connected to the substrate terminals of Qp4, VCC is applied to those substrate terminals.

(Operation During Period T2) Next, the signal SW2
Changes from H to L, the transistors Qn6 and Qp7 are turned off.

Since SW3 changes from L to H and signal SW1 changes from L to H, transistors Qn7 and Qp
8. Qp6 turns ON. Therefore, the substrate terminals of the eight transistors Qn1 to Qn4 and Qp1 to Qp4 are all short-circuited, and Vn and Vp (N1 and Np
The potentials of 2) are both 0.5 × VCC. That is, 8
The substrate terminals of the transistors Qn1 to Qn4 and Qp1 to Qp4 are all 0.5 × VCC.

As described above, in order to prevent leakage current,
Conventionally, an N-type transistor Qn forming a sense amplifier
1 and Qn2 have a low power supply voltage VSS on their substrate terminals, and P-type transistors Qp1 and Qp2 have a high power supply voltage V
Although CC has been applied, in the sense amplifier according to the present invention, eight transistors Qn1 to Qn4 and Qp1 to Qp1 are applied.
It should be noted that all the substrate terminals of Qp4 are applied to 0.5 × VCC (precharge voltage).

At almost the same time, the signal / RAS
Changes from L to H, the word line is selected and the selected word line W
The potential of L changes from L to H. A bit line pair is selected by a signal / CAS (not shown), and the potential of the bit line BL slightly rises from the precharge potential due to data stored in the memory cell.

Then, the eight transistors Qn1 to Qn
4 and the potentials of the substrate terminals of Qp1 to Qp4 are all 0.5 ×
In the state of VCC, the sense amplifier S / A is activated by the signals SAP and / SAN.

At this time, the sense amplifier S / A senses the slight change in the potential of the bit line and amplifies it, and the potentials of the bit line pair BL and / BL are amplified to H and L, respectively. As described above, data is read from the memory cell.

(Operation During Period T3) Next, the signal / RA
S changes from L to H, and the signal / CAS (not shown) also changes to L.
To H, and the storage device enters a standby state. Thus, a series of read operations is completed.

In this embodiment, as described above, the substrate voltage of the N-type transistor constituting the sense amplifier is set to a predetermined potential. The predetermined potential is set so that the substrate voltage of the transistor is such that an inversion layer is easily formed and a leak current does not flow between the substrate terminal and the diffusion layer.
For example, the precharge potential (0.5 ×
If VCC) is used, there is no need to set a voltage dedicated to the predetermined voltage. Of course, as long as the above condition is satisfied, the potential need not be the precharge potential. The same applies to the case of a P-type transistor constituting a sense amplifier.

Since the present embodiment is configured as described above, the substrate voltage of the transistor constituting the sense amplifier is set to such a level that the inversion layer is easily formed and the leakage current does not flow between the substrate terminal and the diffusion layer. Since the potential is set, the sensing operation can be performed at high speed and with low power consumption.

Further, if the substrate voltage of the transistor constituting the sense amplifier is set to the precharge voltage, no new dedicated voltage is required. Further, in the present embodiment, the substrate voltage of the transistor constituting the sense amplifier is set to a predetermined potential by using the movement of electric charge. However, a voltage setting circuit for setting the potential is provided by two bit line pairs. Are provided in common. Therefore, the number of voltage setting circuits can be reduced.

[0092]

Since the present invention is configured as described above, the substrate voltage of the transistor constituting the sense amplifier can be controlled, and the transistor is easily turned on. This enables a high-speed operation of the sense amplifier.

[Brief description of the drawings]

FIG. 1 is a detailed circuit diagram showing a sense amplifier portion of a conventional DRAM.

FIG. 2 is a diagram showing operation waveforms of the circuit diagram shown in FIG. 1;

FIG. 3 is a cross-sectional view of a transistor for explaining leakage current.

FIG. 4 is a detailed circuit diagram of a sense amplifier part according to the first embodiment of the present invention.

FIG. 5 is a diagram showing operation waveforms of the circuit diagram shown in FIG. 4;

FIG. 6 is a diagram illustrating an arrangement location of a voltage generation circuit.

FIG. 7 is a detailed circuit diagram of a sense amplifier part according to a second embodiment of the present invention.

FIG. 8 is a diagram showing operation waveforms of the circuit diagram shown in FIG. 7;

FIG. 9 is a detailed circuit diagram of a sense amplifier part according to a third embodiment of the present invention.

FIG. 10 is a detailed circuit diagram of a sense amplifier part according to a fourth embodiment of the present invention.

FIG. 11 is a diagram showing operation waveforms of the circuit diagram shown in FIG. 10;

[Explanation of symbols]

 Qn1 to Qn5 N-type transistor Qp1 to Qp4 P-type transistor WL Word line BL Bit line

Claims (7)

[Claims] 1. A memory cell array in which memory cells each comprising an information storage capacitor and an information transfer transistor are arranged in a matrix, and a memory cell in a column direction of the memory cells arranged in a matrix is selected. A bit line pair, a word line for selecting a memory cell in a row direction of the memory cells arranged in a matrix, and a current path of two N-type transistors are connected in series between the bit line pair. An N-type sense amplifier having gate terminals of the two N-type transistors cross-connected to the bit line, and a current path of two P-type transistors connected in series between the bit line pair; A P-type sense amplifier in which gate terminals of two P-type transistors are cross-connected to the bit line; and a potential of a back gate of the two P-type transistors is a first initial potential. Set, after setting the potential of the back gate of the two N-type transistors in the second initial potential,
And a voltage setting circuit for electrically connecting the back gates of the four transistors to each other and setting the potential of the back gates to a predetermined voltage. 2. A bit line pair for selecting a memory cell in a column direction of a memory cell array in which a plurality of memory cells are arranged in a matrix, and a bit line pair for selecting a memory cell in a row direction of the memory cell array. An N-type sense amplifier in which a word line and a current path of two N-type transistors are connected in series between the bit line pair, and gate terminals of the two N-type transistors are cross-connected to the bit lines; A P-type sense amplifier in which current paths of two P-type transistors are connected in series between the bit line pairs, and gate terminals of the two P-type transistors are cross-connected to the bit lines; After charging the back gate potentials of the two P-type transistors to a first initial potential and the back gate potentials of the two N-type transistors to a second initial potential, the four transistors are charged. And a voltage setting circuit for setting a potential of a back gate of the transistor to a predetermined potential by movement of electric charge. 3. The voltage setting circuit according to claim 1, wherein the sensing operation is completed during a period from the initial potential to the predetermined potential of the back gates of the four transistors. A storage device as described. 4. The storage device according to claim 1, wherein said voltage setting circuit is arranged between a pair of bit lines to which said sense amplifier is connected. 5. The memory device according to claim 1, wherein said predetermined voltage is substantially equal to a precharge voltage. 6. The storage device according to claim 1, wherein said first initial potential is a high power supply voltage, and said second initial potential is a low power supply voltage. 7. The storage device according to claim 1, wherein said voltage setting circuit is provided commonly to adjacent bit line pairs.