CN112687301B - Memory cell and memory - Google Patents
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- CN112687301B CN112687301B CN202011636432.3A CN202011636432A CN112687301B CN 112687301 B CN112687301 B CN 112687301B CN 202011636432 A CN202011636432 A CN 202011636432A CN 112687301 B CN112687301 B CN 112687301B
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- 230000015654 memory Effects 0.000 title claims abstract description 52
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 54
- 239000010703 silicon Substances 0.000 claims abstract description 54
- 239000012212 insulator Substances 0.000 claims abstract description 42
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 53
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Abstract
The invention relates to a memory cell and a memory, comprising a bit cell, a fully depleted silicon-on-insulator and a back pressure lead; the bit unit includes: the first transistor, the second transistor, the first inverter, the second inverter, the first transistor and the second transistor are all formed on the fully-depleted silicon-on-insulator, the back pressure lead is led out from the inside of the fully-depleted silicon-on-insulator and extends to the outside of the fully-depleted silicon-on-insulator, the back pressure lead comprises a first back pressure lead corresponding to the first transistor and/or a second back pressure lead corresponding to the second transistor, the first back pressure lead is used for applying a first preset back pressure to the first transistor, and the second back pressure lead is used for applying a second preset back pressure to the second transistor. The memory cell and the memory fully utilize the special back bias voltage process of the fully depleted silicon on insulator, thereby optimizing and improving the bit cell to realize different purposes.
Description
Technical Field
The present disclosure relates to the field of memory technologies, and in particular, to a memory unit and a memory.
Background
Current memories, such as Static Random-Access memories (SRAM), are basically in bit cells (bitcells). The design of the bit cell is very important, and the development of a suitable set of bit cells is very important for chip timing closure, physical closure, and finally the performance power supply area (PPA, performance Power Area) of the chip.
In the conventional technology, the development and design of the bit unit are mainly focused on a planar Bulk Silicon (Bulk Silicon) process and a fin field effect transistor (FinFET) process, but for a fully depleted Silicon on insulator (FDSOI, fully Depleted Silicon On Insulator) process, the bit unit on the planar Bulk Silicon process is often simply directly used on the FDSOI process, and the unique process characteristics of the fully depleted Silicon on insulator are not fully utilized to optimize and improve the bit unit.
Disclosure of Invention
Based on this, it is necessary to provide a memory cell and a memory for the above-mentioned problems.
A memory cell comprising a bit cell, a fully depleted silicon on insulator, and a back pressure lead;
the bit cell includes:
the first transistor is provided with a first electric connection end, a second electric connection end and a third electric connection end; a first electric connection end of the first transistor is connected with a word line of the bit unit, and a second electric connection end of the first transistor is connected with an inverted bit line of the bit unit;
the second transistor is provided with a first electric connection end, a second electric connection end and a third electric connection end; the first electric connection end of the second transistor is connected with the word line of the bit cell, and the second electric connection end of the second transistor is connected with the bit line of the bit cell;
a first inverter having an input and an output; the input end of the first inverter is connected with the third electric connection end of the first transistor;
a second inverter having an input and an output; the input end of the second inverter is connected with the third electric connection end of the second transistor and the output end of the first inverter; the output end of the second inverter is connected with the input end of the first inverter;
wherein the first transistor and the second transistor are both formed on the fully depleted silicon on insulator, the back pressure lead is led out from the inside of the fully depleted silicon on insulator and extends to the outside of the fully depleted silicon on insulator, the back pressure lead comprises a first back pressure lead corresponding to the first transistor and/or a second back pressure lead corresponding to the second transistor, the first back pressure lead is used for applying a first preset back pressure to the first transistor, and the second back pressure lead is used for applying a second preset back pressure to the second transistor.
In one embodiment, the first inverter includes a third transistor and a fourth transistor, each having a first electrical connection, a second electrical connection, and a third electrical connection; the first electric connection end of the third transistor is connected with the first electric connection end of the fourth transistor and is used as the input end of the first inverter, the second electric connection end of the third transistor is connected with a power supply, the second electric connection end of the fourth transistor is grounded, and the third electric connection end of the third transistor is connected with the third electric connection end of the fourth transistor and is used as the output end of the first inverter;
the second inverter comprises a fifth transistor and a sixth transistor, wherein the fifth transistor and the sixth transistor are provided with a first electric connection end, a second electric connection end and a third electric connection end; the first electric connection end of the fifth transistor is connected with the first electric connection end of the sixth transistor and is used as the input end of the second inverter, the second electric connection end of the fifth transistor is connected with a power supply, the second electric connection end of the sixth transistor is grounded, and the third electric connection end of the fifth transistor is connected with the third electric connection end of the sixth transistor and is used as the output end of the first inverter;
wherein the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are all formed on the fully depleted silicon on insulator, the back pressure lead further includes at least one of a third back pressure lead corresponding to the third transistor, a fourth back pressure lead corresponding to the fourth transistor, a fifth back pressure lead corresponding to the fifth transistor, and a sixth back pressure lead corresponding to the sixth transistor, the third back pressure lead is used for applying a third preset back pressure to the third transistor, the fourth back pressure lead is used for applying a fourth preset back pressure to the fourth transistor, the fifth back pressure lead is used for applying a fifth preset back pressure to the fifth transistor, and the sixth back pressure lead is used for applying a sixth preset back pressure to the sixth transistor.
In one embodiment, the first transistor, the second transistor, the fourth transistor, and the sixth transistor are NMOS transistors, and the third transistor and the fifth transistor are PMOS transistors.
In one embodiment, the first preset back pressure, the second preset back pressure, the third preset back pressure, the fourth preset back pressure, the fifth preset back pressure, and the sixth preset back pressure are all forward back pressures.
In one embodiment, the third preset back pressure and the fifth preset back pressure are equal, and the first preset back pressure, the second preset back pressure, the fourth preset back pressure and the sixth preset back pressure are equal.
In one embodiment, the first preset back pressure, the second preset back pressure, the third preset back pressure, the fourth preset back pressure, the fifth preset back pressure, and the sixth preset back pressure are all within a range from a negative power supply voltage of the memory cell to twice the power supply voltage of the memory cell.
In one embodiment, the operating states of the memory cell include normal and high speed states;
in a normal state, the third preset back pressure and the fifth preset back pressure are equal to the power supply voltage of the storage unit, and the first preset back pressure, the second preset back pressure, the fourth preset back pressure and the sixth preset back pressure are all zero;
and in a high-speed state, the third preset back pressure and the fifth preset back pressure are equal to the negative power supply voltage of the storage unit to zero, and the first preset back pressure, the second preset back pressure, the fourth preset back pressure and the sixth preset back pressure are equal to one to two times of the power supply voltage of the storage unit.
In one embodiment, the fully depleted silicon-on-insulator comprises, in order, a stack of:
a bottom silicon layer;
an intermediate insulating layer; and
a top silicon layer;
wherein the backpressure leads extend from the bottom silicon layer to the outer surface of the top silicon layer.
In one embodiment, each back pressure lead is located below the gate of a corresponding transistor at one end of the underlying silicon layer.
A memory comprising a memory cell as claimed in any preceding claim.
The memory cell and the memory combine the bit cell and the fully depleted silicon on insulator, and the back pressure lead is led out from the inside of the fully depleted silicon on insulator and extends to the outside of the fully depleted silicon on insulator, so that back pressure can be applied to the first transistor and/or the second transistor in the bit cell through the back pressure lead, thereby fully utilizing the special back bias process of the fully depleted silicon on insulator, realizing the influence of the channel of the transistor in the bit cell through the adjustment of the back bias, and optimizing and improving the bit cell to realize different purposes, such as increasing the reading and writing speed of the bit cell to data, reducing leakage current and the like.
Drawings
In order to more clearly illustrate the technical solutions of embodiments or conventional techniques of the present application, the drawings required for the descriptions of the embodiments or conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
FIG. 1 is a circuit diagram of a bit cell in one embodiment;
FIG. 2 is a schematic diagram of a memory cell according to an embodiment.
Detailed Description
In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Examples of the present application are given in the accompanying drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that the terms "first," "second," and the like, as used herein, may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element. For example, a first resistance may be referred to as a second resistance, and similarly, a second resistance may be referred to as a first resistance, without departing from the scope of the present application. Both the first resistor and the second resistor are resistors, but they are not the same resistor.
It is to be understood that in the following embodiments, "connected" is understood to mean "electrically connected", "communicatively connected", etc., if the connected circuits, modules, units, etc., have electrical or data transfer between them.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Also, the term "and/or" as used in this specification includes any and all combinations of the associated listed items.
The application provides a memory cell. The memory cell includes a bit cell, a fully depleted silicon on insulator, and a back pressure lead. The bit cell includes a first transistor, a second transistor, a first inverter, and a second inverter. The first transistor is provided with a first electric connection end, a second electric connection end and a third electric connection end. The first electrical connection of the first transistor is connected to the word line of the bit cell and the second electrical connection of the first transistor is connected to the bit line of the bit cell. The second transistor has a first electrical connection terminal, a second electrical connection terminal, and a third electrical connection terminal. The first electrical connection of the second transistor is connected to the word line of the bit cell and the second electrical connection of the second transistor is connected to the bit line of the bit cell. The first inverter has an input and an output. The input terminal of the first inverter is connected to the third electrical connection terminal of the first transistor. The second inverter has an input and an output. The input end of the second inverter is connected with the third electric connection end of the second transistor and the output end of the first inverter, and the output end of the second inverter is connected with the input end of the first inverter.
Wherein the first transistor and the second transistor are both formed on fully depleted silicon on insulator. The back pressure lead leads from the interior of the fully depleted silicon on insulator and extends to the exterior of the fully depleted silicon on insulator. The back pressure leads include a first back pressure lead corresponding to the first transistor and/or a second back pressure lead corresponding to the second transistor. The first back pressure lead is used for applying a first preset back pressure to the first transistor. The second back pressure lead is used for applying a second preset back pressure to the second transistor.
For example, referring to fig. 1, the bit cell 10 includes a first transistor N1, a second transistor N2, a first inverter 11, and a second inverter 12. The first electrical connection 1 of the first transistor N1 is connected to the word line WL of the bit cell 10 and the second electrical connection 2 of the first transistor N1 is connected to the bit bar bl| of the bit cell 10. The bit-bar line bl| may be the bit-bar line of the bit line BL. The first electrical connection 1 of the second transistor N2 is connected to the word line WL of the bit cell 10 and the second electrical connection 2 of the second transistor N2 is connected to the bit line BL of the bit cell.
The input a of the first inverter 11 is connected to the third electrical connection 3 of the first transistor N1. The input c of the second inverter 12 is connected to the third connection 3 of the second transistor N2 and to the output b of the first inverter 11, and the output of the second inverter 12 is connected to the input of the first inverter 11. The first inverter 11 and the second inverter 12 may constitute two-stage inverters so that two-stage inversion processing is performed on an input signal.
In this embodiment, the first transistor N1 and the second transistor N2 in the bit cell 10 are formed on the fully depleted silicon-on-insulator substrate. Referring to fig. 2, only one transistor 210 is shown in fig. 2, and the transistor 210 may represent either one of the first transistor N1 and the second transistor N2. In fig. 2, the back pressure lead 241 may extend from the inside of the fully depleted silicon on insulator 220 to the outside of the fully depleted silicon on insulator 220, and an extraction portion 242 may be formed at the outer surface of the fully depleted silicon on insulator 220, and the extraction portion 242 may apply a preset back pressure to a corresponding region on the fully depleted silicon on insulator 220 through the back pressure lead 241 by being connected to the back pressure lead 241 (since fig. 2 is a perspective view, the connection between the extraction portion 242 and the back pressure lead 241 is not shown), such that a preset back pressure may be applied to a corresponding transistor 210 by applying a preset back pressure to the extraction portion 242 at the outer surface of the fully depleted silicon on insulator 220.
In one embodiment, the back pressure lead 241 may include a first back pressure lead corresponding to the first transistor N1, through which a first preset back pressure V1 may be applied to the first transistor N1. In other embodiments, the back pressure lead 241 may include a second back pressure lead corresponding to the second transistor N1, through which a second preset back pressure V2 may be applied to the second transistor N2.
The first preset back pressure V1 and/or the second preset back pressure V2 may be a forward back pressure or a reverse back pressure.
When the first preset back pressure V1 and the second preset back pressure V2 are the forward back pressures, the current between the source 212 and the drain 213 of the corresponding transistor 210 can be increased, so that the data read-write speed of the memory cell is improved, and compared with the conventional technology, the power consumption of the bit cell can be reduced at the same data read-write speed by increasing the area of the bit cell; when the first preset back pressure V1 and the second preset back pressure V2 are reverse back pressures, the current between the source 212 and the drain 213 of the corresponding transistor 210 can be reduced, so that the leakage current is reduced.
The memory cell combines the bit cell 10 with the fully depleted silicon on insulator 220, and the Back pressure lead 241 is led out from the inside of the fully depleted silicon on insulator 220 and extends to the outside of the fully depleted silicon on insulator 220, so that Back pressure can be applied to the first transistor N1 and/or the second transistor N2 in the bit cell 10 through the Back pressure lead 241, thereby fully utilizing the Back Bias process (Back Bias) specific to the fully depleted silicon on insulator 220, realizing the influence on the channel of the transistor 210 in the bit cell 10 through the adjustment of the Back Bias (Back pressure) and optimizing and improving the bit cell 10 to realize different purposes, such as increasing the read-write speed of the bit cell 10 to data or reducing the leakage current.
In one embodiment, still referring to fig. 1, the first inverter 11 includes a third transistor P1 and a fourth transistor N3. The third transistor P1 and the fourth transistor N3 each have a first electrical connection 1, a second electrical connection 2, and a third electrical connection 3. The first electrical connection 1 of the third transistor P1 and the first electrical connection 1 of the fourth transistor N3 are connected and serve as the input a of the first inverter 11, the second electrical connection 2 of the third transistor P1 is connected to the power supply VDD, the second electrical connection 2 of the fourth transistor N3 is grounded, i.e. connected to the ground VSS, and the third electrical connection 3 of the third transistor P1 and the third electrical connection 3 of the fourth transistor N3 are connected and serve as the output b of the first inverter 11.
The second inverter 12 includes a fifth transistor P2 and a sixth transistor N4. The fifth transistor P2 and the sixth transistor N4 each have a first electrical connection 1, a second electrical connection 2 and a third electrical connection 3. The first electrical connection 1 of the fifth transistor P2 and the first electrical connection 1 of the sixth transistor N4 are connected and serve as the input c of the second inverter 12, the second electrical connection 2 of the fifth transistor P2 is connected to the power supply VDD, the second electrical connection 2 of the sixth transistor N4 is grounded, and the third electrical connection 3 of the fifth transistor P2 and the third electrical connection 3 of the sixth transistor N4 are connected and serve as the output d of the first inverter 12.
The third transistor P1, the fourth transistor N3, the fifth transistor P2 and the sixth transistor N4 are all formed on the fully depleted silicon on insulator 220, and the transistor 210 in fig. 2 may represent any one of the first transistor N1, the second transistor N2, the third transistor P1, the fourth transistor N3, the fifth transistor P2 and the sixth transistor N4. The back pressure lead 241 further includes at least one of a third back pressure lead corresponding to the third transistor P1, a fourth back pressure lead corresponding to the fourth transistor N3, a fifth back pressure lead corresponding to the fifth transistor P2, and a sixth back pressure lead corresponding to the sixth transistor N4. The third back pressure lead is used to apply a third preset back pressure V3 to the third transistor P1, the fourth back pressure lead is used to apply a fourth preset back pressure V4 to the fourth transistor N3, the fifth back pressure lead is used to apply a fifth preset back pressure V5 to the fifth transistor P2, and the sixth back pressure lead is used to apply a sixth preset back pressure V6 to the sixth transistor N4.
In one embodiment, the first transistor N1, the second transistor N2, the fourth transistor N3, and the sixth transistor N4 are all NMOS transistors, and the third transistor P1 and the fifth transistor P2 are all PMOS transistors.
In an embodiment, the first preset back pressure V1, the second preset back pressure V2, the third preset back pressure V3, the fourth preset back pressure V4, the fifth preset back pressure V5 and the sixth preset back pressure V6 are all forward back pressures, so that the current between the source 212 and the drain 213 of the corresponding transistor 210 is increased, thereby improving the data read-write speed of the bit unit.
In one embodiment, the third preset back pressure V3 and the fifth preset back pressure V5 are equal, and are both preset back pressures Vpw. The first preset back pressure V1, the second preset back pressure V2, the fourth preset back pressure V4 and the sixth preset back pressure V6 are equal, and are all preset back pressures Vnw.
In one embodiment, the first preset back pressure V1, the second preset back pressure V2, the third preset back pressure V3, the fourth preset back pressure V4, the fifth preset back pressure V5 and the sixth preset back pressure V6 are all within a range from the power supply voltage VDD of the memory cell to twice the power supply voltage VDD of the memory cell with negative values, i.e., within a range from-VDD to 2 VDD.
In one embodiment, the operating states of the memory cell include normal and high speed states.
In a normal state, the third preset back pressure V3 and the fifth preset back pressure V5 are equal to the power voltage VDD of the memory cell, and the first preset back pressure V1, the second preset back pressure V2, the fourth preset back pressure V4 and the sixth preset back pressure V6 are all zero.
In the high-speed state, the third preset back pressure V3 and the fifth preset back pressure V5 are equal to negative power supply voltages of the memory cells, that is, -VDD to zero, and the first preset back pressure V1, the second preset back pressure V2, the fourth preset back pressure V4 and the sixth preset back pressure V6 are equal to one to two times of the power supply voltage VDD of the memory cells.
In other embodiments, the first preset back pressure V1, the second preset back pressure V2, the third preset back pressure V3, the fourth preset back pressure V4, the fifth preset back pressure V5, and the sixth preset back pressure V6 may be selected as the forward back pressure or the reverse back pressure according to the application scenario of the memory unit, and the magnitudes of the first preset back pressure V1, the second preset back pressure V2, the third preset back pressure V3, the fourth preset back pressure V4, the fifth preset back pressure V5, and the sixth preset back pressure V6 may be set according to the driving capability of the bit unit 10.
In one embodiment, referring to fig. 2, the fully depleted silicon on insulator 220 comprises a bottom silicon layer 221, an intermediate insulating layer 222, and a top silicon layer 223, which are stacked in this order. Wherein the back pressure lead 241 extends from the bottom silicon layer 221 to the outer surface of the top silicon layer 223.
In one embodiment, referring to fig. 2, each back pressure lead 241 is located below the gate 211 of the corresponding transistor 210 at one end of the underlying silicon layer 221. A back gate 23 of the transistor 210 may be formed in the underlying silicon layer 221, and the magnitude of the current between the source 212 and the drain 213 of the transistor 210 may be varied by applying a preset back pressure to the back gate 23. When the preset back pressure is the forward back pressure, the current between the source 212 and the drain 213 of the transistor 210 increases; when the preset back pressure is the reverse back pressure, the current between the source 212 and the drain 213 of the transistor 210 decreases.
In one embodiment, the area of the bit cell 10 may be selected to be 0.108 microns square. Compared with all the current 0.124 square micron bit cells on the 22 nanometer technology, the back pressure applying mode can reduce the area of the bit cell by more than 13 percent, and when the preset back pressure is the forward back pressure and the forward back pressure is 1 to 2 times of the power supply voltage VDD of the bit cell 10, the data reading speed of the bit cell can be consistent with the data reading speed of the bit cell of 0.124 square micron in the traditional technology.
In an embodiment, shallow trench isolation structures 25 or other structures may also be formed within the silicon-on-insulator 220, and so forth.
The application also provides a memory. The memory comprises a memory unit in any of the embodiments described above.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (10)
1. A memory cell comprising a bit cell, a fully depleted silicon on insulator, and a back pressure lead;
the bit cell includes:
the first transistor is provided with a first electric connection end, a second electric connection end and a third electric connection end; a first electric connection end of the first transistor is connected with a word line of the bit unit, and a second electric connection end of the first transistor is connected with an inverted bit line of the bit unit;
the second transistor is provided with a first electric connection end, a second electric connection end and a third electric connection end; the first electric connection end of the second transistor is connected with the word line of the bit cell, and the second electric connection end of the second transistor is connected with the bit line of the bit cell;
a first inverter having an input and an output; the input end of the first inverter is connected with the third electric connection end of the first transistor;
a second inverter having an input and an output; the input end of the second inverter is connected with the third electric connection end of the second transistor and the output end of the first inverter; the output end of the second inverter is connected with the input end of the first inverter;
wherein the first transistor and the second transistor are both formed on the fully depleted silicon on insulator, the back pressure lead is led out from the inside of the fully depleted silicon on insulator and extends to the outside of the fully depleted silicon on insulator, the back pressure lead comprises a first back pressure lead corresponding to the first transistor and/or a second back pressure lead corresponding to the second transistor, the first back pressure lead is used for applying a first preset back pressure to the first transistor, and the second back pressure lead is used for applying a second preset back pressure to the second transistor;
the fully depleted silicon on insulator comprises:
a bottom silicon layer;
an intermediate insulating layer; and
a top silicon layer;
wherein the backpressure leads extend from the bottom silicon layer to the outer surface of the top silicon layer.
2. The memory cell of claim 1, wherein the first inverter comprises a third transistor and a fourth transistor, the third transistor and the fourth transistor each having a first electrical connection, a second electrical connection, and a third electrical connection; the first electric connection end of the third transistor is connected with the first electric connection end of the fourth transistor and is used as the input end of the first inverter, the second electric connection end of the third transistor is connected with a power supply, the second electric connection end of the fourth transistor is grounded, and the third electric connection end of the third transistor is connected with the third electric connection end of the fourth transistor and is used as the output end of the first inverter;
the second inverter comprises a fifth transistor and a sixth transistor, wherein the fifth transistor and the sixth transistor are provided with a first electric connection end, a second electric connection end and a third electric connection end; the first electric connection end of the fifth transistor is connected with the first electric connection end of the sixth transistor and is used as the input end of the second inverter, the second electric connection end of the fifth transistor is connected with a power supply, the second electric connection end of the sixth transistor is grounded, and the third electric connection end of the fifth transistor is connected with the third electric connection end of the sixth transistor and is used as the output end of the first inverter;
wherein the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are all formed on the fully depleted silicon on insulator, the back pressure lead further includes at least one of a third back pressure lead corresponding to the third transistor, a fourth back pressure lead corresponding to the fourth transistor, a fifth back pressure lead corresponding to the fifth transistor, and a sixth back pressure lead corresponding to the sixth transistor, the third back pressure lead is used for applying a third preset back pressure to the third transistor, the fourth back pressure lead is used for applying a fourth preset back pressure to the fourth transistor, the fifth back pressure lead is used for applying a fifth preset back pressure to the fifth transistor, and the sixth back pressure lead is used for applying a sixth preset back pressure to the sixth transistor.
3. The memory cell of claim 2, wherein the first transistor, the second transistor, the fourth transistor, and the sixth transistor are NMOS transistors, and the third transistor and the fifth transistor are PMOS transistors.
4. The memory cell of claim 3, wherein the first, second, third, fourth, fifth, and sixth pre-set back pressures are all forward back pressures.
5. The memory cell of claim 4, wherein the third and fifth predetermined back pressures are equal, and the first, second, fourth, and sixth predetermined back pressures are equal.
6. The memory cell of claim 5, wherein the first, second, third, fourth, fifth, and sixth pre-set back pressures are each within a range of a negative memory cell supply voltage to twice the memory cell supply voltage.
7. The memory cell of claim 6, wherein the operating states of the memory cell include normal and high speed states;
in a normal state, the third preset back pressure and the fifth preset back pressure are equal to the power supply voltage of the storage unit, and the first preset back pressure, the second preset back pressure, the fourth preset back pressure and the sixth preset back pressure are all zero;
and in a high-speed state, the third preset back pressure and the fifth preset back pressure are equal to the negative power supply voltage of the storage unit to zero, and the first preset back pressure, the second preset back pressure, the fourth preset back pressure and the sixth preset back pressure are equal to one to two times of the power supply voltage of the storage unit.
8. A memory cell according to any one of claims 1 to 7, wherein an extraction portion is formed on the outer surface of the fully depleted silicon on insulator, said extraction portion being connected to the back pressure lead (.
9. The memory cell of claim 8 wherein each back pressure lead is located below a gate of a corresponding transistor at one end of the underlying silicon layer.
10. A memory comprising a memory cell according to any one of claims 1 to 9.
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| CN103311250A (en) * | 2013-05-23 | 2013-09-18 | 中国科学院上海微系统与信息技术研究所 | Six-transistor static random access memory unit |
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| JP2009064860A (en) * | 2007-09-05 | 2009-03-26 | Renesas Technology Corp | Semiconductor device |
| FR2953641B1 (en) * | 2009-12-08 | 2012-02-10 | S O I Tec Silicon On Insulator Tech | HOMOGENEOUS TRANSISTOR CIRCUIT ON SEOI WITH REAR CONTROL CHANNEL BURED UNDER THE INSULATING LAYER |
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| CN101221957A (en) * | 2007-01-10 | 2008-07-16 | 中国科学院微电子研究所 | Double-gate full-depletion SOI CMOS device and preparation method thereof |
| CN103311250A (en) * | 2013-05-23 | 2013-09-18 | 中国科学院上海微系统与信息技术研究所 | Six-transistor static random access memory unit |
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