KR20080024692A - Mtcmos semiconductor integrated circuit - Google Patents

Abstract

An MTCMOS(Multithreshold voltage Complementary Metal Oxide Semiconductor) semiconductor integrated circuit is provided to increase integration degree by forming a virtual ground voltage line with a metal line having a minimum linewidth to implement a nano-scale semiconductor device. A standard cell region includes an MTCMOS logic cell(9), a non-MTCMOS logic cell(10), and a switch cell. The MTCMOS logic cell is a logic cell containing a logic circuit which is configured with a transistor having a first threshold voltage, and is connected between a source voltage line and a virtual ground voltage line. The non-MTCOM logic cell is connected between a voltage line and a ground voltage line. The switch cell is connected between the virtual ground voltage line and the ground voltage line. The switch cell includes a second transistor which has a second threshold voltage greater than the first threshold voltage to be turned on when the logic circuit is activated and to be turned off when the logic circuit is deactivated. The switch cells are distributed and arranged in the proximity of the MTCMOS logic cells including the first transistors to be connected by the virtual ground voltage lines. A terminal from a source of the first transistor included in the MTCMOS logic cell is connected to the virtual ground voltage line through a pin. The virtual ground voltage line connected to the pin is configured with a metal line having a minimum linewidth that is determined in a design rule of a semiconductor integrated circuit.

Description

MTCMOS semiconductor integrated circuit

1 shows a multithreshold voltage CMOS circuit for reducing leakage current,

2 shows an MTCMOS standard cell region in which switch cells are arranged in a row as a gate array.

3 illustrates a circuit configuration of a logic cell in a standard cell region as an embodiment of the present invention.

4 illustrates a standard cell region in which switch cells are distributed and disposed within a standard cell region presented as an embodiment of the present invention.

FIG. 5 shows a standard cell area in the case where the standard cells share one point because they are adjacent to each other.

6 shows a standard cell region spaced apart from each other.

(Explanation of symbols for the main parts of the drawing)

1: logic cell 2: switch cell

3: switch cell array 4: input pin of the inverter

5: output pin of inverter 6: virtual ground pin (VGND pin)

7: signal transmission line 8: body contact

9: MTCMOS logic cell 10: Non-MTCMOS logic cell

11: switch cell

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit including a multithreshold voltage CMOS (MTCMOS) circuit, and more particularly to a logic cell including a logic circuit composed of a first transistor having a low threshold voltage and a threshold of the first transistor. A switch cell having a threshold voltage higher than a voltage and including a second transistor that is turned on during an operation of the logic circuit and is turned off when an operation is inactive to block a leakage current flowing to the logic circuit in standby mode; The present invention relates to a semiconductor integrated circuit including a standard cell region including a switch cell.

In the CMOS LSI, power consumption is proportional to the power of the power supply voltage, so that the power consumption can be reduced by lowering the power supply voltage. However, in this case, the operation speed of the MOS transistor is reduced by reducing the power supply voltage. This reduction in operating speed can be overcome by reducing the threshold voltage of the MOS transistor. However, in this case, a problem arises in that leakage current of the MOS transistor increases during standby. In particular, in the case of nano-semiconductor devices, as chip density and frequency are gradually increased, the power consumed by the chip is gradually increased while leakage current due to lower threshold voltage and thinner gate oxide film thickness. Is increasing to an almost explosive level.

In order to solve this problem, a multithreshold voltage complementary metal-oxide semiconductor (MTCMOS) circuit is used. The MTCMOS circuit is a circuit in which a transistor having a second threshold voltage higher than the first threshold voltage is connected in series to a CMOS transistor having a low first threshold voltage. The second transistor includes a ground supply line and a virtual ground voltage. VGND) between the supply lines and / or between the supply voltage supply line and the virtual supply voltage supply line. In FIG. 1, the first transistors Q1 and Q2 are connected to the supply voltage VDD supply line and the virtual ground voltage VGND supply line, and the second transistor Q3 is connected to the ground voltage GND supply line and the virtual ground voltage VGND. The MTCMOS circuit is shown connected between the supply lines. In the MTCMOS circuit, in the normal operation mode, the second transistor is turned on to supply the ground voltage to the first transistor, but in the sleep mode, the second transistor is turned off so that the first transistor is connected to the logic circuit. The supply of the ground voltage is cut off and this standby leakage current is suppressed by the second transistor having a high threshold voltage.

The MTCMOS semiconductor integrated circuit can be configured by adding the MTCMOS circuit to the standard cell region. Here, the standard cell region is a region composed of a plurality of standard cells, and has N (N is one or more) cell rows. The standard cell is, for example, a gate or a circuit element such as AND, NAND, OR, or the like. It is designed to be registered as a library. In arranging the standard cell area by arranging such standard cells, the shape or position of the diffusion region (or ion implantation layer) in each standard cell is not always the same, but the terminal position of the input / output signal connected to the standard cell and the power supply line or ground voltage Supply lines are standardized. This standard cell area can be appropriately modified according to the purpose of the arrangement of the standard cells or the circuit configuration included in each cell for a new layout design. When the MTCMOS circuit is added to the standard cell region, the standard cell region includes an MTCMOS logic cell, a non-MTCMOS logic cell, and a switch cell. As shown in FIG. 1, when the logic circuit includes a logic circuit composed of a first transistor and the logic circuit is connected to a switch cell including a second transistor having a second threshold voltage, the logic circuit is an MTCMOS logic cell. When not connected to a transistor, it becomes a non-MTCMOS logic cell. 2 shows a general arrangement method for adding an MTCMOS circuit to a standard cell region. That is, the standard cell region including the MTCMOS circuit is arranged based on the logic cells (MTCMOS and non-MTCMOS) and the switch cells as shown in FIG. 2, but the switch cell arrays are arranged in a constant region. ) And modify the standard cell area so that the logic cells are interconnected through a rail-type virtual ground supply line arranged parallel to the cell rows within the standard cell area. At this time, the virtual ground supply line uses a metal line with a wide line width.

However, this arrangement method requires modification of all logic cells including non-MTCMOS logic cells that do not use an MTCMOS circuit, so that the change of the cell library is very cumbersome and time consuming. In addition, since the metal line having a wide line width is uniformly arranged along the cell row as the virtual ground voltage supply line, the flexibility of design change is inferior and there is a problem that unnecessary space exists in the cell area.

The present invention has been made to solve the above problems, in the MTCMOS standard cell region including a plurality of logic cells and switch cells, and having a plurality of cell rows, the switch cells are not arranged in line in the standard cell region. The terminal from the source of the first transistor in the logic cell in the logic cell connected to the switch cell by a virtual ground voltage supply line and properly distributedly disposed near the portion where the MTCMOS logic cell including the first transistor to be connected to the switch cell is present Processed by a pin (pin) is connected to the virtual ground voltage supply line, the virtual ground voltage supply line relates to a semiconductor integrated circuit, characterized in that made of a metal line having a minimum line width determined by the design standards. In this case, the fin is a portion extending from the source / drain or the gate to transmit a signal to the source / drain or the gate of the MOS transistor, and the electrical signal is connected to the pin by connecting the signal wiring at the upper level to the source / drain or the gate. Delivery is possible.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. 3 shows an MTCMOS logic cell designed in accordance with the present invention. As shown in Fig. 3, the bodies of the NMOS and PMOS are connected by a ground voltage, a power supply voltage, and a contact 8, respectively, and an input terminal 4 and an output terminal 5 of a logic circuit (that is, an inverter). And the source terminal 6 of the NMOS are connected to the signal wiring 7 as a pin (ie, a virtual ground pin). At this time, the signal wiring 7 is connected to the second transistor of the switch cell to become a virtual ground voltage supply line, and according to a design rule which is a standard of design that can be characterized by a minimum wiring width in the design of a semiconductor integrated circuit. It consists of a metal wire with a minimum line width determined. 4 shows a logic cell and a switch cell arranged in a standard cell area.

As shown in FIG. 4, it can be seen that each of the switch cells is not arranged in a line in a specific area but is dispersed and disposed as a whole. The distributed arrangement of each of these switch cells is determined according to the position of each of the MTCMOS logic cells. That is, the position of each of these switch cells is not arranged uniformly and is located as close as possible to each MTCMOS logic cell to be connected, and the second transistor in the switch cell is connected to the MTCMOS logic cell by a metal wire having the minimum wiring width described above. It is connected to the first transistor inside to perform the leakage current protection function described above. Therefore, the position of the switch cell is determined according to the position of the MTCMOS logic cell in the standard cell area.

However, when arranged in such an array structure, the following problems may occur. When the cell rows are paired, one of the cell rows shares a power rail or ground rail so that one cell flips and the other row does not flip the cell. If you design with back option), you will touch each other between cell rows. In this contacting structure, as shown in FIG. 5, four standard cells share a point P, and there is a possibility that a contact arrangement occurs. Each standard cell has an N-type or P-type ion implantation layer formed on a silicon substrate to form an NMOS or PMOS transistor. The width of the ion implantation layer is determined by a design specification, and the layout of the standard cells is determined by the design specification. Violation of should be avoided. However, in the arrangement in which four standard cells are in contact with each other and share one point, as shown in FIG. 5, the design specification regarding the minimum line width or the minimum line distance of the ion implantation layer may occur. In order to solve this problem, as shown in FIG. 6, the cell rows should be spaced at regular intervals, and the above-described problems may be solved through such a space.

Compared to the standard cell region using the conventional rail-type wide-wire virtual ground voltage supply line, the present invention provides a more flexible and faster design change of the standard cell array, thereby increasing the integration and multifunctional MTCMOS of the nano-class semiconductor device. It can be applied more efficiently to implement a semiconductor integrated circuit.

Claims (4)

A logic cell comprising a logic circuit comprising a transistor having a first threshold voltage, wherein the logic circuit is connected between a power supply voltage supply line and a virtual ground voltage supply line, wherein the logic circuit is connected between a voltage supply line and a ground voltage supply line. A non-MTCMOS logic cell connected between the virtual ground voltage supply line and the ground voltage supply line and having a second threshold voltage that is greater than the first threshold voltage and turned on in an operation of the logic circuit and turned off in an inoperative state. 12. A semiconductor integrated circuit comprising a standard cell region having a plurality of switch cells including two transistors, each of the switch cells each of the MTCMOS logic cells including the first transistor to be connected by the virtual ground voltage supply line. And distributed in proximity to the semiconductor integrated circuit. The semiconductor integrated circuit according to claim 1, wherein the terminal from the source of the first transistor included in the MTCMOS logic cell is connected to the virtual ground voltage supply line by processing a pin. The semiconductor integrated circuit of claim 2, wherein the virtual ground voltage supply line connected to the pin is formed of a metal line having a minimum line width determined by a design standard of the semiconductor integrated circuit. The semiconductor integrated circuit according to any one of claims 1 to 3, wherein the standard cell region has a plurality of cell rows, and the cell rows are spaced at regular intervals.

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