JP2012169023A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance reliability of a nonvolatile resistance change element at a low resistance.SOLUTION: A semiconductor device comprises: at least two logic circuits 15 and 16; and a resistance-change type nonvolatile element 14 capable of electrically connecting between a logic circuit 15 in the preceding stage and a logic circuit 16 in the following stage. The resistance-change type nonvolatile element has a resistance value that is electrically rewritable, and has a transition characteristic of a bipolar type in which the direction of applied voltage or current required for transition of the resistance value from a high-resistance state to a low resistance state and the direction of applied voltage or current required for the transition from a row-resistance state to a high resistance state are opposite to each other. The logic circuit in the preceding stage is configured so as to have a driving capability that causes a peak value of a signal current, which is output from the logic circuit in the preceding stage and flows through the resistance change type nonvolatile element, to be increased in the direction in which the resistance change type nonvolatile element transitions to a low-resistance state and to be decreased in the opposite direction.

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device equipped with a variable resistance nonvolatile element.

  With the miniaturization of semiconductor integrated circuits, field effect transistors (MOSFETs) have been reduced in size and power consumption, and MOSFETs have been highly integrated at a quadruple rate in three years. (Scaling law: Moore's law).

  While the cost per device of the MOSFET integrated by the miniaturization of the semiconductor integrated circuit is drastically reduced, the cost for manufacturing the semiconductor integrated circuit (semiconductor chip) is greatly increased. For example, the gate dimensions of state-of-the-art MOSFETs reach dimensions below 30 nm, and the cost of masks for patterning MOSFET patterns on semiconductor wafers is very high.

  Under such circumstances, there is an increased use of an FPGA (Field Programmable Gate Array) chip that allows a designer to electrically program a desired circuit on a manufactured semiconductor chip. The FPGA is a chip that can obtain desired electrical specifications by electrically programming a chip formed with the same mask after manufacturing. In particular, when the number of chips required is small, an FPGA is often selected in that it is not necessary to bear an expensive mask cost.

  By the way, the FPGA requires a large number of switches and memory holding circuits for reflecting the program information on the integrated circuit. In this respect, the area efficiency of current FPGAs is poor, and this tendency becomes more conspicuous as the scale of FPGAs increases.

  Until now, MOSFETs have mainly been used as wiring switching switches, and SRAM (Static Random Access Memory) and latch circuits have been used for memory retention. In this case, in order to obtain sufficient conductivity, the MOSFET switch needs to keep the element size at a certain level or more. Considering the variation in threshold voltage, it is difficult to reduce the element size as much as the effect of the scaling law in order to obtain an operation margin for the SRAM. Therefore, the area occupied by the switch and the memory circuit is increased even if the scaling is advanced.

  Therefore, a variable resistance nonvolatile element is expected as an alternative to the FPGA SRAM / wiring switch. By mounting the variable resistance nonvolatile element inside the multilayer wiring layer of the FPGA, it is possible to further reduce power consumption and area. As the variable resistance nonvolatile element, for example, ReRAM (Resistance Random Access Memory) using a transition metal oxide, NanoBridge (registered trademark of NEC) using an ionic conductor, and the like are known.

  In Patent Document 1 and Non-Patent Document 1, resistance variable nonvolatile elements using movement of metal ions and electrochemical reaction in a solid (ion conductor) in which ions can freely move by application of an electric field or the like are disclosed. It is disclosed. This variable resistance nonvolatile element is composed of an ion conductive layer, and a first electrode and a second electrode provided on an opposing surface in contact with the ion conductive layer. Metal ions are supplied from the first electrode to the ion conductive layer, and metal ions are not supplied from the second electrode. In such a resistance variable nonvolatile element, the resistance value of the ion conductor can be changed by changing the polarity of the applied voltage, and the conduction state between the two electrodes can be controlled.

  Next, the operation of the variable resistance nonvolatile element will be briefly described. When the first electrode is grounded and a negative voltage is applied to the second electrode, the metal of the first electrode becomes metal ions and dissolves in the ion conductive layer. And the metal ion in an ion conductive layer turns into a metal and precipitates in an ion conductive layer, The metal bridge | crosslinking which connects a 1st electrode and a 2nd electrode with the deposited metal is formed. The first electrode and the second electrode are electrically connected by the formed metal bridge, so that the switch is turned on. In contrast, when the first electrode is grounded and a positive voltage is applied to the second electrode in the ON state, a part of the metal bridge is cut. Thereby, the electrical connection between the first electrode and the second electrode is cut off, and the switch is turned off. In order to change from the off state to the on state, the first electrode is grounded again and a negative voltage is applied to the second electrode.

  Among such variable resistance nonvolatile elements, a bipolar type element in which applied voltages necessary to change between a low resistance state (on state) and a high resistance state (off state) are reversed is called a bipolar type. Here, in the bipolar variable resistance element, in order to bring the element into a low resistance state, an electrode that applies a higher potential than the other electrode is defined as a positive electrode, and the other electrode is defined as a negative electrode.

  FIG. 1 schematically shows the electrical characteristics and structure of a bipolar variable resistance element. In the high resistance state, when the negative electrode is grounded and a positive voltage is applied to the positive electrode, as shown in FIG. 1 (A), the resistance change element is lowered from the high resistance state with a certain voltage value as a threshold value (referred to as a set voltage). The voltage current characteristic which changes to a resistance state is shown. In the low resistance state, as shown in FIG. 1B, a metal bridge 104 is formed in the ion conductive layer 102 between the positive electrode 101 and the negative electrode 103 by the metal deposited from the positive electrode 101. On the other hand, when the negative electrode 103 is grounded and a negative voltage is applied to the positive electrode 101 in the low resistance state, a transition is made from the low resistance state to the high resistance state at a certain current value (reset current) as shown in FIG. Voltage / current characteristics are shown. In the high resistance state, as shown in FIG. 1D, the metal bridge 104 is absorbed by the positive electrode 101 due to mass transfer and disappears.

  When such a bipolar variable resistance element is used as a connection switch between logic circuits, the variable resistance nonvolatile element affects the change in resistance state due to a voltage current sufficiently smaller than the set voltage and reset current of the variable resistance element. Without giving, it is possible to propagate the signal of the logic circuit.

JP 2005-101535 A

Shunichi Kaeriyama et al. "A Nonvolatile Programmable Solid-Electronic Nanometer Switch", IEEE Journal of Solid-State Circuits, Vol. 40, no. 1, pp. 168-176, January 2005.

  The following analysis is given in the present invention.

  The bipolar two-terminal variable resistance element described in Patent Document 1 and Non-Patent Document 1 reversibly transitions between a low resistance state and a high resistance state by an external voltage / current. When assembled, it has polarity. In normal operation after writing, a desired logic circuit is connected by a resistance change element in a low resistance state, and a signal is propagated. Therefore, the next stage logic circuit is driven in the resistance change element in a low resistance state. The pulse current flows. The direction in which this pulse current flows through the variable resistance element differs depending on the type of logic circuit to be connected. For example, even when a logic circuit is created by a CMOS circuit in which a direct current does not substantially flow through the resistance change element, a charge / discharge pulse current for charging / discharging the logic circuit at the next stage flows through the resistance change element. .

  By the way, in Non-Patent Document 1, in a bipolar variable resistance nonvolatile element, a direct current in the same direction as the write direction to the low resistance state does not cause stress that deteriorates the retention of the low resistance state, but the reverse direct current Has been shown to be a stress that degrades retention. In other words, the current in the same direction as the reset current may become a stress factor for reliability that causes the resistance change element to change from the low resistance state to the high resistance state within a certain finite time even at a current value lower than the reset current. It is done. Therefore, the current during normal operation needs to be set so that such unintended changes do not occur.

  When a resistance change element is used as a connection switch for a logic circuit, the operation current during normal operation is designed so that no problem occurs in maintaining a low resistance state within a practical time range (for example, 10 years). Is to be done. In this case, if an attempt is made to improve the holding characteristic against stress, there is a design restriction that the reset current must be increased accordingly.

  An object of the present invention is to solve the above-described problems and provide a semiconductor device including a variable resistance nonvolatile element that can be highly reliable.

  First, how the saturation current ratio of nFET and pFET is designed between the conventional CMOS logic circuit and the CMOS logic circuit to which the variable resistance nonvolatile element according to the present invention is connected will be described.

In a normal CMOS logic circuit, the ratio of saturation current of nFET and pFET is generally set to 1 from the viewpoint of delay time and element occupation area. For example, the delay time τ of the CMOS logic inverter is expressed by the following equation (1), assuming that it is the sum of the pulse rising delay time τr and the falling delay time τf.
τ = τr + τf∝ (βn + βp) / (βn · βp) ――― Formula (1)
Here, βn and βp are gain coefficients in nFET and pFET, respectively.

The relationship between the gain coefficient β and the saturation current Idsat is expressed as follows using the power supply voltage Vdd and the threshold voltage Vth of the transistor.
Idsatn = 1/2 · βn · (Vdd−Vthn) ² ——Expression (2)

Further, the gain coefficient β is expressed as follows using the mobility μ, the gate oxide film thickness Cox, the gate length L, and the gate width W.
βn = μn · Cox · Wn / Ln ――― Formula (3)

  The above equations dealt with nFETs, but the same applies to pFETs.

  As can be seen from Equation (3), the gate oxide film thickness Cox, the mobility μ, the gate length L, and the gate overdrive voltage (Vdd−Vth) are parameters specific to the process, and the parameters that can be freely designed are substantially The gate width W.

Here, when Equation (1) is rewritten with respect to the gate width W, it becomes as follows.
τ∝ (A · Wn + Wp) / (A · Wn · Wp) ――― Formula (4)
However, A = μn / μp ――― Formula (5)

As can be seen from the equation (4), the delay time τ can be shortened as the gate width W is increased. In this case, when the condition that the sum of Wn and Wp is constant, it is found that the minimum is obtained when Wp = A · Wn. Here, since the ratio A of the mobility μ of the nFET to the pFET is about 1 <A <2, when the gate width is designed as expressed by the equation (6), the efficiency of the delay time with respect to the gate width is the highest. Become.
Wn <Wp <2Wn ――― Formula (6)

  Therefore, in a normal CMOS logic circuit, the relationship between the gate width of nFET and pFET is designed so that the pFET is larger than the nFET so as to satisfy Equation (6), and is designed to satisfy Idsatn≈Idsatp. The

  FIG. 2 shows a basic circuit diagram of a variable resistance nonvolatile element (hereinafter simply referred to as a variable resistance element) connected to an inverter logic circuit. For simplicity, all circuits are not shown. In FIG. 2, the resistance change element 201 is connected to the previous stage inverter 202 and the next stage inverter 203, and is further connected to the write transistor group 204 of the resistance change element 201. Further, the positive electrode 205 is represented by a black bar in the variable resistance element 201 in order to represent bipolar characteristics. In this example, the positive electrode is connected to the inverter 203 at the next stage.

  In FIG. 2, it is assumed that the resistance change element 201 is in a low resistance state by the writing transistor group 204. When a logic signal is transmitted to the next stage inverter 203 via the previous stage inverter 202, the gate capacity Cgate of the next stage inverter 203 and the stray capacity Cstray from the variable resistance element 201 to the next stage inverter are charged and discharged. Current flows through the resistance change element 201.

This will be described in more detail with reference to FIG. When the previous stage inverter 202 outputs a signal from Low level to High level, the nFET 207 constituting the previous stage inverter 202 is cut off, the pFET 206 is saturated, and Cgate and Cstray are charged through the resistance change element 201. . At this time, a stress current I ₊ flows through the resistance change element 201 from the negative electrode to the positive electrode. Conversely, when the inverter 202 at the previous stage outputs a low level, the pFET 206 is cut off and the nFET 207 is saturated, so that Cgate and Cstra are discharged through the nFET 207. At this time, a non-stress current I ₋ flows from the positive electrode to the negative electrode.

The pulse waveform of the current (I ₊ , I ₋ ) flowing through the variable resistance element in the above operation is as shown in FIG. Here, in order to improve the reliability of the nonvolatile variable resistance element at the time of low resistance, it is preferable that the stress current I ₊ is suppressed as indicated by a broken line.

Next, in order to discuss the reliability of the resistance change element in the low resistance state, the average failure time (MTF) of the wiring is considered using the black relational expression (Black's law) shown in Expression (7). .
MTF = A · (1 / Jn) · exp (Ea / kT) ――― Formula (7)
Here, A is a proportional constant, J is a current density, n is a real number greater than 1, Ea is an activation energy, k is a Boltzmann constant, and T is a temperature.

なお、Ｔｃｙｃｌｅは信号周期である。 In the case of a pulse current, J is expressed as shown in Equation (8) using the charge / discharge current I (t).

Tcycle is a signal period.

Here, if it is considered that the non-stress current I ₋ does not affect the MTF, it is considered that the MFT of the bipolar variable resistance element is expressed by Equation (9).

  The important point here is that Cgate + Cstray is constant, so if n = 1, the MTF is constant for any βp. However, in practice, the current value has an effect that is more than linear with respect to the MTF and n> 1, and the smaller the βp, the better the MTF improves with a downward convex function.

  On the other hand, from the viewpoint of signal delay time, if βn and βp are simultaneously reduced, the delay time of the logic circuit increases unacceptably.

  The inventors of the present application have studied improvement measures for these, and clarified that it is desirable to design the delay time of the logic circuit with βn that has little influence on MTF and to make βp smaller than βn. Further, it has been clarified that in order to minimize the delay time, it is desirable that the logic threshold value of the logic circuit in the next stage is approximately the same as the logic threshold value of the logic circuit in the preceding stage.

  A semiconductor device according to one aspect (side surface) of the present invention includes at least two logic circuits, and a variable resistance nonvolatile element that can electrically connect a preceding logic circuit and a succeeding logic circuit. The resistance variable nonvolatile element has an electrically rewritable resistance value, the direction of applied voltage or current necessary for the resistance value to transition from the high resistance state to the low resistance state, and the low resistance state to the high resistance state. Bipolar type transition characteristics such that the direction of applied voltage or current necessary for transition to the state is opposite, and the logic circuit in the previous stage is output from the logic circuit in the previous stage and is a variable resistance nonvolatile element Is configured to have such a driving capability that the peak value of the signal current flowing through the capacitor changes greatly in the direction in which the variable resistance nonvolatile element transitions to the low resistance state and decreases in the opposite direction.

  ADVANTAGE OF THE INVENTION According to this invention, the reliability at the time of the low resistance of a non-volatile resistance change element can be improved.

It is a figure which shows typically the electrical property and structure of a bipolar variable resistance element. It is a basic circuit diagram of a variable resistance nonvolatile element connected to an inverter logic circuit. It is a figure explaining the signal current pulse which flows through a resistance change element. It is a figure which shows the amplitude and time change of the signal current pulse which flow through a resistance change element. 1 is a circuit diagram of a semiconductor device according to a first embodiment of the present invention. 1 is a circuit diagram of an input driver according to a first exemplary embodiment of the present invention. 1 is a circuit diagram of an output driver according to a first exemplary embodiment of the present invention. It is a figure explaining the transition operation to the low resistance state of the crossbar switch using the resistance change element concerning the 1st example of the present invention. FIG. 3 is a circuit diagram in which the logic circuit in the previous stage and the logic circuit in the next stage are connected by the resistance change element in the low resistance state of the crossbar switch using the resistance change element according to the first example of the present invention. 1 is a diagram schematically showing a layout of transistors in a semiconductor device according to a first example of the present invention. It is a figure which shows typically the layout of the transistor in the semiconductor device which concerns on the 2nd Example of this invention. It is a figure which shows typically the layout of the transistor in the semiconductor device which concerns on the 3rd Example of this invention. It is a figure which shows typically the other layout of the transistor in the semiconductor device which concerns on the 3rd Example of this invention. It is sectional drawing which shows typically the variable resistance nonvolatile element which concerns on each Example of this invention.

  Hereinafter, an embodiment for carrying out the present invention will be outlined. Note that the reference numerals of the drawings attached to the following outline are only examples for facilitating understanding, and are not intended to be limited to the illustrated embodiments.

  A semiconductor device according to an embodiment of the present invention includes at least two logic circuits (corresponding to 15 and 16 in FIG. 5) and resistors that can electrically connect the preceding logic circuit and the succeeding logic circuit. A variable resistance nonvolatile element (14 in FIG. 5), the resistance variable nonvolatile element has an electrically rewritable resistance value, and an application necessary for the resistance value to transition from the high resistance state to the low resistance state. It has a bipolar transition characteristic in which the direction of the voltage or current and the direction of the applied voltage or current necessary for transition from the low resistance state to the high resistance state are opposite to each other. 15) in FIG. 5 shows that the peak value of the signal current output from the preceding logic circuit and flowing through the variable resistance nonvolatile element is greatly reduced in the direction in which the variable resistance nonvolatile element transitions to the low resistance state. Have the driving ability Configured.

  In the semiconductor device, the logic circuit in the previous stage has p-type and n-type transistors (31, 32 or 33, 34 in FIG. 6) each having saturation current characteristics satisfying the driving capability as the current supply terminals of the variable resistance nonvolatile elements. You may make it respond | correspond.

  In the semiconductor device, the saturation current characteristic may be determined by the ratio of the gate lengths or the gate widths of the respective p-type and n-type transistors.

  In the semiconductor device, the ratio of the saturation current to the respective p-type and n-type transistors may be more than 1 and not more than a predetermined value of 2 or more.

  In the semiconductor device, the ratio of the saturation current to the respective p-type and n-type transistors may be 2.

  In the semiconductor device, the ratio of the lengths in the gate width direction of the N-type and P-type well regions constituting the p-type and n-type transistors may be configured to satisfy the saturation current ratio.

  In the semiconductor device, the p-type and n-type transistors provided corresponding to the current supply terminals of the variable resistance nonvolatile element may constitute a buffer circuit (30 in FIG. 6) in the preceding logic circuit.

  In the semiconductor device, the p-type and n-type transistors provided corresponding to the current supply terminals of the variable resistance nonvolatile element are inserted between the buffer circuit in the preceding logic circuit and the current supply terminal of the variable resistance nonvolatile element. The transfer gate (29 in FIG. 6) may be configured.

  In the semiconductor device, the logic circuit in the subsequent stage is configured so that the logic threshold value corresponding to the connection end of the variable resistance nonvolatile element in the logic circuit in the subsequent stage is the same as the logic threshold value in the driving terminal of the logic circuit in the previous stage. May be.

  In a semiconductor device, a plurality of variable resistance nonvolatile elements are provided in a matrix form as a crossbar switch, and the logic circuit in the previous stage and the logic in the subsequent stage are respectively associated with connection lines to the variable resistance nonvolatile elements in the row direction and the column direction of the matrix. Each of the circuits may be provided, and a desired reconfigurable logic circuit may be configured by setting a plurality of variable resistance nonvolatile elements to a high resistance state or a low resistance state, respectively.

  A semiconductor device according to another embodiment of the present invention includes a variable resistance nonvolatile element in a reconfigurable logic circuit including a plurality of logic circuits and a plurality of variable resistance nonvolatile elements that electrically connect the logic circuits. The resistance value is electrically rewritable, and the direction of the externally applied voltage or current necessary for the resistance value to transition from the high resistance state to the low resistance state and the transition from the low resistance state to the high resistance state It has a bipolar (bipolar) transition characteristic in which the direction of the required externally applied voltage or current is reversed, and the peak value of the signal current output from the logic circuit and flowing through the variable resistance nonvolatile element is The variable resistance nonvolatile element is designed so as to have a relationship that greatly decreases in the direction of transition to the low resistance state and decreases in the reverse direction.

  In the semiconductor device, the logic circuit is preferably composed of complementary field effect transistors, and the saturation currents of the p-type transistor and the n-type transistor are designed so that the peak value of the signal current satisfies the relationship.

  In the semiconductor device, the saturation current relationship is preferably satisfied by the ratio of the gate length or the gate width of the complementary electric field transistors.

  In the semiconductor device, the saturation current ratio of the logic circuit portion connected to the variable resistance nonvolatile element is specifically large and 2 or more, and the saturation current ratio of the logic circuit portion not connected to the nonvolatile resistance change element is It is preferably smaller than this and close to 1 on average.

  In addition, the semiconductor device is provided with another logic circuit so that the height ratio of the P-type well region and the N-type well region constituting the logic circuit unit connected to the variable resistance nonvolatile element satisfies the saturation current ratio. The part is preferably designed differently from the part.

  Further, it is preferable that the logic threshold value of the logic circuit to which a signal is input from the preceding logic circuit via the semiconductor device and the nonvolatile variable resistance element is designed to be about the same as that of the preceding logic circuit.

  Hereinafter, embodiments of a semiconductor device of the present invention will be described in detail with reference to the drawings. In addition, the structure of each part in the Example disclosed here exemplifies only a main part, and an actual semiconductor device includes various parts not explicitly shown in this example. Moreover, the material and shape which comprise each part in the Example disclosed here can be variously changed in the range which does not change the main point of this invention.

  FIG. 5 is a circuit diagram of the semiconductor device according to the first embodiment of the present invention. In FIG. 5, the semiconductor device includes a crossbar switch unit 11, a plurality of input drivers 15, and a plurality of output drivers 16. The crossbar switch unit 11 includes resistance change elements 14 in a matrix (array), and commonly connects the negative electrodes of the resistance change elements 14 arranged in the horizontal direction to the input driver 15 through the input line 12. Further, the positive electrodes of the variable resistance elements 14 arranged in the vertical direction are commonly connected to the output driver 16 via the output line 13. In the semiconductor device having such a configuration, the plurality of input lines 12 and the plurality of output lines 13 can be arbitrarily connected by setting the resistance change element 14 in the crossbar switch unit 11 to a high resistance state or a low resistance state. A crossbar switch can be formed to form a reconfigurable logic circuit.

  FIG. 6 is a circuit diagram of the input driver. The input driver 15 includes a signal input line 17, an output buffer circuit 30 for transmitting a logic signal of the preceding logic circuit, a write decoder signal input 24 for writing the resistance change element 14 in a desired state, and an output buffer at the time of writing A pass transistor (transfer gate) 29 for separating the circuit 30; a voltage output driver 26 for resetting the resistance change element; a ground voltage output driver 27 for setting the resistance change element; and for preventing write interference of the non-selected resistance change element at the time of writing. Hold voltage output driver 28 and the input line 12 which is a signal output line to the crossbar switch unit 11.

  The output buffer circuit 30 includes a pFET 31 and an nFET 32 constituting a CMOS inverter circuit, inverts and amplifies the signal on the signal input line 17 and outputs the amplified signal to the pass transistor 29. The pass transistor 29 includes a pFET 33 and an nFET 34 whose sources and drains are connected in common, and an inverted signal of the signal of the gate of the nFET 34 is given to the gate of the pFET 33 via the inverter 35. The pass transistor 29 controls whether or not to transmit the output signal of the output buffer circuit 30 to the input line 12 by the signal 24a. The reset voltage output driver 26 controls whether or not to apply the voltage Vreset to the input line 12 by the signal 24b. The setting ground voltage output driver 27 controls whether or not the ground potential Gnd is applied to the input line 12 by the signal 24c. The hold voltage output driver 28 controls whether or not the hold voltage Vhold is applied to the input line 12 by the signal 24d.

  FIG. 7 is a circuit diagram of the output driver. The output driver 16 writes the output line 13, which is a signal input line from the crossbar switch unit, the input buffer circuit 40 for transmitting the logic signal of the logic circuit in the next stage, the signal output line 18, and the resistance change element in a desired state. For this purpose, a write decoder signal input 44, a resistance change element setting voltage output driver 46, a resistance change element reset ground voltage output driver 47, and a hold voltage output for preventing write interference of a non-selected resistance change element at the time of writing. At least a driver 48 is included.

  The input buffer circuit 40 includes a pFET 41 and an nFET 42 that constitute a CMOS inverter circuit, and inverts and amplifies the signal on the output line 13 and outputs the amplified signal to the signal output line 18. The setting voltage output driver 46 controls whether or not to apply the voltage Vset to the output line 13 by the signal 44b. The reset ground voltage output driver 47 controls whether or not the ground potential Gnd is applied to the output line 13 by the signal 44c. The hold voltage output driver 48 controls whether or not to apply the hold voltage Vhold to the output line 13 by the signal 44d.

  Next, operations of the input driver 15 and the output driver 16 when writing the selected variable resistance element to the low resistance state will be described. In FIG. 8, the resistance change element 14a shown in the center is written in a low resistance state. In this case, the setting ground voltage output driver 27 in the input driver 15 connected to the selected resistance change element 14a is turned on, and the setting voltage output driver 46 in the output driver 16 connected to the resistance change element 14a is turned on. Turn on. As a result, the set voltage Vset is applied to the positive electrode of the resistance change element 14a, the ground voltage (Gnd) is applied to the negative electrode, and the resistance change element 14a transitions to the low resistance state.

  For the input driver 15 and the output driver 16 corresponding to the other variable resistance elements not selected, the hold voltage output driver 28 in the input driver 15 is turned on, and the hold voltage output driver 48 in the output driver 16 is turned on. As a result, the hold voltage Vhold is applied to the positive and negative electrodes of the other variable resistance elements that are not selected in order to prevent erroneous writing. In this case, the most appropriate hold voltage Vhold is ½ Vset. By applying the hold voltage Vhold in this way, only the selected variable resistance element 14a can be shifted to the low resistance state without causing write interference. Conversely, when Vreset is applied to the negative electrode of the variable resistance element to be selected and the ground voltage (Gnd) is applied to the positive electrode, the variable resistance element can be shifted to the high resistance state.

  In FIG. 5, the negative electrode of the variable resistance element is connected to the input driver 15 and the positive electrode is connected to the output driver 16. However, in the case of the reverse connection relationship, the set voltage and reset voltage of the input driver and output driver respectively. Each output driver will be placed in the opposite driver.

  FIG. 9 shows a circuit diagram in which the previous stage logic circuit and the next stage logic circuit are connected via the variable resistance element 14a in the low resistance state. In order to suppress the peak value of the stress current pulse flowing through the resistance change element 14a in the low resistance state, the gain coefficient βp of the pFET 31 of the output buffer circuit 30 is made smaller than the gain coefficient βn of the nFET 32 (βn / βp > 1) Design each gate width. In order to prevent an increase in the delay time, it is desirable to design the ratio of the gain coefficient of the pFET 41 and the gain coefficient of the nFET 42 of the input buffer circuit 40 of the next stage logic circuit to the same level as that of the previous stage logic circuit. By doing so, the logical threshold values of the output buffer circuit 30 and the input buffer circuit 40 become equal, and an increase in delay time due to a reduction in the gain coefficient of the pFET can be suppressed.

  In the above case, the preferred gain coefficient ratio βn / βp is more than 1 and not more than a predetermined value of 2 or more. Here, if the gain coefficient ratio βn / βp is too large, the logic amplitude does not fully swing, and malfunction is likely to occur due to the influence of noise or the like. According to the study by the inventors of the present application, it is found by simulation using a commonly used process that a remarkable malfunction occurs when βn / βp exceeds 10, and the predetermined value is preferably about 10. The result is obtained.

  Next, the layout of the transistors in the output buffer circuit 30 and the input buffer circuit 40 will be described. FIG. 10 is a diagram schematically showing a layout of transistors in the semiconductor device according to the first example of the present invention. In FIG. 10, 52 is an n-type well formed on the semiconductor substrate, 53 is a p-type well formed on the semiconductor substrate, 54 is a p-type diffusion layer formed on the n-type well 52, and 55 is a p-type. An n-type diffusion layer formed on the well 53, a common electrode 56 on the p-type diffusion layer 54 and the n-type diffusion layer 55 are gate electrodes. In addition, the well contact, gate, source, and drain region wirings necessary for the transistor have well-known contents and are not shown for the sake of simplicity.

  According to the transistor layout as shown in FIG. 10, the p-type diffusion layer 54 and the gate electrode 56 constitute a pFET. The n-type diffusion layer 55 and the gate electrode 56 constitute an nFET. In this case, in order to adjust the ratio of the gain coefficient of the pFET and the nFET, the height of the diffusion layer of each of the pFET and the nFET, that is, the gate width Wp, Wn is changed from the normal layout, thereby the gain of the nFET and the pFET. An inverter having a coefficient ratio βn / βp exceeding 1 and not more than a predetermined value of 2 or more can be configured.

  FIG. 11 is a diagram schematically showing a layout of transistors in the semiconductor device according to the second example of the present invention. In FIG. 11, 52a is an n-type well formed on the semiconductor substrate, 53a is a p-type well formed on the semiconductor substrate, 54a is a p-type diffusion layer formed on the n-type well 52a, and 55a is a p-type. An n-type diffusion layer formed on the well 53a, 56a commonly disposed on the p-type diffusion layer 54a and the n-type diffusion layer 55a is a gate electrode. In addition, illustration of the wiring of the well contact, gate, source, and drain regions necessary for the transistor is omitted. The p-type diffusion layer 54a and the gate electrode 55a constitute a pFET. The n-type diffusion layer 55a and the gate electrode 55a constitute an nFET.

  Here, the heights of the diffusion layers of the pFET and the nFET, that is, the gate widths Wp and Wn are the same as the gate widths of other logic circuits (ordinary CMOS logic circuits) that are not related to the connection of the resistance change elements. .

  According to the layout of FIG. 11, the nFET has substantially two gates, and the pFET has one gate. Therefore, the gate width of the nFET is 2 · Wn, and the gate width of the pFET can be regarded as Wp. Thus, by laying out the transistors so that the number of gates differs between the pFET and the nFET, the gate width can be adjusted and the gain coefficient ratio βn / βp can be designed to a desired value.

  The configuration of the transistor formed here is equivalent to a configuration in which two nFETs are connected in parallel to one pFET. Therefore, if the layout shown in FIG. 11 is based on a normal process, βn / βp = 2 can be obtained by using the same layout structure as that of other logic circuits in the semiconductor device. That is, based on the layout of a normal semiconductor device, the ratio of the gain coefficient to pFET and nFET can be set to 2, which is preferable in terms of layout design.

  Furthermore, if the configuration is such that k nFETs (k = 3 to 9) are connected in parallel to one pFET, the gain coefficient ratio βn / βp to pFET and nFET can be set to k. Needless to say, there is.

  In this embodiment, the ratio of the gain coefficient of the pFET 33 and the nFET 34 in the pass transistor (transfer gate) 29 in the input driver 15 of FIG. 6 (FIG. 9) is set instead of the ratio of the gain coefficient of the logic circuit in the previous stage. Controls the peak value of the pulse current. Others are the same as those in the first embodiment, and the description thereof is omitted.

  In the example of FIG. 5, the stress-related pulse current flows when the output of the input driver 15 changes from the Low level to the High level, and the input line 12 of the crossbar switch changes from the Gnd level to the High level. Since the peak of the pulse current appears immediately after the transition from the low level to the high level is started, the potential of the input line 12 is close to the low level, and considering the bias condition among the pFET 33 and the nFET 34 of the pass transistor 29 in FIG. , Mainly through the nFET 34. Therefore, the current gain coefficient of the nFET 34 is configured to be smaller than that of the pFET 33 so as to suppress the peak value of the stress current pulse in the pass transistor 29.

  With this configuration, it is possible to selectively suppress only the stress current peak value without suppressing the non-stress current peak value. Moreover, an increase in the delay time can be prevented by not suppressing the non-stress current peak. At this time, it is desirable that the gain coefficient ratio βn / βp of the pFET 41 and the nFET 42 of the input buffer circuit 40 in FIG. 7 is designed to be 1 as in a normal logic circuit.

  FIG. 12 is a diagram schematically showing the layout of the transistors in the semiconductor device according to the third example of the present invention. In FIG. 12, 52b is an n-type well formed on the semiconductor substrate, 53b is a p-type well formed on the semiconductor substrate, 54b is a p-type diffusion layer formed on the n-type well 52b, and 55b is a p-type. An n-type diffusion layer formed on the well 53b, a 56b disposed on the p-type diffusion layer 54b, and a gate electrode 56c disposed on the n-type diffusion layer 55b. In addition, the well contact, gate, source, and drain region wirings necessary for the transistor have well-known contents and are not shown for the sake of simplicity. The p-type diffusion layer 54b and the gate electrode 56b constitute a pFET. The n-type diffusion layer 55b and the gate electrode 56c constitute an nFET.

  According to the transistor layout as shown in FIG. 12, by changing the height of the diffusion layers of the pFET and the nFET, that is, the gate widths Wp and Wn from the normal layout, the ratio βp of the gain coefficient of the pFET and the nFET. / Βn can constitute a pass transistor (transfer gate) 29 that is greater than 1 and less than or equal to 2 and less than a predetermined value. According to the pass transistor 29 including the transistor having such a configuration, the peak value of the stress current pulse can be suppressed.

  FIG. 13 is a diagram schematically showing another layout of transistors in the semiconductor device according to the third example of the present invention. In FIG. 13, 52a is an n-type well formed on the semiconductor substrate, 53a is a p-type well formed on the semiconductor substrate, 54a is a p-type diffusion layer formed on the n-type well 52a, and 55a is a p-type. An n-type diffusion layer formed on the well 53a, a 56d disposed on the p-type diffusion layer 54a, and a gate electrode 56e disposed on the n-type diffusion layer 55a. In addition, illustration of the wiring of the well contact, gate, source, and drain regions necessary for the transistor is omitted. The p-type diffusion layer 54a and the gate electrode 56d constitute a pFET. The n-type diffusion layer 55a and the gate electrode 56e constitute an nFET.

  Here, the heights of the diffusion layers of the pFET and the nFET, that is, the gate widths Wp and Wn are the same as the gate widths of other logic circuits (ordinary CMOS logic circuits) that are not related to the connection of the resistance change elements. .

  The transistor layout as shown in FIG. 13 is equivalent to a configuration in which two pFETs are connected in parallel to one nFET, and the gain coefficient ratio βp / βn of the pFET and nFET is 2. A pass transistor (transfer gate) 29 can be formed.

  In the description so far, the case where the positive electrode of the resistance change element is connected to the input terminal of the inverter of the next stage has been described. However, in the case where the variable polarity element is arranged with the reverse polarity, 3 flows in the opposite direction. Therefore, the relationship between the sizes of the pFET and the nFET may be set in reverse. That is, when the positive electrode of the variable resistance element is connected to the output terminal of the inverter at the previous stage, in the case of the first and second embodiments, the peak of the stress current pulse that flows through the variable resistance element 14 in the low resistance state. In order to suppress the value, the layout is designed such that each gate width is designed so that the gain coefficient βn of the nFET 32 of the output buffer circuit 30 is smaller than the gain coefficient βp of the pFET 31.

  On the other hand, in the case of the third embodiment, when the peak value of the stress current pulse is suppressed by the pass transistor 29, the layout is designed so that the current gain coefficient of the pFET 33 is smaller than that of the nFET 34.

  The case where the CMOS logic circuit is an inverter circuit has been described above. However, the present invention is not limited to this, and other known circuits such as NAND circuits and NOR circuits can be similarly designed.

  In addition to static CMOS circuits, the concept of charge / discharge is the same for dynamic logic circuits such as so-called domino circuits.

  Furthermore, the reliability of the nMOS circuit, the pMOS circuit, and the bipolar transistor can be improved by designing so that the peak value of the current decreases in the stress current direction.

  Next, the structure of the variable resistance nonvolatile element in each example will be described. FIG. 14 is a cross-sectional view schematically showing a variable resistance nonvolatile element. The semiconductor device of FIG. 14 is configured such that the variable resistance element described in the first embodiment is provided in a multilayer wiring layer provided on a semiconductor substrate. The resistance change element is formed by disposing the negative electrode 68 and the positive electrode 70 to face each other with the ion conductive layer 69 interposed therebetween. The area of the variable resistance element is defined by the opening to the negative electrode of the insulating barrier film 64. The negative electrode 68 also serves as a lower layer wiring, and a plug 71 for electrically connecting the upper layer wiring 72 and the positive electrode 70 is formed. Further, an interlayer insulating film 61, an insulating barrier film 62, an interlayer insulating film 63, an insulating barrier film 64, an interlayer insulating film 65, an insulating barrier film 66, and an interlayer insulating film 67 for electrically insulating the wiring layer are provided. Each layer is formed in order.

  For the ion conductive layer 69, a material containing any of organic substances, organic siloxane, silicon carbide oxide, silicon tantalum oxide, tantalum oxide, zirconium oxide, hafnium oxide, silicon oxide, and titanium oxide can be used. The negative electrode 68 can be made of a material containing Cu as a main component, and the positive electrode 70 can be made of a material containing Ru or Pt. Here, as Cu used for the negative electrode 68, Cu used for wiring of the semiconductor integrated circuit element can be used as it is. In this case, the ion conductive layer 69 is formed in contact with Cu of the wiring layer, and the process steps can be simplified. At this time, the Cu content is 95% or more. Generally, when the Cu content is less than this, the wiring resistance increases. The variable resistance element formed in the wiring layer in this manner and the CMOS circuit formed on the silicon substrate by a known method on the lower side of the element are connected by a multilayer wiring, so that the function as a reconfigurable logic circuit is achieved. Can be provided.

  Although the present invention has been described with reference to the above embodiments, the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be added to the configuration and details of the present invention, and the order of the steps disclosed within the scope of the present invention may be changed. Further, the present invention includes a combination of some or all of the configurations of the above-described embodiments as appropriate.

11: Crossbar switch unit 12: Input line 13: Output line 14, 14a: Resistance change element 15: Input driver 16: Output driver 17: Signal input line 18: Signal output line 24, 44: Decoder signal input for writing 26: Reset Voltage output driver 27: Set ground voltage output driver 28, 48: Hold voltage output driver 29: Pass transistor (transfer gate)
30: Output buffer circuits 31, 33, 41: pFET
32, 34, 42: nFET
35: Inverter 40: Input buffer circuit 46: Set voltage output driver 47: Reset ground voltage output driver 52, 52a, 52b: n-type wells 53, 53a, 53b: p-type wells 54, 54a, 54b: p-type diffusion Layers 55, 55a, 55b: n-type diffusion layers 56, 56a, 56b, 56c, 56d, 56e: gate electrodes 61, 63, 65, 67: interlayer insulating films 62, 64, 66: insulating barrier film 68: negative electrode ( Lower layer wiring)
69: Ion conduction layer 70: Positive electrode 71: Plug 72: Upper layer wiring 101: Positive electrode 102: Ion conduction layer 103: Negative electrode 104: Metal bridge 201: Resistance change element 202, 203: Inverter 204: Write transistor group 205: Positive electrode 206 : PFET
207: nFET

Claims (10)

Comprising at least two logic circuits, and a variable resistance nonvolatile element that enables electrical connection between the preceding logic circuit and the following logic circuit,
In the variable resistance nonvolatile element, the resistance value is electrically rewritable, the direction of the applied voltage or current necessary for the resistance value to transition from the high resistance state to the low resistance state, and the low resistance state to the high resistance state. It has a bipolar transition characteristic such that the direction of the applied voltage or current necessary for transitioning to the resistance state has an inverse relationship,
In the preceding logic circuit, the peak value of the signal current output from the preceding logic circuit and flowing through the variable resistance nonvolatile element is greatly reversed in the direction in which the variable resistance nonvolatile element transitions to a low resistance state. A semiconductor device characterized in that it has a driving capability that is small.   2. The preceding stage logic circuit includes p-type and n-type transistors each having a saturation current characteristic that satisfies the drive capability, corresponding to a current supply terminal of the variable resistance nonvolatile element. The semiconductor device described.   3. The semiconductor device according to claim 2, wherein the saturation current characteristic is determined by a ratio of a gate length or a ratio of a gate width of each of the p-type and n-type transistors.   4. The semiconductor device according to claim 2, wherein a ratio of a saturation current to each of the p-type and n-type transistors is more than 1 and not more than a predetermined value of 2 or more.   The semiconductor device according to claim 4, wherein a ratio of a saturation current to each of the p-type and n-type transistors is two.   5. The length ratio in the gate width direction of the N-type and P-type well regions constituting the p-type and n-type transistors, respectively, is configured to satisfy the saturation current ratio. Or the semiconductor device according to 5;   7. The p-type and n-type transistors provided corresponding to the current supply terminals of the variable resistance nonvolatile element constitute a buffer circuit in the preceding logic circuit. A semiconductor device according to 1.   The p-type and n-type transistors provided corresponding to the current supply terminal of the variable resistance nonvolatile element are inserted between the buffer circuit in the preceding logic circuit and the current supply terminal of the variable resistance nonvolatile element. 7. The semiconductor device according to claim 2, wherein a transfer gate is configured.   The latter logic circuit is configured such that a logic threshold value corresponding to a connection end of the variable resistance nonvolatile element in the latter logic circuit is the same as a logic threshold value of a driving end of the preceding logic circuit. 9. The semiconductor device according to claim 1, wherein the semiconductor device is characterized in that: A plurality of the variable resistance nonvolatile elements are provided as a crossbar switch in a matrix,
The logic circuit in the previous stage and the logic circuit in the subsequent stage are respectively provided corresponding to connection lines with the variable resistance nonvolatile elements in the row direction and the column direction of the matrix,
The desired reconfigurable logic circuit is configured by setting the plurality of variable resistance nonvolatile elements to a high resistance state or a low resistance state, respectively. Semiconductor device.

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