JP2010147133A - Nonvolatile storage - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile storage having high reliability enabling high integration by substituting the nonvolatile storage for a SRAM used in a switch of a programmable logic such as a FPGA or the like. <P>SOLUTION: The nonvolatile storage includes a first input electrode 101, an output electrode 104, and a second input electrode 107. Further, the nonvolatile storage includes a first variable resistance layer 120 interposed between the first input electrode 101 and the output electrode 104, and a second variable resistance layer 130 interposed between the output electrode 104 and the second input electrode 107. The first variable resistance layer 120 includes a first metal oxide layer 102 and a second metal oxide layer 103, and the second variable resistance layer 130 includes a third metal oxide layer 105 and a fourth metal oxide layer 106. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a nonvolatile memory device including a resistance change layer made of a metal oxide.

  In recent years, development competition for electronic devices has intensified, and electronic devices have been downsized. Under such circumstances, programmable logic that can provide many functions with one chip by changing the circuit configuration by electronic signals even after manufacturing has been attracting attention. Typical examples of programmable logic include a field-programmable gate array (FPGA) and a dynamically reconfigurable processor (DRP). Programmable logic has a wide variety of applications from home appliances to communication equipment, recently aircraft and satellite devices.

  In many programmable logics, as well known as a switch device, a combination of a pass transistor and an SRAM (Static Random Access Memory) that outputs a control voltage to the gate of the pass transistor is shown in FIG. A circuit is used. In this circuit, program information is written to the SRAM 1201 when power is turned on. When the output voltage V1 from the SRAM 1201 is at a high level, the pass transistor 1202 is turned on and the terminals P1 and P2 are connected. However, since the SRAM 1201 loses stored information when the power is turned off, the SRAM 1201 needs to be programmed again after the power is turned on.

  On the other hand, some FPGAs use flash memory or fuses instead of SRAM. In this case, since the stored information is maintained even when the power is turned off, it is not necessary to perform the program again after the power is turned on. However, when a high-density logic circuit and a flash memory are mixedly mounted in an FPGA that requires a large capacity and high-speed operation, the manufacturing process becomes complicated and it is difficult to increase the degree of integration. Also, since the fuse can be programmed only once, it is not convenient. For this reason, as a device for applying a control voltage to the pass transistor, an SRAM that is easy to be highly integrated is generally used although stored information is lost when the power is turned off.

In the case of a large-scale FPGA, about 100 million switches of SRAM + pass transistors shown in FIG. 12 are mounted, and the number of switches tends to increase year by year due to high integration. In a CMOS integrated circuit with a technology node of 45 nm or earlier, the area of the SRAM portion is about 100 F ² when the minimum dimension is F, and occupies 50% of the entire FPGA.

1. G. Baek, et al., "Highly Scalable Non-volatile Resistive Memory using Simple Binary Oxide Driven by Asymmetric Unipolar Voltage Pulses", IEDM, pp. 587-590, 2004. ChiaHua Ho, et al., "A Highly Reliable Self-Aligned Graded Oxide WOx Resistance Memory: Conduction Mechanisms and Reliability", Symposium on VLSI Technology Digest of Technical Papers, 12B-2, pp228-229 A. Chen, et al., "Switching characteristics of Cu2O metal-insulator-metal resistive memory", APPLIED PHYSICS LETTERS, vol. 91, 123517-1-123517-3, 2007. S. Muraoka, et al., "Fast switching and long retention Fe-O ReRAM and its switching mechanism", IEDM, pp.779-782, 2007.

However, when the technology node is 32 nm or later, there is a problem that the scaling limit of the SRAM occurs due to transistor variation, and the area of the SRAM portion increases to about 400 F ² . An increase in the area of the SRAM portion leads to an increase in the cost of the FPGA, which lowers the cost competitiveness and degrades performance due to a signal delay due to an increase in the wiring length between circuits.

  Further, in the SRAM + pass transistor, a neutron beam farm error becomes a serious problem. Various cosmic rays such as α rays are flying on the ground. Among them, neutron rays with high energy enter the semiconductor substrate and collide with Si atoms. At this time, a weak pulse current flows through the substrate due to the ions released by the collision, which may change the data stored in the SRAM. Since a change in SRAM information means a circuit change, if a neutron beam error occurs, normal circuit operation will not be performed. In general applications near the ground, the probability of such a neutron beam error occurring is low compared to other error factors, so this is not a problem. However, in the space and aviation field where many high-energy neutrons fly, The problem of line errors has been known since early, and resistance to neutrons is essential.

  The present invention has been made in order to solve the above-described problems, and has been changed to an SRAM used for a programmable logic switch such as an FPGA, and has high reliability enabling high integration. An object is to provide a nonvolatile memory device.

  A nonvolatile memory device according to the present invention includes an output electrode, a first input electrode and a second input electrode arranged so as to sandwich the output electrode, and a first input electrode sandwiched between the first input electrode and the output electrode. A variable resistance layer and a second variable resistance layer sandwiched between the second input electrode and the output electrode, the first variable resistance layer includes a first metal oxide layer and a second metal oxide layer; The second resistance change layer includes a third metal oxide layer and a fourth metal oxide layer, and one of the first metal oxide layer and the second metal oxide layer is made of amorphous tantalum oxide, The other of the first metal oxide layer and the second metal oxide layer is made of a transition metal oxide, and one of the third metal oxide layer and the fourth metal oxide layer is made of amorphous tantalum oxide. And the other of the third metal oxide layer and the fourth metal oxide layer is an oxide of the transition metal. It is obtained as and a.

  In the nonvolatile memory device, the first input electrode, the first variable resistance layer, the output electrode, the second variable resistance layer, and the second input electrode may be stacked in a normal direction of the substrate. The one input electrode, the first variable resistance layer, the output electrode, the second variable resistance layer, and the second input electrode may be arranged in the planar direction of the substrate.

  In the nonvolatile memory device, the transition metal may be at least one of nickel oxide and titanium oxide. In the nonvolatile memory device, the output electrode is connected to a pass transistor.

  As described above, according to the present invention, the first variable resistance layer formed of the amorphous metal tantalum oxide and the transition metal is sandwiched between the first input electrode and the output electrode. And a second variable resistance layer composed of a transition metal and a layer composed of amorphous tantalum oxide sandwiched between the second input electrode and the output electrode, so that it is used for a switch such as an FPGA. As a result, it is possible to provide a highly reliable nonvolatile memory device that enables high integration.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[Embodiment 1]
First, Embodiment 1 of the present invention will be described with reference to FIG. FIG. 1 is a cross-sectional view schematically showing the configuration of the nonvolatile memory device according to Embodiment 1 of the present invention. The nonvolatile memory device according to the first embodiment first includes a first input electrode 101, an output electrode 104, and a second input electrode 107. In addition, the nonvolatile memory device is sandwiched between the first variable resistance layer 120 sandwiched between the first input electrode 101 and the output electrode 104, and between the output electrode 104 and the second input electrode 107. The second resistance change layer 130 is provided.

The first resistance change layer 120 includes a first metal oxide layer 102 and a second metal oxide layer 103, and the second resistance change layer 130 includes a third metal oxide layer 105 and a fourth metal oxide layer 106. Prepare. One of the first metal oxide layer 102 and the second metal oxide layer 103 is made of amorphous tantalum oxide (Ta ₂ O ₅ ), and the other is an oxide of a transition metal such as nickel oxide or titanium oxide. It is composed of Similarly, one of the third metal oxide layer 105 and the fourth metal oxide layer 106 is made of amorphous tantalum oxide (Ta ₂ O ₅ ), and the other is a transition metal such as nickel oxide or titanium oxide. It is comprised from the oxide of this. It is desirable that the tantalum oxide has a stoichiometric composition. As transition metal oxides, it is conceivable to use hafnium oxide and zirconium oxide in addition to nickel oxide and titanium oxide (see Non-Patent Document 1). Further, it is conceivable to use tungsten oxide (see Non-Patent Document 2), copper oxide (see Non-Patent Document 3), and iron oxide (see Non-Patent Document 4) as oxides of transition metals.

  In the nonvolatile memory device according to the present embodiment configured as described above, the first resistance change layer 120 and the second resistance change layer 130 are resistance change layers (elements) of bipolar operation. Therefore, by applying a predetermined voltage between the first input electrode 101 and the second input electrode 107, one of the first resistance change layer 120 and the second resistance change layer 130 is switched to a low resistance state, The other can be switched to a high resistance state. After switching in this way, a voltage corresponding to the memory (switching) state is output from the output electrode 104 by applying a voltage lower than that at the time of switching between the first input electrode 101 and the second input electrode 107. Can be made.

  Therefore, according to the nonvolatile memory device in this embodiment, the output electrode 104 can be made to function as a nonvolatile switch of the FPGA by connecting to the gate of the pass transistor, for example. In other words, the nonvolatile memory device in this embodiment can be used instead of an SRAM used for a switch such as an FPGA. In addition, according to the present embodiment, unlike an SRAM switch that requires six or more transistors, one element functions as a switch, which is very advantageous for high integration. Furthermore, since a metal oxide is used for the memory layer (resistance change layer), in principle, it is not affected by carriers due to neutrons or the like, and extremely high reliability can be realized.

  The first input electrode 101, the first variable resistance layer 120, the output electrode 104, the second variable resistance layer 130, and the second input electrode 107 may be stacked in the normal direction of a predetermined substrate. In addition, the first input electrode 101, the first variable resistance layer 120, the output electrode 104, the second variable resistance layer 130, and the second input electrode 107 are arranged in a plane direction of a predetermined substrate. Also good.

  By the way, the oxide layer and the tantalum oxide layer of transition metal such as nickel oxide each do not function stably as a variable resistance element with good reproducibility. By laminating these, it functions stably as a resistance change layer. This was found for the first time by the inventors' experiments. Here, an initial process is important in which a voltage is applied to the variable resistance layer so that the resistance value of the variable resistance layer is lower than the resistance value of the single layer tantalum oxide layer. This process is called “Forming” (see Non-Patent Documents 2 and 3). After performing this process, by applying a predetermined voltage to the resistance change layer, the resistance is changed from the high resistance state to the low resistance state, or from the low resistance state to the high resistance state, and one of the resistance states is maintained. be able to.

[Embodiment 2]
Next, a second embodiment of the present invention will be described. As shown in the cross-sectional view of FIG. 2, the nonvolatile memory device in this embodiment is formed on an interlayer film 208 formed on a silicon substrate 210 on which an integrated circuit such as a MOS transistor is formed. The vias 209 formed in are connected to the integrated circuit formed in the silicon substrate 210. The nonvolatile memory device in this embodiment includes a lower electrode (first input electrode) 201 formed so as to be connected to the via 209, a first metal oxide layer 202 made of a first metal oxide, A second metal oxide layer 203 made of two metal oxides, an output electrode 204, a third metal oxide layer 205 made of a second metal oxide, and a fourth metal oxide made of a first metal oxide. A material layer 206 and an upper electrode (second input electrode) 207 are provided in this order.

  In the present embodiment, the laminated film including the first metal oxide layer 202 and the second metal oxide layer 203 is a first resistance change layer whose resistance is changed by voltage application thereto, and the third metal A stacked film including the oxide layer 205 and the fourth metal oxide layer 206 is a second variable resistance layer in which the resistance changes when a voltage is applied thereto. These resistance change layers operate in both polarities from the low resistance state to the high resistance state, or from the high resistance state to the low resistance state, depending on the polarity of the applied voltage. In the present embodiment, the lower electrode 201, the first variable resistance layer, the output electrode 204, the second variable resistance layer, and the upper electrode 207 are stacked in the normal direction of the silicon substrate 210.

Here, the first metal oxide is preferably a material containing at least NiO or TiO ₂ . In the present embodiment, the first metal oxide is TiO ₂ . The second metal oxide is amorphous Ta ₂ O ₅ . The second metal oxide is preferably composed of stoichiometric Ta ₂ O ₅ . In addition, since TiO ₂ tends to have a microcrystalline structure, the thickness of the TiO ₂ layer is made thinner than that of the Ta ₂ O ₅ layer in order to minimize the influence of unevenness due to this. For example, the second metal oxide layer 203 and the third metal oxide layer 205 made of Ta ₂ O ₅ have a layer thickness of 10 nm. The first metal oxide layer 202 and the fourth metal oxide layer 206 made of TiO ₂ have a layer thickness of 3 nm.

  Note that the lower electrode 201, the output electrode 204, and the upper electrode 207 may basically have conductivity. For example, Au, Ni, Co, Pt, Ru, Ir, Ti, Cu, Ta, iridium-tantalum alloy (Ir-Ta), tin-added indium oxide (ITO), or alloys thereof, or oxides thereof It can be formed of nitride, fluoride, carbide, silicide or the like. Moreover, the laminated body of these materials may be sufficient. Here, the lower electrode 201, the output electrode 204, and the upper electrode 207 are made of Ru.

  The nonvolatile memory device according to this embodiment having the above-described structure includes a variable resistance layer (a stack of the first metal oxide layer 202 and the second metal oxide layer 203 sandwiched between the lower electrode 201 and the output electrode 204. The film is reduced in resistance when a positive voltage (negative voltage on the lower electrode 201 side) is applied to the output electrode 204 side, and when a negative voltage (positive voltage on the lower electrode 201 side) is applied to the output electrode 204 side. Increase resistance. In addition, the variable resistance layer (laminated film of the third metal oxide layer 205 and the fourth metal oxide layer 6) sandwiched between the upper electrode 207 and the output electrode 204 has a positive voltage (upper electrode) on the output electrode 204 side. When a negative voltage is applied to the 207 side, the resistance is reduced, and when a negative voltage is applied to the output electrode 204 side (a positive voltage is applied to the upper electrode 207 side), the resistance is increased.

  Next, an operation method of the resistance change memory device according to this embodiment is described with reference to FIG. FIG. 3A is a configuration diagram schematically showing a cross-sectional configuration of the nonvolatile memory device according to the present embodiment. The upper electrode 207 and the lower electrode 201 are V1 and V2, respectively, and the output electrode 204 is OUT. A resistance change element composed of a resistance change layer is formed between the electrodes. The resistance value of the resistance change element between V1 and OUT is R1, and the resistance value of the resistance change element between OUT and V2 is R2.

First, R1 and R2 resistance reduction (Forming operation) is performed. First, a voltage is applied between V1 and OUT to reduce the resistance of R1. For example, a positive voltage pulse was applied to the OUT electrode to reduce the resistance of R1. Next, a voltage is applied between V2 and OUT to reduce the resistance of R2. For example, a positive voltage pulse is applied to the OUT electrode to reduce the resistance of R2.
The subsequent switching operation is performed by grounding the V2 electrode and applying a positive voltage or a negative voltage to the V1 electrode as shown in Table 1 below.

First, a case where the OUT electrode is floated in a state after “Forming” (R1 and R2 are in a low resistance state) and a positive voltage pulse (+ Vpro) is applied to V1 will be described. In this state, the resistance of R2 does not change, and only R1 switches to the high resistance state. When reading the output voltage, a voltage (V _DD ) smaller than the switching voltage is applied to the V1 electrode. In this case, the output voltage is resistance-divided by R1 and R2, and becomes R2 / (R1 + R2) × V _DD .

When the resistance ratio between R1 and R2 is high, the output voltage is almost 0 (GND) and a high ON / OFF ratio is obtained. Therefore, the resistance value of R1 and R2 is preferably at least 10 times or more. In addition, when the total value of R1 and R2 is high, leakage current flowing between V1 and V2 can be reduced, and power consumption can be reduced. In order to suppress the leakage current when V _DD is 1 V to 1 nA or less, the total value of R1 and R2 is desirably 1 GΩ or more.

Next, a case where a negative voltage pulse (-Vpro) is applied to V1 will be described. In this state, first, a voltage is applied to R1 which is in the high resistance state to switch to the low resistance state, and then R2 is switched to the high resistance state by the voltage between V2 and OUT. When reading the output voltage, a voltage (V _DD ) smaller than the switching voltage is applied to the V1 electrode. In this case, the output voltage is resistance-divided by R1 and R2, and becomes R2 / (R1 + R2) × V _DD .

When the resistance ratio between R1 and R2 is high, the output voltage is almost V _{DD and a} high ON / OFF ratio is obtained. Therefore, it is desirable that the resistance value of R1 and R2 is at least 10 times or more. In addition, when the total value of R1 and R2 is high, leakage current flowing between V1 and V2 can be reduced, and power consumption can be reduced. In order to suppress the leakage current when V _DD is 1 V to 1 nA or less, the total value of R1 and R2 is desirably 1 GΩ or more.

When it is desired to set the output voltage to GND again, a positive voltage pulse is applied to V1. In this state, first, a voltage is applied to R2 which is in the high resistance state, and switching to the low resistance state is performed. Next, R1 is switched to a high resistance state by the voltage between V1 and OUT. When the read voltage V _DD is added to V1, ˜0 V (GND) is output from OUT = R2 / (R1 + R2) × V _DD . As shown in FIG. 3B, by connecting the OUT electrode to the input gate of the pass transistor 301, it operates as a switch. By applying a positive voltage pulse to V1, the pass transistor 301 is closed (becomes OFF state) and negative to V1. By applying the voltage pulse, the pass transistor is opened (turned on).

  In the present embodiment described above, since the resistance change layer has a non-volatile property that maintains the state even when there is no power supply, the stored information of R1 and R2 is not lost even when the power supply is turned off. In addition, since one element functions as a switch, it is very advantageous for high integration. Furthermore, since the memory principle is not based on charge accumulation, in principle it is hardly affected by cosmic rays and high reliability is obtained.

  Next, a method for manufacturing the nonvolatile memory device in this embodiment will be described. First, as shown in FIG. 4A, Ru is deposited as a material of the lower electrode 201 on the interlayer film 208 in which the via 209 is formed to form a Ru film. Further, an etching mask 401 is formed on the formed Ru film using a known photolithography technique and etching technique, and the Ru film is dry-etched using the etching mask 401 to form the lower electrode 201. For the etching mask 401, a material having a high selectivity with Ru, such as titanium nitride (TiN), is used. After the lower electrode 201 is formed as described above, the etching mask 401 is selectively etched and removed.

Next, TiO _{2 serving} as the first metal oxide layer 202, Ta ₂ O _{5 serving} as the second metal oxide layer 203, and Ru serving as the output electrode 204 are sequentially deposited to form a TiO ₂ film, Ta ₂ O _5. A film and a Ru film are stacked. Next, an etching mask 402 is formed on the Ru film using a known photolithography technique and etching technique. For the etching mask 401, a material such as titanium nitride having a high selection ratio with Ru, Ta ₂ O ₅ , or TiO ₂ is used.

Next, by using the formed etching mask 402 as a mask, the TiO ₂ film, the Ta ₂ O ₅ film, and the Ru film are dry-etched, as shown in FIG. A metal oxide layer 203 and an output electrode 204 are formed. After forming each layer in this manner, the etching mask 402 is selectively etched and removed.

Next, a Ta ₂ O ₅ film to be the third metal oxide layer 205, a TiO ₂ film to be the fourth metal oxide layer 206, and a Ru film to be the upper electrode 207 are formed on the output electrode 204. . Next, an etching mask 403 made of titanium nitride is formed on the Ru film using a known photolithography technique and etching technique. Next, by using the formed etching mask 403 as a mask, the Ru film, the Ta ₂ O ₅ film, and the TiO ₂ film are dry-etched, as shown in FIG. A metal oxide layer 206 and an upper electrode 207 are formed. If the etching mask 403 is selectively removed after forming each layer in this manner, the nonvolatile memory device in this embodiment can be obtained as shown in FIG. 4D.

[Embodiment 3]
Next, a third embodiment of the present invention will be described. As shown in the cross-sectional view of FIG. 5, the nonvolatile memory device is formed on the interlayer film 208 formed on the silicon substrate 210 on which an integrated circuit using MOS transistors or the like is formed, and is formed on the interlayer film 208. Vias 209 are connected to an integrated circuit formed on the silicon substrate 210. This is the same as in the second embodiment described above. The nonvolatile memory device in this embodiment includes a lower electrode (first input electrode) 201 formed to be connected to a via 209, a first metal oxide layer 502 made of a second metal oxide, The second metal oxide layer 503 made of one metal oxide, the output electrode 204, the third metal oxide layer 505 made of the first metal oxide, and the fourth metal oxide made of the second metal oxide. A physical layer 506 and an upper electrode (second input electrode) 207 are stacked in this order.

  In this embodiment mode, the stacked film including the first metal oxide layer 502 and the second metal oxide layer 503 is a first resistance change layer whose resistance is changed by voltage application thereto, and the third metal A stacked film including the oxide layer 505 and the fourth metal oxide layer 506 is a second variable resistance layer in which the resistance changes when a voltage is applied thereto. These resistance change layers operate in both polarities from the low resistance state to the high resistance state, or from the high resistance state to the low resistance state, depending on the polarity of the applied voltage.

Here, the first metal oxide and the second metal oxide are the same as those in the second embodiment described above, the first metal oxide is TiO ₂ , and the second metal oxide is Amorphous Ta ₂ O ₅ . In this embodiment, the second metal oxide layer 503 and the third metal oxide layer 505 made of the first metal oxide are arranged on the output electrode 204 side. Each electrode is the same as that in the second embodiment.

  In this embodiment, the variable resistance layer (the stacked film of the first metal oxide layer 503 and the second metal oxide layer 504) sandwiched between the lower electrode 201 and the output electrode 204 is negative on the output electrode 204 side. The resistance is reduced when a voltage (positive voltage on the lower electrode 201 side) is applied, and the resistance is increased when a positive voltage (negative voltage on the lower electrode 201 side) is applied on the output electrode 204 side. Further, the variable resistance layer (laminated film of the third metal oxide layer 505 and the fourth metal oxide layer 506) sandwiched between the upper electrode 207 and the output electrode 204 has a negative voltage (upper electrode) on the output electrode 204 side. The resistance is reduced when a positive voltage (207 side) is applied, and the resistance is increased when a positive voltage (negative voltage on the upper electrode 207 side) is applied to the output electrode 204 side.

  Next, an operation method of the nonvolatile memory device in this embodiment is described with reference to Table 2. The upper electrode 207 and the lower electrode 201 are V1 and V2, respectively, and the output electrode 204 is OUT. The laminated film between the electrodes is a resistance change element, and the resistance value of the resistance change element (the third metal oxide layer 505 and the fourth metal oxide layer 506) between V1 and OUT is set to R1, OUT−. The resistance value of the variable resistance element (the first metal oxide layer 503 and the second metal oxide layer 504) between V2 is R2.

  First, R1 and R2 resistance reduction (Forming operation) processing is performed. First, a voltage is applied between V1 and OUT to reduce the resistance of R1. For example, a positive voltage pulse is applied to the V1 electrode to reduce the resistance of R1. Next, a voltage is applied between V2 and OUT to reduce the resistance of R2. For example, a positive voltage pulse is applied to the V2 electrode to reduce the resistance of R2.

  After performing “Forming” as described above, the V2 electrode is grounded, and a positive voltage or a negative voltage is applied to the V1 electrode as shown in Table 2 below.

First, a case where the OUT electrode is floated and a negative voltage pulse (−Vpro) is applied to V1 in a state immediately after forming (R1 and R2 are in a low resistance state) will be described. In this state, the resistance of R2 does not change, and only R1 switches to the high resistance state. When reading the output voltage, a voltage (V _DD ) smaller than the switching voltage is applied to the V1 electrode. In this case, the output voltage from the OUT electrode is resistance-divided by R1 and R2, and becomes R2 / (R1 + R2) × V _DD .

When the resistance ratio between R1 and R2 is high, the output voltage is almost 0 (GND) and a high ON / OFF ratio is obtained. Therefore, the resistance value of R1 and R2 is desirably at least 10 times or more. In addition, when the total value of R1 and R2 is high, leakage current flowing between V1 and V2 can be reduced, and power consumption can be reduced. In order to suppress the leakage current when V _DD is 1 V to 1 nA or less, the total value of R1 and R2 is desirably 1 GΩ or more.

Next, a case where a positive voltage pulse (Vpro) is applied to V1 will be described. In this state, first, a voltage is applied to R1 which is in the high resistance state, and switching to the low resistance state is performed. Next, R2 is switched to a high resistance state by the voltage between V2 and OUT. When reading the output voltage, a voltage (V _DD ) smaller than the switching voltage is applied to the V1 electrode.

In this case, the output voltage is resistance-divided by R1 and R2, and becomes R2 / (R1 + R2) × V _DD . When the resistance ratio between R1 and R2 is high, the output voltage is almost V _{DD and a} high ON / OFF ratio is obtained. Therefore, it is desirable that the resistance value of R1 and R2 is at least 10 times or more. In addition, when the total value of R1 and R2 is high, leakage current flowing between V1 and V2 can be reduced, and power consumption can be reduced. In order to suppress the leakage current when V _DD is 1 V to 1 nA or less, the total value of R1 and R2 is desirably 1 GΩ or more.

When it is desired to set the output voltage to GND again, a negative voltage pulse is applied to V1 again. In this state, first, a voltage is applied to R2 which is in the high resistance state, and switching to the low resistance state is performed. Next, R1 is switched to a high resistance state by the voltage between V1 and OUT. When the read voltage V _DD is added to V1, ˜0 V (GND) is output from OUT = R2 / (R1 + R2) × V _DD . By connecting the OUT electrode to the input gate of the pass transistor, it operates as a switch, applying a negative voltage pulse to V1 closes the pass transistor, and applying a positive voltage pulse to V1 opens the pass transistor.

  Also in this embodiment, since the resistance change layer has a non-volatility that maintains the state even when there is no power supply, the stored information of R1 and R2 is not lost even when the power supply is turned off. In addition, since one element functions as a switch, it is very advantageous for high integration. Furthermore, since the memory principle is not based on charge accumulation, in principle it is hardly affected by cosmic rays and high reliability is obtained.

  Next, a method for manufacturing the nonvolatile memory device in this embodiment will be described. First, as shown in FIG. 6A, on the interlayer film 208 in which the via 209 is formed, Ru is deposited as a lower electrode material to form a Ru film. Further, an etching mask 601 is formed on the formed Ru film using a known photolithography technique and etching technique, and Ru is dry-etched using the etching mask 601 to form the lower electrode 201. For the etching mask 601, a material having a high selectivity with Ru, such as TiN, is used. After the lower electrode 201 is formed as described above, the etching mask 601 is removed by etching.

Next, Ta ₂ O _{5 serving} as the first metal oxide layer 503, TiO _{2 serving} as the second metal oxide layer 504, and Ru serving as the output electrode 204 are sequentially deposited, and a Ta ₂ O ₅ film and TiO ₂ are deposited. A film and a Ru film are stacked. Next, an etching mask 602 is formed on the Ru film using a known photolithography technique and etching technique. The etching mask 601 is made of a material having a high selectivity with respect to Ru, Ta ₂ O ₅ , and TiO ₂ such as TiN.

Next, by using the formed etching mask 602 as a mask, the Ru film, the TiO ₂ film, and the Ta ₂ O ₅ film are dry-etched, as shown in FIG. The metal oxide layer 503 and the output electrode 204 are formed. After each layer is formed in this manner, the etching mask 602 is selectively etched and removed.

Next, a TiO ₂ film to be the third metal oxide layer 505, a Ta ₂ O ₅ film to be the fourth metal oxide layer 506, and a Ru film to be the upper electrode 207 are formed on the output electrode 204. Next, an etching mask 603 made of TiN is formed on the Ru film using a known photolithography technique and etching technique. Next, by using the etching mask 603 as a mask, the Ru film, the Ta ₂ O ₅ film, and the TiO ₂ film are dry-etched to form the third metal oxide layer 505 and the fourth metal oxide layer as shown in FIG. 6C. A physical layer 506 and a fourth metal oxide layer 506 are formed. If the etching mask 603 is selectively removed after forming each layer in this manner, the nonvolatile memory device in this embodiment can be obtained as shown in FIG. 6D.

[Embodiment 4]
Next, a fourth embodiment of the present invention will be described. In this embodiment mode, a case where the nonvolatile memory device is a horizontal type is described. First, also in the nonvolatile memory device in the present embodiment, as shown in the cross-sectional view of FIG. 7, it is formed on an interlayer film 708 formed on a silicon substrate 710 on which an integrated circuit such as a MOS transistor is formed, Vias 709 formed in the interlayer film 708 are connected to an integrated circuit formed in the silicon substrate 710.

  In this embodiment mode, an output electrode 704 is connected to the via 709. Further, a first side wall electrode (first input electrode) 701 is provided on one side of the output electrode 704, and a second side wall electrode (second input electrode) 707 is provided on the other side. The first sidewall electrode 701 and the second sidewall electrode 707 are disposed to face each other with the output electrode 704 interposed therebetween. Thus, each electrode is arranged in the plane direction (lateral direction) of the silicon substrate 710, which is a feature of the nonvolatile memory device in this embodiment.

  In each of the electrodes arranged in the lateral direction as described above, first, the first metal oxide layer 702 made of the first metal oxide and the second metal are provided between the output electrode 704 and the first sidewall electrode 701. A second metal oxide layer 703 made of an oxide is provided. In addition, a third metal oxide layer 705 made of the second metal oxide and a fourth metal oxide layer 706 made of the first metal oxide are provided between the output electrode 704 and the second side wall electrode 707. Prepare.

  Note that the first sidewall electrode 701 and the second sidewall electrode 707 need not face each other with the output electrode 704 interposed therebetween. The first side wall electrode 701 and the second side wall electrode 707 may be disposed via the output electrode 704 in a state of being insulated and separated from each other. In addition, the first metal oxide layer 702 and the second metal oxide layer 703 are also arranged with the third metal oxide layer 705 and the fourth metal oxide layer 706 through the output electrode 704. Just do

  In this embodiment mode, the stacked film including the first metal oxide layer 702 and the second metal oxide layer 703 is a first resistance change layer whose resistance is changed by voltage application thereto, and the third metal A stacked film including the oxide layer 705 and the fourth metal oxide layer 706 is a second variable resistance layer in which resistance is changed by applying a voltage thereto. These resistance change layers operate in both polarities from the low resistance state to the high resistance state, or from the high resistance state to the low resistance state, depending on the polarity of the applied voltage. In the present embodiment, the first sidewall electrode 701, the first variable resistance layer, the output electrode 704, the second variable resistance layer, and the second sidewall electrode 707 are arranged in the planar direction of the @silicon substrate 710. .

Here, the first metal oxide and the second metal oxide are the same as those in the second embodiment described above, the first metal oxide is TiO ₂ , and the second metal oxide is Amorphous Ta ₂ O ₅ . In this embodiment, the second metal oxide layer 703 and the third metal oxide layer 705 made of the second metal oxide are disposed on the output electrode 704 side. Each electrode is the same as that in the second embodiment.

  In this embodiment, the variable resistance layer (the stacked film of the first metal oxide layer 702 and the second metal oxide layer 703) sandwiched between the first sidewall electrode 701 and the output electrode 704 is on the output electrode 704 side. When a positive voltage (a negative voltage is applied to the first side wall electrode 701) is applied, the resistance is reduced, and when a negative voltage (a positive voltage is applied to the first side wall electrode 701) is applied to the output electrode 704, the resistance is increased. In addition, the variable resistance layer (laminated film of the third metal oxide layer 705 and the fourth metal oxide layer 706) sandwiched between the second sidewall electrode 707 and the output electrode 704 has a positive voltage ( The resistance is reduced when a negative voltage is applied to the second side wall electrode 707, and the resistance is increased when a negative voltage is applied to the output electrode 704 side (a positive voltage is applied to the second side wall electrode 707).

  Next, an operation method of the nonvolatile memory device in this embodiment will be described with reference to FIGS. FIG. 8 is a configuration diagram schematically showing a cross-sectional configuration of the nonvolatile memory device according to the present embodiment. The first sidewall electrode 701 and the second sidewall electrode 707 are V1 and V2, respectively, and the output electrode 704 is OUT. The laminated film between the electrodes is a resistance change element, and the resistance value of the resistance change element (the first metal oxide layer 702 and the second metal oxide layer 703) between V1 and OUT is set to R1, OUT−. The resistance value of the variable resistance element between V2 (the third metal oxide layer 705 and the fourth metal oxide layer 706) is R2.

  First, R1 and R2 resistance reduction (Forming operation) processing is performed. First, a voltage is applied between V1 and OUT to reduce the resistance of R1. For example, a positive voltage pulse is applied to the OUT electrode to reduce the resistance of R1. In addition, a voltage is applied between V2 and OUT to reduce the resistance of R2. For example, a positive voltage pulse is applied to the OUT electrode to reduce the resistance of R2.

  After performing “Forming” as described above, the V2 electrode is grounded, and a positive voltage or a negative voltage is applied to the V1 electrode as shown in Table 3 below.

First, a case where the OUT electrode is floated and a positive voltage pulse (+ Vpro) is applied to V1 in a state after forming (R1 and R2 are in a low resistance state) will be described. In this state, the resistance of R2 does not change, and only R1 switches to the high resistance state. When reading the output voltage, a voltage (V _DD ) smaller than the switching voltage is applied to the V1 electrode. In this case, the output voltage from the OUT electrode is resistance-divided by R1 and R2, and becomes R2 / (R1 + R2) × V _DD .

When the resistance ratio between R1 and R2 is high, the output voltage is almost 0 (GND), and a high ON / OFF ratio is obtained. Therefore, the resistance value of R1 and R2 is preferably at least 10 times or more. In addition, when the total value of R1 and R2 is high, leakage current flowing between V1 and V2 can be reduced, and power consumption can be reduced. In order to suppress the leakage current when V _DD is 1 V to 1 nA or less, the total value of R1 and R2 is desirably 1 GΩ or more.

Next, a case where a negative voltage pulse (-Vpro) is applied to V1 will be described. In this state, first, a voltage is applied to R1 which is in the high resistance state, and switching to the low resistance state is performed. Next, R2 is switched to a high resistance state by the voltage between V2 and OUT. When reading the output voltage, a voltage (V _DD ) smaller than the switching voltage is applied to the V1 electrode.

In this case, the output voltage is resistance-divided by R1 and R2, and becomes R2 / (R1 + R2) × V _DD . When the resistance ratio between R1 and R2 is high, the output voltage is almost V _{DD and a} high ON / OFF ratio is obtained. Therefore, it is desirable that the resistance value of R1 and R2 is at least 10 times or more. In addition, when the total value of R1 and R2 is high, leakage current flowing between V1 and V2 can be reduced, and power consumption can be reduced. In order to suppress the leakage current when V _DD is 1 V to 1 nA or less, the total value of R1 and R2 is desirably 1 GΩ or more.

When it is desired to set the output voltage to GND again, a positive voltage pulse is applied to V1. In this state, first, a voltage is applied to R2 which is in the high resistance state, and switching to the low resistance state is performed. Next, R1 is switched to a high resistance state by the voltage between V1 and OUT. When the read voltage V _DD is added to V1, 0V (GND) is output from OUT = R2 / (R1 + R2) × V _DD . As shown in FIG. 3B, by connecting the OUT electrode to the input gate of the pass transistor, it operates as a switch. By applying a positive voltage pulse to V1, the pass transistor is closed, and by applying a negative voltage pulse to V1. The pass transistor opens.

  Also in this embodiment, since the resistance change layer has a non-volatility that maintains the state even when there is no power supply, the stored information of R1 and R2 is not lost even when the power supply is turned off. In addition, since one element functions as a switch, it is very advantageous for high integration. Furthermore, since the memory principle is not based on charge accumulation, in principle it is hardly affected by cosmic rays and high reliability is obtained. In addition, by using a horizontal structure, as shown in the description of the manufacturing method described later, it is possible to reduce so-called patterning steps and reduce manufacturing costs.

  Hereinafter, the manufacturing method of the nonvolatile memory device in this embodiment will be described. First, as shown in FIG. 9A, Ru is deposited as a material of the output electrode 704 on the interlayer film 208 in which the via 209 is formed to form a Ru film. Further, an etching mask 901 is formed on the formed Ru film using a known photolithography technique and etching technique, and the Ru film is dry-etched using the etching mask 901 to form the output electrode 704. For the etching mask 901, a material having a high selectivity with Ru, such as TiN, is used. After forming the output electrode 704 as described above, the etching mask 901 is removed by etching.

Then, TiO ₂ serving as the second metal oxide layer 703 and the third metal oxide layer 705 to become Ta ₂ O _5, a first metal oxide layer 702 and the fourth metal oxide layer 706, a Ru to be the first side wall electrode 701 and the second side wall electrode 707 are sequentially deposited so that the Ta ₂ O ₅ film 902, the TiO ₂ film 903, and the Ru film 904 are laminated as shown in FIG. 9B. Here, the Ta ₂ O ₅ film 902, the TiO ₂ film 903, and the Ru film 904 are formed so as to straddle the output electrode 704 in the left-right direction in FIG. 9B. On the other hand, the Ta ₂ O ₅ film 902, the TiO ₂ film 903, and the Ru film 904 are not formed on the side of the output electrode 704 in the front-rear direction of the page.

Next, the stacked Ta ₂ O ₅ film 902, the TiO ₂ film 903, and the Ru film 904 are sequentially etched back to expose the upper portion of the output electrode 704. A metal oxide layer 703, a third metal oxide layer 705, a first metal oxide layer 702, a fourth metal oxide layer 706, a first sidewall electrode 701, and a second sidewall electrode 707 are formed. To do. As a result, the nonvolatile memory device in this embodiment can be obtained.

[Embodiment 5]
Next, a fifth embodiment of the present invention will be described. As shown in the cross-sectional view of FIG. 10, the nonvolatile memory device is formed on an interlayer film 708 formed on a silicon substrate 710 on which an integrated circuit such as a MOS transistor is formed, and is formed on the interlayer film 708. Vias 709 are connected to an integrated circuit formed on the silicon substrate 710.

  Also in this embodiment, the output electrode 704 is connected to the via 709 similarly to the above-described fourth embodiment. Further, a first side wall electrode (first input electrode) 701 is provided on one side of the output electrode 704, and a second side wall electrode (second input electrode) 707 is provided on the other side. The first sidewall electrode 701 and the second sidewall electrode 707 are disposed to face each other with the output electrode 704 interposed therebetween.

  In each of the electrodes arranged in the lateral direction as described above, first, the first metal oxide layer 1002 made of the second metal oxide and the first metal are provided between the output electrode 704 and the first sidewall electrode 701. A second metal oxide layer 1003 made of an oxide is provided. In addition, a third metal oxide layer 1005 made of the first metal oxide and a fourth metal oxide layer 1006 made of the second metal oxide are provided between the output electrode 704 and the second sidewall electrode 707. Prepare. In the present embodiment, unlike the above-described fourth embodiment, a layer made of the first metal oxide is disposed on the output electrode 704 side.

  Note that the first sidewall electrode 701 and the second sidewall electrode 707 need not face each other with the output electrode 704 interposed therebetween. The first side wall electrode 701 and the second side wall electrode 707 may be disposed via the output electrode 704 in a state of being insulated and separated from each other. Further, the first metal oxide layer 1002 and the second metal oxide layer 1003 are also arranged with the third metal oxide layer 1005 and the fourth metal oxide layer 1006 through the output electrode 704. Just do

  In this embodiment mode, the stacked film including the first metal oxide layer 1002 and the second metal oxide layer 1003 is a first resistance change layer whose resistance is changed by voltage application thereto, and the third metal A stacked film including the oxide layer 1005 and the fourth metal oxide layer 1006 is a second variable resistance layer in which the resistance is changed by applying a voltage to them. These resistance change layers operate in both polarities from the low resistance state to the high resistance state, or from the high resistance state to the low resistance state, depending on the polarity of the applied voltage.

Here, the first metal oxide and the second metal oxide are the same as those in the second embodiment described above, the first metal oxide is TiO ₂ , and the second metal oxide is Amorphous Ta ₂ O ₅ . Each electrode is the same as that in the second embodiment.

  In this embodiment, the variable resistance layer (the stacked film of the first metal oxide layer 1002 and the second metal oxide layer 1003) sandwiched between the first sidewall electrode 701 and the output electrode 704 is on the output electrode 704 side. When a negative voltage (a positive voltage is applied to the first side wall electrode 701) is applied, the resistance is reduced, and when a positive voltage (a negative voltage is applied to the first side wall electrode 701) is applied to the output electrode 704, the resistance is increased.

  In addition, the variable resistance layer (laminated film of the third metal oxide layer 1005 and the fourth metal oxide layer 1006) sandwiched between the second sidewall electrode 707 and the output electrode 704 has a negative voltage ( The resistance is reduced when a positive voltage is applied to the second sidewall electrode 707, and the resistance is increased when a positive voltage is applied to the output electrode 704 side (a negative voltage is applied to the second sidewall electrode 707).

  Next, an operation method of the nonvolatile memory device in this embodiment is described with reference to Table 4. The first sidewall electrode 701 and the second sidewall electrode 707 are V1 and V2, respectively, and the output electrode 704 is OUT. The laminated film between the electrodes is a variable resistance element, and the resistance value of the variable resistance element between V1 and OUT (the laminated film of the first metal oxide layer 1002 and the second metal oxide layer 1003) is R1. , The resistance value of the variable resistance element between OUT and V2 (a stacked film of the third metal oxide layer 1005 and the fourth metal oxide layer 1006) is R2.

  First, R1 and R2 resistance reduction (Forming operation) processing is performed. First, a voltage is applied between V1 and OUT to reduce the resistance of R1. For example, a positive voltage pulse is applied to the V1 electrode to reduce the resistance of R1. In addition, a voltage is applied between V2 and OUT to reduce the resistance of R2. For example, a positive voltage pulse is applied to the V2 electrode to reduce the resistance of R2.

  After performing “Forming” as described above, the V2 electrode is grounded, and a positive voltage or a negative voltage is applied to the V1 electrode as shown in Table 4 below.

First, a case where the OUT electrode is floated in a state after forming (R1 and R2 are in a low resistance state) and a negative voltage pulse (-Vpro) is applied to V1 will be described. In this state, the resistance of R2 does not change, and only R1 switches to the high resistance state. When reading the output voltage, a voltage (V _DD ) smaller than the switching voltage is applied to the V1 electrode. In this case, the output voltage from the OUT electrode is resistance-divided by R1 and R2, and becomes R2 / (R1 + R2) × V _DD .

When the resistance ratio between R1 and R2 is high, the output voltage is almost 0 (GND), and a high ON / OFF ratio is obtained. Therefore, the resistance value of R1 and R2 is preferably at least 10 times or more. In addition, when the total value of R1 and R2 is high, leakage current flowing between V1 and V2 can be reduced, and power consumption can be reduced. In order to suppress the leakage current when V _DD is 1 V to 1 nA or less, the total value of R1 and R2 is desirably 1 GΩ or more.

Next, a case where a positive voltage pulse (Vpro) is applied to V1 will be described. In this state, first, a voltage is applied to R1 which is in the high resistance state, and switching to the low resistance state is performed. Next, R2 is switched to a high resistance state by the voltage between V2 and OUT. When reading the output voltage, a voltage (V _DD ) smaller than the switching voltage is applied to the V1 electrode.

In this case, the output voltage is resistance-divided by R1 and R2, and becomes R2 / (R1 + R2) × V _DD . When the resistance ratio between R1 and R2 is high, the output voltage is almost V _{DD and a} high ON / OFF ratio is obtained. Therefore, it is desirable that the resistance value of R1 and R2 is at least 10 times or more. In addition, when the total value of R1 and R2 is high, leakage current flowing between V1 and V2 can be reduced, and power consumption can be reduced. In order to suppress the leakage current when V _DD is 1 V to 1 nA or less, the total value of R1 and R2 is desirably 1 GΩ or more.

When it is desired to set the output voltage to GND again, a negative voltage pulse is applied to V1 again. In this state, first, a voltage is applied to R2 which is in the high resistance state, and switching to the low resistance state is performed. Next, R1 is switched to a high resistance state by the voltage between V1 and OUT. When the read voltage V _DD is added to V1, ˜0 V (GND) is output from OUT = R2 / (R1 + R2) × V _DD . By connecting the OUT electrode to the input gate of the pass transistor, it operates as a switch, applying a negative voltage pulse to V1 closes the pass transistor, and applying a positive voltage pulse to V1 opens the pass transistor.

  Also in this embodiment, since the resistance change layer has a non-volatility that maintains the state even when there is no power supply, the stored information of R1 and R2 is not lost even when the power supply is turned off. In addition, since one element functions as a switch, it is very advantageous for high integration. Furthermore, since the memory principle is not based on charge accumulation, in principle it is hardly affected by cosmic rays and high reliability is obtained. Note that the output is inverted by switching the layer made of the first metal oxide and the layer made of the second metal oxide.

  Moreover, by using a horizontal structure, as shown in the description of the manufacturing method described later, the patterning process is reduced, and the manufacturing cost can be reduced.

  Hereinafter, a method for manufacturing the nonvolatile memory device in the present embodiment will be described. First, as shown in FIG. 11A, Ru is deposited as a material of the output electrode 704 on the interlayer film 208 in which the via 209 is formed to form a Ru film. Further, an etching mask 1101 is formed on the formed Ru film using a known photolithography technique and etching technique, and the Ru film is dry-etched using the etching mask 1101 to form an output electrode 704. For the etching mask 1101, for example, a material having a high selection ratio with Ru such as TiN is used. After the output electrode 704 is formed as described above, the etching mask 1101 is etched and removed.

Next, TiO _{2 serving} as the second metal oxide layer 1003 and the third metal oxide layer 1005, Ta ₂ O _{5 serving} as the first metal oxide layer 1002 and the fourth metal oxide layer 1006, Ru to be the first side wall electrode 701 and the second side wall electrode 707 are sequentially deposited, and as shown in FIG. 11B, the TiO ₂ film 1102, the Ta ₂ O ₅ film 1103, and the Ru film 1104 are stacked. Here, the TiO ₂ film 1102, the Ta ₂ O ₅ film 1103, and the Ru film 1104 are formed so as to straddle the output electrode 704 in the left-right direction in FIG. 11B. On the other hand, the TiO ₂ film 1102, the Ta ₂ O ₅ film 1103, and the Ru film 1104 are not formed on the side of the output electrode 704 in the front-rear direction of the page.

Next, the stacked TiO ₂ film 1102, Ta ₂ O ₅ film 1103, and Ru film 1104 are sequentially etched back to expose the upper portion of the output electrode 704, and as shown in FIG. A metal oxide layer 1003, a third metal oxide layer 1005, a first metal oxide layer 1002, a fourth metal oxide layer 1006, a first sidewall electrode 701, and a second sidewall electrode 707 are formed. To do. As a result, the nonvolatile memory device in this embodiment can be obtained.

It is sectional drawing which shows typically the structure of the non-volatile memory device in Embodiment 1 of this invention. It is sectional drawing which shows typically the structure of the non-volatile memory device in Embodiment 2 of this invention. It is a block diagram which shows typically the cross-sectional structure of the non-volatile memory device in Embodiment 2 of this invention. It is a circuit diagram which shows the equivalent circuit of the non-volatile memory device in Embodiment 2 of this invention. It is process drawing explaining the manufacturing method of the non-volatile memory device in Embodiment 2 of this invention. It is process drawing explaining the manufacturing method of the non-volatile memory device in Embodiment 2 of this invention. It is process drawing explaining the manufacturing method of the non-volatile memory device in Embodiment 2 of this invention. It is process drawing explaining the manufacturing method of the non-volatile memory device in Embodiment 2 of this invention. It is sectional drawing which shows typically the structure of the non-volatile memory device in Embodiment 3 of this invention. It is process drawing explaining the manufacturing method of the non-volatile memory device in Embodiment 3 of this invention. It is process drawing explaining the manufacturing method of the non-volatile memory device in Embodiment 3 of this invention. It is process drawing explaining the manufacturing method of the non-volatile memory device in Embodiment 3 of this invention. It is process drawing explaining the manufacturing method of the non-volatile memory device in Embodiment 3 of this invention. It is sectional drawing which shows typically the structure of the non-volatile memory device in Embodiment 4 of this invention. It is a block diagram which shows typically the cross-sectional structure of the non-volatile memory device in Embodiment 4 of this invention. It is process drawing explaining the manufacturing method of the non-volatile memory device in Embodiment 4 of this invention. It is process drawing explaining the manufacturing method of the non-volatile memory device in Embodiment 4 of this invention. It is process drawing explaining the manufacturing method of the non-volatile memory device in Embodiment 4 of this invention. It is sectional drawing which shows typically the structure of the non-volatile memory device in Embodiment 5 of this invention. It is process drawing explaining the manufacturing method of the non-volatile memory device in Embodiment 5 of this invention. It is process drawing explaining the manufacturing method of the non-volatile memory device in Embodiment 5 of this invention. It is process drawing explaining the manufacturing method of the non-volatile memory device in Embodiment 5 of this invention. It is a circuit diagram showing the composition of a circuit provided with a pass transistor and SRAM which outputs a control voltage to the gate of this pass transistor as a switch device used in programmable logic.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 101 ... 1st input electrode, 102 ... 1st metal oxide layer, 103 ... 2nd metal oxide layer, 104 ... Output electrode, 105 ... 3rd metal oxide layer, 106 ... 4th metal oxide layer, 107 ... 2nd input electrode, 120 ... 1st variable resistance layer, 130 ... 2nd variable resistance layer.

Claims (5)

An output electrode, and a first input electrode and a second input electrode arranged so as to sandwich the output electrode;
A first variable resistance layer sandwiched between the first input electrode and the output electrode;
A second variable resistance layer sandwiched between the second input electrode and the output electrode,
The first resistance change layer includes a first metal oxide layer and a second metal oxide layer,
The second resistance change layer includes a third metal oxide layer and a fourth metal oxide layer,
One of the first metal oxide layer and the second metal oxide layer is composed of amorphous tantalum oxide,
The other of the first metal oxide layer and the second metal oxide layer is composed of an oxide of a transition metal,
One of the third metal oxide layer and the fourth metal oxide layer is composed of amorphous tantalum oxide,
The other of the third metal oxide layer and the fourth metal oxide layer is made of a transition metal oxide. The nonvolatile memory device according to claim 1,
The first input electrode, the first variable resistance layer, the output electrode, the second variable resistance layer, and the second input electrode are stacked in a normal direction of the substrate. Storage device. The nonvolatile memory device according to claim 1,
The non-volatile memory, wherein the first input electrode, the first variable resistance layer, the output electrode, the second variable resistance layer, and the second input electrode are arranged in a planar direction of a substrate. apparatus. The non-volatile memory device according to claim 1,
The non-volatile memory device, wherein the transition metal is at least one of nickel oxide and titanium oxide. The non-volatile memory device according to claim 1,
The non-volatile memory device, wherein the output electrode is connected to a pass transistor.

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