JP2004095567A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a structure realizing a power management semiconductor device or an analog semiconductor device being fabricated at a low cost in a short term and capable of a low voltage operation while exhibiting low power consumption, high driving power and high accuracy. <P>SOLUTION: The semiconductor device comprises a buried insulating film provided on a supporting substrate, a semiconductor thin film provided on the buried insulating film, and an MOS transistor formed on the semiconductor thin film wherein the buried insulating film is formed thicker beneath the source and drain of the MOS transistor as compared with other regions. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device that requires low voltage operation, low power consumption, and high drivability of a MOS transistor formed on an SOI substrate, particularly a voltage detector (hereinafter, referred to as VD) and a constant voltage regulator (hereinafter, referred to as VD). The present invention relates to a power management semiconductor device such as a voltage regulator (hereinafter abbreviated as VR) and a switching regulator (hereinafter abbreviated as SWR) and an analog semiconductor device such as an operational amplifier and a comparator.
[0002]
[Prior art]
FIG. 4 shows a schematic sectional view of a conventional semiconductor device. A buried insulating film 222 is formed on a support substrate 201, and an N well 202 and a P well 208 are formed in the semiconductor thin film of the SOI structure substrate in which a semiconductor thin film is formed on the buried insulating film 222. P + 204 is formed in the well 202, N + 203 is formed in the P well, a gate insulating film 205 is formed on the N well 202 and the P well 208, and a gate electrode 232 is formed on the gate insulating film 205. A field insulating film 206 is formed between the NMOS 213 and the PMOS 212. The field insulating film 206 separates the NMOS 213 and the PMOS 212 from each other. By using an SOI substrate, the field insulating film 206 and the buried insulating film 222 come into contact with each other and can be electrically completely separated, so that soft error free and latch up free are achieved.
[0003]
In addition, since a parasitic capacitance is reduced by using an SOI substrate, a high-speed IC can be realized. Further, it is possible to realize a low power consumption IC by improving the transistor characteristics.
[0004]
[Problems to be solved by the invention]
In the above-described semiconductor device having the conventional structure, the MOS transistor manufactured using the SOI substrate is high-speed, low power consumption, soft error free, and latch-up free. However, the supporting substrate is a gate electrode, and the buried insulating film is a gate insulating film. Since a MOS transistor to be a film is also manufactured, there is a problem that a threshold voltage of the MOS transistor and a change in IV characteristics are caused by a potential of a supporting substrate. There is a problem that the characteristic variation is particularly large near the boundary between the semiconductor thin film and the low threshold region where the semiconductor thin film is thin.
[0005]
FIG. 5 shows the IV characteristics of a MOS transistor having a low threshold voltage region. FIG. 5 shows that the channel under the gate electrode is turned on after the rise of the parasitic transistor in the low threshold voltage region. In the case of having a low threshold voltage region, the current consumption of the MOS transistor increases, so that the IC performance remarkably deteriorates.
[0006]
By fixing the potential of the supporting substrate, it is possible to suppress a change in the threshold voltage of the MOS transistor and a change in the IV characteristics. However, in the case of the complementary MOS transistor, when the supporting substrate is grounded, the P-type MOS transistor is back gated, When the supporting substrate is fixed to the power supply, there is a problem that the N-type MOS transistor is back gated. By fixing the potential of the supporting substrate to the intermediate potential so as to reduce the influence on the P-type transistor and the N-type transistor, the back gate phenomenon of the MOS transistor can be reduced, but the influence of the back gate was not negligible. .
[0007]
Further, by forming a channel stopper in the low threshold voltage region at the boundary between the MOS transistor and the field insulating film, it is possible to cut the channel in the low threshold voltage region, thereby suppressing an increase in current consumption of the MOS transistor. However, there is a problem that the number of manufacturing steps increases.
[0008]
The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor device with high speed, low power consumption, low cost, and high accuracy.
[0009]
[Means for Solving the Problems]
In order to solve the above problems, the present invention uses the following means.
[0010]
(1) In a semiconductor device having a support substrate, a buried insulating film provided on the support substrate, a semiconductor thin film provided on the buried insulating film, and a MOS transistor formed on the semiconductor thin film, A semiconductor device in which the buried insulating film below the source and the drain of the transistor is thicker than the region other than the region below the source and the drain of the MOS transistor.
[0011]
(2) The thickness of the buried insulating film is 2,000 to 10,000 ° near the boundary between the MOS transistor and the field insulating film, and 1,000 to 5,000 ° in a region other than near the boundary between the MOS transistor and the field insulating film. Semiconductor device.
[0012]
(3) The MOS transistor has a high impurity concentration diffusion layer in which a source and a drain overlap a gate electrode in a plane, and a channel only on the drain side or in both the source and the drain more than the high concentration diffusion layer. A semiconductor device including a MOS transistor having a first structure including a diffusion layer having a low impurity concentration, which is diffused to the side and overlaps the gate electrode in a plane, is provided.
[0013]
(4) The MOS transistor has a low impurity concentration diffusion layer in which only the drain side planarly overlaps with the gate electrode, or in which both the source and the drain planarly overlap with the gate electrode, Only the drain side does not overlap with the gate electrode in a plane, or both the source and the drain consist of a diffusion layer with a high impurity concentration which does not overlap with the gate electrode in a plane. The semiconductor device includes a MOS transistor having a second structure in which the insulating film between the electrodes is thicker than the gate insulating film.
[0014]
(5) In the MOS transistor having the first structure and the MOS transistor having the second structure, the impurity concentration of the low impurity concentration diffusion layer is 1 × 10 ¹⁶ to 1 × 10 ¹⁸ atoms / cm ³ . In the semiconductor device having the MOS transistor having the above structure and the MOS transistor having the second structure, the impurity concentration of the high impurity concentration diffusion layer is 1 × 10 ¹⁹ atoms / cm ³ or more.
[0015]
(6) A semiconductor device in which the gate electrode of the MOS transistor is N-type conductive polysilicon and has an impurity concentration of 1 × 10 ¹⁹ atoms / cm ³ or more.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0017]
FIG. 1 is a schematic sectional view showing a first embodiment of the semiconductor device of the present invention. In the semiconductor device according to the first embodiment of the present invention, a buried insulating film 122, for example, a silicon oxide film is formed on a support substrate 101, for example, a high-resistance silicon substrate, and a semiconductor thin film, for example, silicon, is formed on the buried oxide film 122. On a SOI substrate on which a thin film is formed, a PMOS 112 having a Double Diffused Drain (DDD) structure composed of an N well 102, P + 104, a gate oxide film 105, a gate electrode 107, and P-120, a P well 108, N + 103, and a gate It comprises a complementary MOS transistor composed of an oxide film 105, an NMOS 113 composed of a gate electrode 107 and N-109, and a field insulating film. The gate electrode is formed of polysilicon, and the impurity concentration is preferably 1 × 10 ¹⁸ atoms / cm ³ or more in order to reduce the gate electrode sheet resistance. The gate electrode 107 contains a donor impurity such as phosphorus or arsenic.
[0018]
The MOS transistor structure shown in FIG. 1 is formed, for example, by selectively forming a low impurity concentration diffusion layer by ion implantation and heat treatment, and then providing a high impurity concentration diffusion layer. Diffusion layer of low impurity concentration, concentration using boron or BF ₂ is ^{1 × 10 16 ~1 × 10 18} atoms / cm 3 approximately in terms of hot carriers and pressure are preferred as an impurity in the case of P-120 of PMOS112 In the case of N- of the NMOS 113, phosphorus or arsenic is used as an impurity, and the concentration is preferably about 1 × 10 ¹⁶ to 1 × 10 ¹⁸ atoms / cm ³ from the viewpoint of hot carriers and breakdown voltage. Diffusion layer of a high impurity concentration, because concentration is low sheet resistance using boron or BF ₂ as an impurity in the case of P + 104 of PMOS 112, preferably 1 × ¹⁰ 19 atoms / cm ³ or more, in the case of N + 103 of NMOS113 Is preferably 1 × 10 ¹⁹ atoms / cm ³ or more in order to lower the sheet resistance by using phosphorus or arsenic as an impurity.
[0019]
The difference between the lateral diffusion amounts of the thin diffusion layers N-109 and P-120 and the deep diffusion layers N + 103 and P + 104 to the channel side is usually about 0.2 μm to 1 μm. Although only one side of the NMOS 113 and the PMOS 112 has the DDD structure in FIG. 1, an appropriate structure can be selected in the circuit depending on how the element is used in the circuit. Normally, if the current direction is bidirectional and the source and drain are switched on a case-by-case basis and if a withstand voltage is required in both directions, both the source and drain have a DDD structure, and the current direction is unidirectional and the source and drain are fixed. In such a case, only one side, that is, the drain side has a DDD structure in order to reduce the effective channel length.
[0020]
The contact between the field insulating film 106 and the buried insulating film 122 enables the PMOS 112 and the NMOS 113 to be electrically isolated from each other, so that the PMOS 112 and the NMOS 113 are free from soft errors and free from latch-up.
[0021]
Furthermore, by using an SOI substrate, a parasitic capacitance is reduced, so that a high-speed device can be obtained. Since weak inversion region characteristics are improved, low power consumption can be realized.
[0022]
By increasing the thickness of the oxide film in the low threshold voltage region as in the buried insulating film 122, the threshold voltage in the low threshold voltage region increases, so that the current consumption of the MOS transistor does not increase and the increase in the number of manufacturing steps is prevented. It becomes possible.
[0023]
FIG. 6 shows IV characteristics of the semiconductor device of the present invention. In FIG. 6, the threshold voltage in the low threshold voltage region is increased by increasing the thickness of the buried insulating film in the low threshold voltage region, so that it can be confirmed that the leakage current is reduced.
[0024]
The thickness of the buried insulating film 122 is preferably 2000 to 10000 ° near the boundary between the MOS transistor and the field insulating film 106 from the viewpoint of the threshold voltage value in the low threshold voltage region and the manufacturing TAT. The region other than the vicinity of the boundary is preferably 1000 to 5000 ° from the viewpoint of the performance of the MOS transistor.
[0025]
In many cases, the thickness of the semiconductor thin film is set to 100 to 10,000 °. When the semiconductor thin film is thinned, a low-voltage, low power consumption, high-speed IC can be formed. In this case, a high withstand voltage and low power consumption IC can be configured.
[0026]
In addition, the MOS transistor according to the first embodiment of the present invention is not limited to an enhancement type (hereinafter referred to as E type), a depletion type (hereinafter referred to as D type), a surface channel type, and a buried channel type. It goes without saying that a high-performance IC can be configured.
[0027]
Next, specific effects when the present invention is applied to an actual product will be described with reference to FIG. FIG. 2 shows an outline of the configuration of a regular VR using a semiconductor device. VR includes a reference voltage circuit 123, an error amplifier 124, a PMOS output element 125, and a voltage dividing circuit 130 including a resistor 129, and a current that always requires a constant voltage even if an arbitrary voltage is input to the input terminal 126. The semiconductor device has a function of outputting a value to an output terminal 128 together with the value.
[0028]
In recent years, VRs especially for portable devices have been required to reduce input voltage, reduce power consumption, output high current even with a small input / output potential difference, increase output voltage accuracy, reduce cost, and reduce size. Has been requested. In particular, cost reduction and miniaturization are high-priority requirements. In order to meet the above-mentioned demands, the error amplifier, the PMOS output element and the reference voltage circuit are constituted by the structure of the present invention, that is, the CMOS capable of reducing the threshold voltage and increasing the precision at a low cost, thereby achieving low-voltage operation and low-voltage operation. It is possible to cope with higher precision of power consumption and output voltage.
[0029]
Furthermore, it will be specifically described that the structure of the present invention has an extremely great effect on cost reduction, which is the highest priority requirement, that is, reduction in chip size, miniaturization, and high accuracy.
[0030]
The VR outputs a current of several tens mA to several hundred mA, which depends 100% on the driving capability of the PMOS output element. Depending on the product, the PMOS output element may occupy almost half of the chip area. Therefore, how to reduce the size of the PMOS output element is the key to cost reduction and miniaturization.
[0031]
On the other hand, although the demand for lowering the input voltage and the market demand for high current output under a small input / output potential difference are also strong, this is because the voltage applied to the gate in the PMOS output element is small and the voltage between the source and drain is low. It indicates that the current is high in the unsaturated operation mode in which the voltage is small.
[0032]
The drain current of the MOS transistor in the unsaturated operation is Id = (μ · Cox · W / L) × {(Vgs−Vth) −1 / 2 · Vds} × Vds− (1) Formula Id: drain current μ: mobility Cox: expressed by gate insulating film capacitance W: channel width L: channel length Vgs: gate-source voltage Vth: threshold voltage Vds: drain-source voltage.
[0033]
In order to make the drain sufficiently large even if Vgs and Vds are small without increasing the area, it is necessary to reduce the channel length, decrease Vth, and further improve the mobility according to the equation (1).
[0034]
The MOS transistor structure in which the buried insulating film thickness in the low threshold voltage region is increased by using the SOI substrate of the present invention can reduce the threshold voltage and reduce the channel length while suppressing the leakage current at the time of turning off. It will be understood that this is a very effective means for reducing the cost, reducing the size, and increasing the accuracy of the above-mentioned VR because the mobility is improved by the reduction of the parasitic resistance.
[0035]
Further, the MOS type transistor structure in which the buried insulating film thickness in the low threshold voltage region is increased by using the SOI substrate of the present invention makes it possible to practically use a PMOS E / D type reference voltage circuit. Therefore, in the E / D type reference voltage circuit, either the NMOS or the PMOS can be selected, and the present invention has an advantage that the degree of freedom in circuit design is increased.
[0036]
The effects of the present invention in the VR have been described above. However, the present invention is also applicable to a SWR in which a high-output element is mounted and a VD in which demands for low-voltage operation, low power consumption, low cost, miniaturization, and high accuracy are strong. It should also be noted that the application of the present invention provides a great effect similar to that of VR.
[0037]
FIG. 3 is a schematic sectional view showing a second embodiment of the semiconductor device of the present invention. The buried insulating film has a structure in which the buried insulating film thickness in the low threshold voltage region is increased, and has the same effects of low voltage operation, low power consumption, low cost, and high precision as in the embodiment shown in FIG. In a MOS transistor, only the source and the drain or the drain are diffusion layers P-120 and N-109 having a low impurity concentration, and only the source and the drain or the drain are spaced apart from the gate electrode and a thick insulating film 114 is provided therebetween. The MOS transistor has a diffused layer P + 104 and N + 103 having a high impurity concentration. In the structure shown in FIG. 3, since the thick insulating film is provided between the high impurity concentration diffusion layer and the gate electrode, the effect of the electric field relaxation is large, and a high withstand voltage operation, for example, an operation of several tens of volts to several hundreds of volts is achieved. There is a merit that it can respond. However, there is a disadvantage that the element size cannot be reduced.
[0038]
In the structure shown in FIG. 3, for example, after a diffusion layer having a low impurity concentration is selectively formed, a portion between the gate electrode and the source and the drain or between the gate electrode and the drain is formed at the same time as the formation of a so-called LOCOS for element isolation. It is formed by forming an insulating film, forming a gate electrode, and then providing a diffusion layer having a high impurity concentration. In the case of P-120 of the PMOS 112, boron or BF ₂ is used as the impurity for the diffusion layer having a low impurity concentration, and the concentration is preferably about 1 × 10 ¹⁶ to 1 × 10 ¹⁸ atoms / cm ³ from the viewpoint of withstand voltage. In the case of N-109, phosphorus or arsenic is used as an impurity, and the concentration is preferably about 1 × 10 ¹⁶ to 1 × 10 ¹⁸ atoms / cm ³ from the viewpoint of withstand voltage. Diffusion layer of a high impurity concentration, because concentration is low sheet resistance using boron or BF ₂ as an impurity in the case of P + 104 of PMOS 112, preferably 1 × ¹⁰ 19 atoms / cm ³ or more, in the case of N + 103 of NMOS113 Is preferably 1 × 10 ¹⁹ atoms / cm ³ or more in order to lower the sheet resistance by using phosphorus or arsenic as an impurity.
[0039]
The thickness of the insulating film formed between the gate electrode and the drain is usually the same as the thickness of the field oxide film for element isolation, about several thousand to about 1 μm, and the distance from the gate electrode to the high impurity concentration diffusion is Although it depends on the voltage input to the semiconductor device, it is usually about 1 μm to several μm. Although only one side of the PMOS 112 has a high breakdown voltage structure in FIG. 3, an appropriate structure can be selected in the circuit depending on how the element is used in the circuit. Normally, if the current direction is bidirectional and the source and drain are switched on a case-by-case basis and if a withstand voltage is required in both directions, both the source and drain have a high withstand voltage structure, and the current direction is unidirectional and the source and drain are fixed. In such a case, only one side, that is, the drain side has a high breakdown voltage structure in order to reduce the parasitic resistance.
[0040]
Although the MOS transistors having various structures are shown in the first and second embodiments of the present invention, a semiconductor device having a high performance can be obtained by appropriately combining the specifications required for the semiconductor device and the features of each element structure. It is also possible to form For example, in a semiconductor device having two or more power supply systems, an appropriate structure is selected and combined from the element structures described above according to the voltage band including the gate oxide film thickness, if necessary. is there.
[0041]
Further, although the silicon semiconductor substrate is used as the support substrate in the embodiment of the present invention, the above-described effect can be obtained even if the support substrate is a substrate using another semiconductor material such as sapphire. Needless to say.
[0042]
【The invention's effect】
As described above, according to the present invention, in a power management semiconductor device or an analog semiconductor device including a complementary MOS transistor, the threshold voltage of the low threshold voltage region is increased by increasing the thickness of the buried insulating film in the low threshold voltage region of the MOS transistor. The leakage current can be reduced because of the high threshold voltage, making it possible to shorten the channel and lower the threshold voltage. Furthermore, the parasitic capacitance in the low threshold voltage region can be reduced, so that the speed can be increased and the manufacturing process can be increased. I will not let you.
[0043]
From the above, the semiconductor device of the present invention enables the realization of a power management semiconductor device and an analog semiconductor device that are advantageous in terms of cost, work period, and element performance.
[Brief description of the drawings]
FIG. 1 is a schematic sectional view showing a first embodiment of a semiconductor device of the present invention.
FIG. 2 is an outline of a regular VR configuration using a semiconductor device.
FIG. 3 is a schematic sectional view showing a second embodiment of the semiconductor device of the present invention.
FIG. 4 is a schematic sectional view of a conventional CMOS semiconductor device.
FIG. 5 is a diagram showing IV characteristics of a MOS transistor having a low threshold voltage region.
FIG. 6 is a diagram showing IV characteristics of a MOS transistor according to the present invention.
[Explanation of symbols]
101, 201 Support substrate 102, 202 N well 103, 203 N +
104, 204 P +
105, 205 Gate insulating film 106, 206 Field insulating film 107, 207 Gate electrode 108, 208 P well 109 N-
112, 212 PMOS
113,213 NMOS
114 Insulating film 120 P-
122, 222 embedded insulating film 123 reference voltage circuit 124 error amplifier 125 PMOS output element 126 input terminal 127 ground terminal 128 output terminal 129 resistor 130 voltage dividing circuit

Claims (6)

In a semiconductor device having a support substrate, a buried insulating film provided on the support substrate, a semiconductor thin film provided on the buried insulating film, and a MOS transistor formed on the semiconductor thin film, A semiconductor device, wherein the buried insulating film under a source and a drain is thicker than a region other than under the source and the drain of the MOS transistor. The thickness of the buried insulating film is 2000 to 10000 ° near the boundary between the MOS transistor and the field insulating film, and 1000 to 5000 ° in a region other than near the boundary between the MOS transistor and the field insulating film. The semiconductor device according to claim 1, wherein: The MOS transistor has a high impurity concentration diffusion layer in which a source and a drain overlap a gate electrode in a plane, and only the drain side or both the source and the drain diffuse further to the channel side than the high concentration diffusion layer. 2. The semiconductor device according to claim 1, further comprising a MOS transistor having a first structure comprising a gate electrode and a diffusion layer having a low impurity concentration overlapping in a plane. The MOS type transistor has a low impurity concentration diffusion layer in which only the drain side planarly overlaps the gate electrode or both the source and the drain planarly overlap the gate electrode; A high-impurity-concentration diffusion layer that does not overlap the gate electrode planarly or that both the source and the drain do not planarly overlap the gate electrode. 2. The semiconductor device according to claim 1, wherein said insulating film includes a MOS transistor having a second structure which is thicker than a gate insulating film. In the MOS transistor having the first structure and the MOS transistor having the second structure, an impurity concentration of the low impurity concentration diffusion layer is 1 × 10 ¹⁶ to 1 × 10 ¹⁸ atoms / cm ³ . 5. The semiconductor device according to claim 4, wherein the impurity concentration of the high impurity concentration diffusion layer in the MOS transistor and the MOS transistor having the second structure is 1 × 10 ¹⁹ atoms / cm ³ or more. 2. The semiconductor device according to claim 1, wherein the MOS transistor is an N-type conductive polysilicon serving as a gate electrode, and has an impurity concentration of 1 × 10 ¹⁹ atoms / cm ³ or more.

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