JP2002237524A - Complementary mos semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having low power consumption and high drive capability that can operate at a low voltage. SOLUTION: For a conductive type of a gate electrode of a CMOS, both an NMOS and a PMOS are made into a P-type polycide structure, with a layer structure consisting of a P-type monopolar of polysilicon or P-type polysilicon and a metal silicide with a high-melting point. The PMOS can be made a short channel and a low threshold voltage due to a surface channel type, and also for the NMOS of an embedded channel type made into an extremely shortly embedded channel and the short channel and the low threshold voltage can be made easily, because arsenic with a small diffusion number can be used as an impurity for controlling the threshold. A resistor used for a partial voltage circuit and a CR circuit and a fuse for laser trimming are made identical with the polysilicon layer as the gate electrode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device requiring low-voltage operation, low power consumption and high driving capability, in particular, a voltage detector (hereinafter referred to as VD) and a constant-voltage regulator (hereinafter referred to as "Voltage Regulator"). VR) and Switching Regulator (hereinafter S)
(Such as WR) and analog semiconductor devices such as operational amplifiers and comparators.

[0002]

2. Description of the Related Art FIG. 9 is a schematic sectional view of a conventional semiconductor device. The gate electrode formed on the P-type semiconductor substrate is N +
N-channel MOS transistor (hereafter referred to as NMOS) made of N-type polycrystalline silicon, and a P-channel MOS transistor (hereafter written as PMOS) whose gate electrode formed in the N-well region is also made of N + type polysilicon. A complementary MOS structure (Complementary MOS, hereinafter referred to as CMOS) consisting of: and a resistor used for a voltage divider circuit for dividing the voltage formed on the field insulating film or a CR circuit for setting the time constant It is composed of Resistors are CMOS with N-type conductivity because of the simplicity of the manufacturing method.
Of the same layer and the same conductivity type as that of the gate electrode. In order to set the voltage division by the voltage divider circuit and the time constant by the CR circuit with high accuracy, N
A trimming fuse made of + -type polycrystalline silicon is formed.

[0003]

In a semiconductor device having the above-described conventional structure, an enhancement-type NMOS (hereinafter referred to as an E-type NMO) having a standard threshold voltage of about 0.7 V is used.
S) is a surface channel whose channel is formed on the surface of the semiconductor substrate due to the work function of the gate electrode and the semiconductor substrate because the conductivity type of the gate electrode is N + type polycrystalline silicon. -0.7
In the enhancement type PMOS of about V (hereinafter referred to as E type PMOS), a channel is formed somewhat inside the semiconductor substrate from the surface of the semiconductor substrate due to the work function of the gate electrode and the N well, which are N + type polysilicon. Embedded channel.

In a buried channel type E-type PMOS, a threshold voltage is set to, for example, -0.5 V in order to realize a low voltage operation.
With the above setting, the subthreshold characteristic, which is an index of the low-voltage operation of the MOS transistor, is extremely deteriorated, so that the leakage current when the PMOS is off increases,
As a result, the current consumption of the semiconductor device during standby increases remarkably, and it is difficult to apply it to portable devices such as cellular phones and portable terminals, whose demand is large in recent years and the market is expected to further develop in the future. Have a problem. On the other hand, as a technical measure to achieve both the low voltage operation and the low current consumption, which are the above problems, the NMOS shown in FIGS.
The so-called same-polarity gate technology in which the conductivity type of the gate electrode is N-type and the conductivity type of the gate electrode of the PMOS is P-type is generally known. In this case, E-type NMOS and E-type PMOS
Since both are surface channel type MOS transistors, even if the threshold voltage is reduced, both the low-voltage operation and the low power consumption can be achieved without extremely deteriorating the sub-threshold coefficient.

However, the same-polarity gate CMOS has an increased number of steps since the polarity of the gate is made separately for both NMOS and PMOS in the manufacturing process, compared to CMOS which is a gate electrode having only N + polysilicon single electrode. In addition, the inverter circuit, which is the most basic circuit element, usually requires an NMOS to improve the area efficiency.
And PMOS gates should be flat, avoiding connections through metal
A single polycrystalline silicon structure from NMOS to PMOS or a polycide structure composed of a stack of polycrystalline silicon and high melting point metal silicide is laid out. The fact that the impedance of the PN junction in the polycrystalline silicon is high and impractical, and in the case of a polycide structure as shown in FIG. 11, N-type and P-type impurities are introduced into the refractory metal silicide during the heat treatment in the process. There is a problem in terms of cost and characteristics, such as diffusion into the opposite conductive type gate electrodes at high speed, and as a result, the work function changes and the threshold voltage becomes unstable.

SUMMARY OF THE INVENTION An object of the present invention is to provide a structure capable of realizing a high-precision power management semiconductor device or analog semiconductor device which is low cost, has a short construction period, operates at a low voltage and consumes low power.

[0007]

In order to solve the above-mentioned problems, the present invention uses the following means. (1) N-channel type MOS transistor and P-channel type MOS transistor
In a complementary MOS semiconductor device having a transistor, a resistor, and a laser trimming fuse, the conductivity type of the gate electrode of the N-channel MOS transistor is P-type, and the conductivity type of the gate electrode of the P-channel MOS transistor is A P-type complementary MOS semiconductor device was used.

(2) A complementary MOS semiconductor device in which the P-type gate electrode of the N-channel MOS transistor and the P-type gate electrode of the P-channel MOS transistor are made of first polycrystalline silicon.

(3) The P-type gate electrode of the N-channel type MOS transistor and the P-type gate electrode of the P-channel type MOS transistor are polycide comprising a laminate of first polycrystalline silicon and a first refractory metal silicide. A complementary MOS semiconductor device having a structure is provided.

(4) A complementary MOS semiconductor device in which the resistor is the first polycrystalline silicon.

(5) The resistor made of the first polycrystalline silicon is a complementary MOS semiconductor device including a relatively low-concentration first N-type resistor.

(6) The resistor made of the first polycrystalline silicon is a complementary MOS semiconductor device including a second N-type resistor having a relatively high concentration.

(7) The resistor made of the first polycrystalline silicon is a complementary MOS semiconductor device including a relatively low-concentration first P-type resistor.

(8) The resistor made of the first polycrystalline silicon is a complementary MOS semiconductor device including a relatively high-concentration second P-type resistor.

(9) The thickness of the P-type gate electrode comprising the first polycrystalline silicon single layer is from 2000 to 600.
A complementary MOS semiconductor device having a range of 0 ° was obtained.

(10) In the P-type gate electrode having the polycide structure, which is a laminate of the first polycrystalline silicon and the first refractory metal silicide, the thickness of the first polycrystalline silicon is The complementary MOS semiconductor device has a thickness in the range of 500 ° to 2500 ° and the first refractory metal silicide in a range of 500 ° to 2500 °.

(11) When the P-type gate electrodes of the N-channel MOS transistor and the P-channel MOS transistor are formed of the first polysilicon single layer, the resistor made of the first polysilicon is used. The thickness of the body is in the range of 2,000 to 6,000, and the N-channel MOS transistor and the P-channel MOS
The film thickness of the resistor of the first polycrystalline silicon when the P-type gate electrode of the transistor has the polycide structure in which the first polycrystalline silicon and the first refractory metal silicide are stacked. Is from 500 to 250
A complementary MOS semiconductor device having a range of 0 ° was obtained.

(12) The relatively low-concentration first N-type resistor has an impurity concentration of 1 × 10 ^{14 to} 9 × 10 ¹⁸ atoms / cm ^3.
And the sheet resistance is several kΩ /
A complementary MOS semiconductor device having a resistance of about □ to several tens of kΩ / □ was used.

(13) The second N-type resistor having a relatively high concentration contains phosphorus or arsenic having an impurity concentration of 1 × 10 ¹⁹ or more, and has a sheet resistance value of about 100Ω / □ to several hundred Ω.
/ □ and temperature coefficient of several hundred ppm / ℃ to 1,000 ppm / ℃
This is a complementary MOS semiconductor device which is about the same as before and after.

(14) The relatively low-concentration first P-type resistor has an impurity concentration of 1 × 10 ^{14 to} 9 × 10 ¹⁸ atoms / cm ^3.
Contains boron or BF _{2 and} has a sheet resistance of several kΩ
/ □ to several tens of kΩ / □ was used as the complementary MOS semiconductor device.

(15) The second P-type resistor having a relatively high concentration contains boron or BF ₂ having an impurity concentration of 1 × 10 ¹⁹ atoms / cm ³ or more, and has a sheet resistance of several hundred Ω / □. From about 1 kΩ / □ to a temperature coefficient of several hundred ppm / ° C to 1,000 p.
A complementary MOS semiconductor device of about pm / ° C. was used.

(16) A complementary MOS semiconductor device in which the first refractory metal silicide is tungsten silicide, molybdenum silicide, titanium silicide or platinum silicide.

(17) The first polycrystalline silicon forming the P-type gate electrode of the N-channel MOS transistor and the P-type gate electrode of the P-channel MOS transistor has an impurity concentration of 1 × 10 ¹⁸ atoms / cm. ³ was complementary MOS semiconductor device comprising more boron or BF _2.

(18) The N-channel type MOS transistor and the P-channel type MOS transistor have a single-drain structure having a high impurity concentration diffusion layer whose source and drain overlap the P-type gate electrode in a plane. The complementary MOS semiconductor device including the MOS transistor having the first structure described above.

(19) In the N-channel MOS transistor and the P-channel MOS transistor, only the drain side overlaps the P-type gate electrode in a plane, or both the source and the drain have the P-type gate electrode.
A low impurity concentration diffusion layer that planarly overlaps the type gate electrode, and only the drain side does not planarly overlap the P-type gate electrode or both the source and the drain are the P-type gate electrode. A complementary MOS semiconductor device including a MOS transistor having a second structure including a diffusion layer having a high impurity concentration that does not overlap in a plane.

(20) In the N-channel MOS transistor and the P-channel MOS transistor, only the drain side overlaps the P-type gate electrode in a plane or both the source and the drain have the P-type gate electrode.
A low impurity concentration diffusion layer that planarly overlaps the type gate electrode, and only the drain side does not planarly overlap the P-type gate electrode or both the source and the drain are the P-type gate electrode. A third structure, comprising a high-impurity-concentration diffusion layer that does not overlap in a plane, and an insulating film between the high-impurity-concentration diffusion layer and the P-type gate electrode having a greater thickness than a gate insulating film.
Complementary MOS semiconductor device including MOS transistor.

(21) In the N-channel MOS transistor and the P-channel MOS transistor, a high impurity concentration diffusion layer whose source and drain overlap the P-type gate electrode in a plane is provided only on the drain side. Alternatively, a MOS transistor having a fourth structure comprising a low-impurity-concentration diffusion layer in which both the source and the drain further diffuse to the channel side than the high-concentration diffusion layer and overlap with the P-type gate electrode in plan view. Complementary MOS including
It was a semiconductor device.

(22) In the MOS transistor having the second structure, the MOS transistor having the third structure, and the MOS transistor having the fourth structure, the impurity concentration of the low impurity concentration diffusion layer is 1 × 10 ¹⁶ to 1 ×. 10 ¹⁸
atoms / cm ³ , and the high impurity concentration diffusion layer in the MOS transistor having the first structure, the MOS transistor having the second structure, the MOS transistor having the third structure, and the MOS transistor having the fourth structure. A complementary MOS semiconductor device having an impurity concentration of 1 × 10 ¹⁹ atoms / cm ³ or more.

(23) The MOS transistor having the second structure, the MOS transistor having the third structure, and the M transistor having the fourth structure of the N-channel MOS transistor.
The impurity of the low impurity concentration diffusion layer in the OS transistor is arsenic or phosphorus, and the N-channel MOS transistor has the first structure MOS transistor, the second structure MOS transistor, and the third structure MOS transistor. Transistor and MOS of the fourth structure
A complementary MOS semiconductor device in which the impurity of the high impurity concentration diffusion layer in the transistor is arsenic or phosphorus.

(24) The MOS transistor having the second structure, the MOS transistor having the third structure, and the M transistor having the fourth structure of the P-channel MOS transistor.
Impurity of the low impurity concentration diffusion layer in the OS transistor is boron or BF _2, the P channel type MOS transistor and the second structure of the first structure of the MOS transistor of the MOS transistor and the third structure MOS transistor and M of the fourth structure
Impurities of the high impurity concentration diffusion layer in the OS transistor has a complementary MOS semiconductor device is boron or BF _2.

(25) The N-channel MOS transistor is a complementary MOS semiconductor device including a first N-channel MOS transistor whose threshold voltage is an enhancement type of a buried channel type.

(26) The N-channel MOS transistor is a complementary MOS semiconductor device including a second N-channel MOS transistor whose threshold voltage is a buried channel type depletion type.

(27) The P-channel MOS transistor is a complementary MOS semiconductor device including a first P-channel MOS transistor whose threshold voltage is an enhancement type of a surface channel type.

(28) The P-channel MOS transistor is a complementary MOS semiconductor device including a second P-channel MOS transistor whose threshold voltage is a buried channel type depletion type.

(29) A complementary MOS semiconductor device in which the conductivity type of the laser trimming fuse is P-type.

(30) The P-type gate electrode of the N-channel MOS transistor and the P-type gate electrode of the P-channel MOS transistor are formed of a polycide layer of a first polycrystalline silicon and a first refractory metal silicide. A complementary MOS semiconductor device having a structure in which the first refractory metal silicide in a region irradiated with a laser beam of a laser trimming fuse is removed from the above-described complementary MOS semiconductor device.

[0037]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic sectional view showing one embodiment of the CMOS semiconductor device of the present invention. P-type semiconductor substrate 10
The gate electrode formed in 1 is a P + type polycrystalline silicon 1
07, an NMOS 113 having a so-called single drain structure with a source and a drain, and a P + type polycrystalline silicon 10 having a gate electrode formed in the N well region 102.
7 and a PMOS 112 having a single drain structure.
A CMOS and a voltage dividing circuit or a time constant for dividing a voltage formed on the field insulating film 106 are set.
It comprises a P-resistor 114 and an N-resistor 115 used for a CR circuit and the like, and a laser trimming fuse 401 for obtaining a highly accurate voltage division and a time constant. P + polycrystalline silicon 107 serving as a gate electrode contains an acceptor impurity such as boron or BF ₂ having a concentration of 1 × 10 ¹⁸ atoms / cm ³ or more. Resistors 114, 115
Are formed of the same layer of polycrystalline silicon as the CMOS gate electrode because of the simplicity of the manufacturing method.

When the gate electrode is made of P + polycrystalline silicon 107 in the PMOS 112, the channel of the E-type PMOS becomes a surface channel due to the work function of the N-well 102 and the gate electrode. However, the threshold is set in the surface channel type PMOS. Even if the value voltage is set to, for example, -0.5 V or more, both the low-voltage operation and the low power consumption can be performed without extremely deteriorating the sub-threshold coefficient.

On the other hand, in the NMOS 113, the channel of the E-type NMOS is a buried channel because of the relationship between the gate electrode of the P + polycrystalline silicon 107 and the work function of the P-type semiconductor substrate 101, but the threshold value is set to a desired value. In this case, the channel becomes an extremely shallow buried channel because arsenic having a small diffusion coefficient can be used as a donor impurity for threshold control. Therefore, even if the threshold voltage is set to a small value of, for example, 0.5 V or less, it is necessary to use boron having a large diffusion coefficient and a large projection range for ion implantation as an acceptor impurity for threshold control. E-type PM with N + polycrystalline silicon as gate electrode
Sub-threshold deterioration and increase in leak current can be significantly suppressed as compared with the case of OS.

As described above, the CMOS according to the present invention using a P + polycrystalline silicon single electrode as a gate electrode has a lower voltage operation and lower power consumption than the conventional CMOS using a N + polycrystalline silicon single electrode as a gate electrode. It will be appreciated that this is a valid technique.

For low-voltage operation and low power consumption, a so-called same-polarity gate CMOS technology is generally known.
At least two additional mask steps are required in comparison with a normal single-pole gate process in order to separately form a mold and an N-type.
Although the standard number of mask steps for a single-pole gate CMOS is about 10 times, the use of the same-pole gate increases the process cost by about 20%, and the present invention is also considered from the comprehensive viewpoint of the performance and cost of the semiconductor device. It can be said that a CMOS using a P + polycrystalline silicon monopolar gate electrode is effective.

FIG. 1 shows both the P-resistor 114 and the N-resistor 115. The purpose of reducing the number of steps and the cost is to consider the characteristics of these resistors and the characteristics required for the product. In some cases, only one of the P-resistor 114 and the N-resistor 115 is mounted.

The resistor is formed of the same layer of polycrystalline silicon as the gate electrode, and therefore has a thickness of about 2000 to 6000.degree., And the sheet resistance depends on the use of the resistor, but it is a normal value. Several kΩ /
It is used in the range of □ to several tens of kΩ / □. The impurity at this time is boron or BF ₂ in the P-resistor 114, and
Concentration of about × 10 ^{14 to} 9 × 10 ¹⁸ atoms / cm ³ ,
1 × 1 using phosphorus or arsenic in the resistor 115
The concentration is about 0 ^{14 to} 9 × 10 ¹⁸ atoms / cm ³ .

The laser trimming fuse 40
1 is formed of P + polycrystalline silicon formed in the same step as P + polycrystalline silicon 107.

In the case where the conventional gate electrode is N + polycrystalline silicon single-pole gate CMOS, N
Phosphorus diffusion in a diffusion furnace is generally used as doping of the type impurity, but in this case, the formation of the resistor requires a hard mask such as an oxide film or an insulating film, and in particular, a surface having a higher resistance than the N type is required. In the case of P + polycrystalline silicon single-pole gate CMOS, the impurity doping of gate polycrystalline silicon does not require a hard mask, although the P-type resistor that is advantageous and could be formed only through a more complicated process It is performed by the simple ion implantation method
The formation of both P- and N-resistors is possible,
In this regard, the present invention also has an advantage.

Next, a specific effect when the present invention is applied to an actual product will be described with reference to FIG. FIG. 2 shows an outline of the configuration of a regular VR using a semiconductor device. VR is the reference voltage circuit 123
, An error amplifier 124, a PMOS output element 125, and a resistor 12
9 and a voltage dividing circuit 130 composed of
Is a semiconductor device having a function of always outputting a constant voltage to the output terminal 128 together with a required current value even if an arbitrary voltage is input to the semiconductor device.

In recent years, especially for VRs for portable devices, low input voltage, low power consumption, high current output even with a small input / output potential difference, high accuracy output voltage, low cost,
The market demands miniaturization and the like. In particular, cost reduction and miniaturization are high priority requirements. In response to the above requirements, the structure of the present invention, that is, an error amplifier, a PMOS output element, and a reference voltage circuit are configured by CMOS capable of reducing the threshold voltage at a low cost, and have a low cost, a high resistance, and a high accuracy. By configuring the voltage dividing circuit by the P-resistor, it is possible to cope with low voltage operation, low power consumption, and high accuracy of the output voltage.

Further, it will be specifically described that the structure of the present invention has an extremely great effect on cost reduction, which is the highest priority requirement, that is, reduction in chip size and size.

The VR outputs a current of several tens mA to several hundred mA, which depends 100% on the driving capability of the PMOS output element, and depending on the product, the PMOS output element may occupy almost half of the chip area. Therefore, how to reduce the size of this PMOS output element is the key to cost reduction and miniaturization.

On the other hand, it has been stated that the demand for lowering the input voltage and the market demand for high current output under a small input / output potential difference are strong, but this is because the voltage applied to the gate in the PMOS output element is small and the source is low. And a high current in a non-saturated operation mode in which the voltage between drains is small. The drain current of the MOS transistor in the unsaturated operation is Id = (μ · Cox · W / L) × {(Vgs−Vth) −1 / 2 · Vds} × Vds (1) Equation Id: Drain current μ: Mobility Cox : Gate insulating film capacitance W: Channel width L: Channel length Vgs: Gate-source voltage Vth: Threshold voltage Vds: Drain-source voltage In order to obtain a sufficiently large drain even if Vgs or Vds is small without increasing the area, it is necessary to reduce the channel length and Vth from equation (1).

In the CMOS structure according to the present invention in which a P + polycrystalline silicon single electrode is used as a gate, the threshold voltage can be lowered and the channel length can be reduced while suppressing the leakage current at the time of off. It will be understood that this is a very effective means for reducing the cost and size of the device. Of course, even if the same-polarity gate CMOS technology is used, the same effect can be obtained with respect to the chip size, but the number of steps is increased in terms of cost, so that the effect is not as comprehensive as the present invention.

Another advantage of the P + polysilicon single-pole gate CMOS structure of the present invention in VR is that the reference voltage circuit is a so-called E / D type of an E type NMOS and a depletion type NMOS (hereinafter referred to as a D type NMOS). E-type NMOS, D-type
Both NMOSs are buried channel type, so each MOS
The threshold voltage and transconductance of the N-type polycrystalline silicon can be changed to the same degree with respect to temperature change. Another advantage is that a reference voltage circuit having a small output voltage change with respect to a temperature change can be provided as compared with a reference voltage circuit composed of a mold.

Further, with the P + polycrystalline silicon single-pole gate CMOS structure of the present invention, the conventional N + polycrystalline silicon gate structure has a large variation in the threshold voltage of the D-type, so that the PMOS cannot be used in practical use. An E / D type reference voltage circuit will also be practical. Therefore, in the reference voltage circuit of the E / D type, either the NMOS or the PMOS can be selected, and the present invention has an advantage that the degree of freedom in circuit design is increased.

The effect of the present invention in VR has been described above. However, the present invention can be applied to SWR having a high output element and VD which has strong demands for low voltage operation, low power consumption, low cost, and miniaturization. It should be noted that the effect is as great as VR.

FIG. 3 is a schematic sectional view showing another embodiment of the CMOS semiconductor device of the present invention. In the embodiment of the present invention shown in FIG. 1, the gate electrode is a single layer of P + polycrystalline silicon. In this case, the sheet resistance of the single layer of P + polycrystalline silicon is as large as about 100 Ω / □, so that high-speed operation and high-frequency operation are possible. However, there is a problem that it is difficult to apply the method to a semiconductor device that requires the above. As a countermeasure, a so-called polycide structure in which a high melting point metal silicide 116 such as tungsten silicide, molybdenum silicide, titanium silicide, or platinum silicide is formed on P + polycrystalline silicon 107 is used as a gate electrode to reduce the resistance as shown in FIG. It is. The sheet resistance value depends on the type and thickness of the refractory metal silicide, but is typically in the range of 500 ° to 2500 ° and a sheet resistance value of several tens / Ω to several Ω / □. Since the operation of the MOS itself is determined by the work function of the P + polycrystalline silicon and the semiconductor, the same effects as those described in FIG. 1 can be obtained with respect to low voltage operation, low power consumption, and low cost, and the gate electrode has a low resistance. Thus, the performance of the semiconductor device can be improved.

In FIG. 3, the P-resistor 114 and N
The resistor 115 is formed of a single layer of polycrystalline silicon, for example, it is not coated with a refractory metal silicide in advance on the portion of the polycrystalline silicon which becomes a resistor, or once has a high melting point on the polycrystalline silicon; After the metal silicide is deposited, it can be formed by a process flow in which the high melting point metal silicide is selectively removed therefrom. In this case, the total thickness of the polycrystalline silicon which is the resistor is about 2000 to 6000 mm. Since it is the same layer as the lower layer of the polycide structure described above, the thickness is reduced from 500 ° to 2500 ° as compared with the embodiment shown in FIG. 1, so that a higher resistance can be achieved, which is an advantageous structure also in this respect.

Further, the fuse 501 for laser trimming in FIG. 3 has a so-called polycide structure in which a high melting point metal silicide 116 such as tungsten silicide, molybdenum silicide, titanium silicide or platinum silicide is formed on P + polycrystalline silicon 107. The laser beam irradiation region 502 for cutting the fuse has a structure in which the high melting point metal silicide 116 such as tungsten silicide, molybdenum silicide, titanium silicide, or platinum silicide formed on the P + polycrystalline silicon 107 is removed.

By adopting this structure, the fuse can be easily cut by the laser beam, and the danger such as uncut portions can be greatly reduced. On the other hand, since the portion other than the laser beam irradiation region 502 is in a state in which the high-melting-point metal silicide 116 is mounted, the resistance can be reduced.

FIG. 4 is a schematic sectional view showing another embodiment of the CMOS semiconductor device of the present invention. P + Polycrystalline silicon monopolar C
The MOS structure is the same as the structure shown in the embodiment of FIG. 1, and has the same effects of low voltage operation, low power consumption, and low cost as in the embodiment shown in FIG. 1, but the embodiment shown in FIG. The difference is that the resistors made of polycrystalline silicon are a P + resistor 117 and an N + resistor 118 having a relatively high impurity concentration and low resistance. In a resistor circuit in which relative accuracy is important with a relatively high sheet resistance value such as a voltage dividing circuit, the P-resistor and the N-resistor shown in the embodiment of FIG. 1 are effective, but determine the time constant. For resistors that require absolute value accuracy such as CR circuits and resistors that require a low temperature coefficient, it is better to increase the impurity concentration and make the resistance relatively low, so that the absolute value accuracy and temperature coefficient Is to be improved.

The formation of the P + resistor 117 and the N + resistor 118 can be achieved, for example, by simultaneously doping impurities in polycrystalline silicon when forming the source and drain of the NMOS and PMOS in a normal CMOS formation. In this case, the P + resistor 117 contains boron or BF ₂ as an impurity and has a concentration of 1
At about × 10 ¹⁹ atoms / cm ³ or more, the sheet resistance is several hundred Ω / cm ^3.
The sheet resistance value is from about □ to about 1 kΩ / □, and the temperature coefficient is about several hundred ppm / ° C. to about 1,000 ppm / ° C. The N + resistor 118 contains phosphorus or arsenic as an impurity and has a concentration of 1 × 1.
At about 0 ¹⁹ atoms / cm ³ or more, the sheet resistance is about 100 Ω / □ to about several hundred Ω / □, and the temperature coefficient is about several hundred ppm / ° C. to about 1000 ppm / ° C. The CMOS shown in the embodiment of FIG. 4 shows a case where the gate electrode is a single layer of polycrystalline silicon. However, the CMOS resistor in which the gate electrode shown in FIG. Even if a resistor having a high concentration is applied, the effect is the same, or the performance is improved because the polycrystalline silicon can be made thinner to increase the resistance. In FIG. 4, both the N + resistor 118 and the P + resistor 117 are shown. However, in consideration of the characteristics required for the semiconductor device and the characteristics of those resistors, either one of them is used for the purpose of reducing the number of steps and cost. Of course, the semiconductor device may be constituted only by the resistor. The other description is replaced by the same reference numeral as in FIG.

FIG. 5 is a schematic sectional view showing another embodiment of the CMOS semiconductor device of the present invention. The gate electrode is a P + polycrystalline silicon 107 monopolar CMOS which is the basis of the present invention,
Low voltage operation, low power consumption, and the same as in the embodiment shown in FIG.
Although it has a low cost effect, a diffusion layer N-119 having a low impurity concentration is formed only on the source and the drain or only the drain for the purpose of improving channel length modulation in an analog circuit, suppressing reduction in reliability due to hot carriers, and improving drain withstand voltage. , P-120, and a diffusion layer N + 103 and P + 104 having a high impurity concentration provided with a source and a drain or only the drain at a distance from the gate electrode. High input voltage V
This is to support D, VR, and boost type SWR with high output voltage. The structure shown in FIG. 5 is formed, for example, by selectively forming a low impurity concentration diffusion layer and then selectively providing a high impurity concentration diffusion layer in a semiconductor by using a resist mask and an ion implantation technique.

The diffusion layer having a low impurity concentration is
In the case of −120, boron or BF ₂ is used as an impurity, and the concentration is about 1 × 10 ¹⁶ to 1 × 10 ¹⁸ atoms / cm ^{3. In} the case of N-119 of the NMOS 113, the concentration of phosphorus or arsenic is used. Is 1 × 10 ¹⁶ to 1 × 10 ¹⁸ at
oms / cm ³ . The diffusion layer with high impurity concentration is PMOS1
In the case of P + 104, boron or BF ₂ is used as an impurity, the concentration is 1 × 10 ¹⁹ atoms / cm ³ or more,
In the case of N + 103 of the MOS 113, phosphorus or arsenic is used as an impurity, and the concentration is 1 × 10 ¹⁹ atoms / cm ³ or more.

The distance from the gate electrode formed apart from the gate electrode to the high impurity concentration diffusion, the so-called offset length, is usually 0.5 μm to several μm, depending on the voltage inputted to the semiconductor device. In FIG. 5, PMOS1
12 has an offset structure only on one side, and the NMOS 113 has an offset structure on both sides. Depending on how the element is used in a circuit, an appropriate structure in the circuit can be selected regardless of the conductivity type of the MOS transistor. .
Normally, the current direction is bidirectional, and the source and drain are switched on a case-by-case basis.If withstand voltage is required in both directions, both the source and drain have an offset structure, the current direction is unidirectional, and the source and drain are fixed. In such a case, only one side, that is, the drain side has an offset structure to reduce parasitic resistance. FIG. 5 shows an example of a P + polycrystalline silicon single layer as a gate electrode.
Can be used as the gate electrode. Similarly, only the P-resistor is shown in FIG. 5 for the resistor, but the N-resistor, P + resistor, and N + resistor shown in FIGS. 1 and 4 may be selectively applied as necessary. . The other description is replaced by the same reference numeral as in FIG.

FIG. 6 is a schematic sectional view showing another embodiment of the CMOS semiconductor device of the present invention. The gate electrode is a P + polycrystalline silicon 107 monopolar CMOS which is the basis of the present invention,
Low voltage operation, low power consumption, and the same as in the embodiment shown in FIG.
Although it has an effect of low cost, diffusion layers N + 103 and P + 104 having a high impurity concentration are arranged on both the source and the drain so as to overlap with the gate electrode, and only the source and the drain or the drain overlap the gate electrode. The MOS transistor structure has a so-called Double Diffused Drain (DDD) structure in which diffusion layers N-119 and P-120 with low concentration are arranged. The purpose is to achieve the same effect as the structure shown in FIG. 5, but the difference from the embodiment shown in FIG. 5 is that the diffusion layer having a high impurity concentration overlaps with the gate electrode, so that the MOS There is an advantage that the parasitic resistance of the device can be reduced. However, there is also a drawback that the overlap between the gate and the drain, that is, a large mirror capacitance, is not suitable for high-frequency operation.

The structure shown in FIG. 6 is formed, for example, by selectively forming a diffusion layer having a low impurity concentration by ion implantation and heat treatment and then providing a diffusion layer having a high impurity concentration.
In the case of the P-120 of the PMOS 112, the diffusion layer having a low impurity concentration uses boron or BF ₂ as an impurity and has a concentration of 1%.
About × 10 ¹⁶ to 1 × 10 ¹⁸ atoms / cm ³ ,
In the case of 3 of the N-119 has a concentration with phosphorus or arsenic as an impurity is about ^{1 × 10 1 6 ~1 × 10} 18 atoms / cm 3. The diffusion layer having a high impurity concentration is the P + 1 of the PMOS 112.
In the case of No. 04, boron or BF ₂ is used as an impurity, the concentration is 1 × 10 ¹⁹ atoms / cm ³ or more.
In the case of N + 103, phosphorus or arsenic is used as an impurity, and the concentration is 1 × 10 ¹⁹ atoms / cm ³ or more.

The difference between the lateral diffusion amounts of the thin diffusion layers N-119 and P-120 and the deep diffusion layers N + 103 and P + 104 to the channel side is usually about 0.2 μm to 1 μm. FIG.
, Only one side of the PMOS 112 has a DDD structure,
Although S113 has a DDD structure on both sides, it can be selected irrespective of the conductivity type of the MOS transistor depending on how the element is used in the circuit of the element. Normally, the current direction is bidirectional and the source and drain are switched on a case-by-case basis.
If the current direction is unidirectional and the source and drain are fixed, the DDD structure is used on only one side, that is, the drain side, in order to reduce the effective channel length. FIG. 6 shows an example of a P + polycrystalline silicon single layer as the gate electrode, but the P + polycide structure shown in FIG. 3 can be used as the gate electrode. Similarly, FIG. 6 shows only the P-resistor, but the N-resistor, the P + resistor, and the N + resistor shown in FIGS. 1 and 4 may be selectively applied as necessary. . The other description is replaced by the same reference numeral as in FIG.

FIG. 7 is a schematic sectional view showing another embodiment of the CMOS semiconductor device of the present invention. The gate electrode is a P + polycrystalline silicon 107 monopolar CMOS which is the basis of the present invention,
Low voltage operation, low power consumption, and the same as in the embodiment shown in FIG.
Although it has the effect of low cost, the source and the drain are further provided with diffusion layers N-119 having a low impurity concentration, and the diffusion layer N + 103 having a high impurity concentration provided at a distance of a side spacer from the gate electrode P-120 and the gate electrode. P + 104
M with so-called Lightly Doped Drain (LDD) structure
OS transistor structure. The purpose is to achieve the same effect as the structure shown in FIGS. 5 and 6, but the difference from the embodiment shown in FIGS. 5 and 6 is that the high impurity concentration diffusion layer is formed in a self-aligned manner, so that the miniaturization is achieved. Although this is an advantageous structure, it also has a demerit that there is a limitation on the improvement of the withstand voltage.

In the structure shown in FIG. 7, for example, after forming a diffusion layer having a low impurity concentration by ion implantation and heat treatment, an insulating film is deposited by CVD (chemical vapor deposition) and anisotropic dry etching is performed. Is formed by providing a diffusion layer having a high impurity concentration in a self-aligned manner by an ion implantation method. The diffusion layer with low impurity concentration is PMOS1
In the case of 12 P-120, boron or BF ₂ is used as an impurity, and the concentration is 1 × 10 ¹⁶ to 1 × 10 ¹⁸ atoms / cm ^3.
In the case of N-119 of the NMOS 113, phosphorus or arsenic is used as an impurity and the concentration is 1 × 10 ¹⁶ to 1 ×.
It is about 10 ¹⁸ atoms / cm ³ . The diffusion layer having a high impurity concentration uses boron or BF ₂ as an impurity in the case of P + 104 of the PMOS 112 and has a concentration of 1 × 10 ¹⁹ atoms / cm ³ or more, and uses phosphorus or arsenic as an impurity in the case of N + 103 of the NMOS 113. Concentration is 1 × 10 ¹⁹ atoms / cm ³
That is all.

The width of the side spacer 121 is usually 0.2
It is about 0.5 μm to 0.5 μm. FIG. 7 shows an example of a P + polycrystalline silicon single layer as a gate electrode.
Can be used as the gate electrode. Similarly, only the P-resistor is shown in FIG. 7 for the resistor, but the N-resistor, P + resistor, and N + resistor shown in FIGS. 1 and 4 may be selectively applied as necessary. . The other description is replaced by the same reference numeral as in FIG.

FIG. 8 is a schematic sectional view showing another embodiment of the CMOS semiconductor device of the present invention. The gate electrode is a P + polycrystalline silicon 107 monopolar CMOS which is the basis of the present invention,
Low voltage operation, low power consumption, and the same as in the embodiment shown in FIG.
Although it has a low cost effect, the source and drain or only the drain is formed of a diffusion layer N-11 having a low impurity concentration.
9, P-120, and a MOS transistor structure in which the source and the drain or only the drain are spaced apart from the gate electrode and the diffusion layer N + 103 and P + 104 with a high impurity concentration are formed by providing a thick insulating film 122 therebetween. . The purpose is the same as that of the structure shown in FIG. 5, but the difference from the embodiment shown in FIG. 5 is that a thick insulating film is provided between the high impurity concentration diffusion layer and the gate electrode. The effect of the relaxation is large, and there is an advantage that it can cope with a high withstand voltage operation, for example, an operation of several tens V to several hundreds V. However, there is a disadvantage that the element size cannot be reduced.

In the structure shown in FIG. 8, for example, after a diffusion layer having a low impurity concentration is selectively formed, a so-called so-called
Simultaneously with the formation of the LOCOS, a thick insulating film is formed in a portion between the gate electrode and the source and the drain or between the gate electrode and the drain, and after forming the gate electrode, a diffusion layer having a high impurity concentration is provided. The diffusion layer with low impurity concentration
In the case of P-120 of the PMOS 112, boron or BF ₂ is used as an impurity and the concentration is 1 × 10 ¹⁶ to 1 × 10 ¹⁸ atoms.
/ Cm ³ , and in the case of N-119 of the NMOS 113, phosphorus or arsenic is used as an impurity and the concentration is 1 × 10 ¹⁶ to
It is about 1 × 10 ¹⁸ atoms / cm ³ . Diffusion layer of a high impurity concentration, PMOS112 of P + 104 boron or BF ₂ was used concentration of 1 × 10 ¹⁹ atoms / cm ³ as an impurity in the case of
In the case of N + 103 of the NMOS 113, phosphorus or arsenic is used as an impurity and the concentration is 1 × 10 ¹⁹ atoms / c.
m ³ or more.

The thickness of the insulating film formed between the gate electrode and the drain is usually the same as the thickness of the field oxide film for element isolation, about several thousand to about 1 μm. Is usually about 1 μm to several μm depending on the voltage input to the semiconductor device. In FIG. 8, only one side of the PMOS 112 has a high withstand voltage structure, and the NMOS 113 has a high withstand voltage structure on both sides. However, depending on how the element is used in the circuit, an appropriate structure in the circuit regardless of the conductivity type of the MOS transistor. Can be selected. Normally, if the current direction is bidirectional and the source and drain are switched on a case-by-case basis and if a withstand voltage is required in both directions, both the source and drain have a high withstand voltage structure, and the current direction is unidirectional and the source and drain are fixed. In such a case, only one side, that is, the drain side has a high breakdown voltage structure in order to reduce the parasitic resistance. Although FIG. 8 shows an example of a P + polycrystalline silicon single layer as the gate electrode, the P + polycide structure shown in FIG. 3 can be used as the gate electrode. Similarly, only the P-resistor is shown in FIG. 8 for the resistor, but the N-type resistor shown in FIGS.
-A resistor, a P + resistor, and an N + resistor may be selected and applied as needed. The other description is replaced by the same reference numeral as in FIG.

In the embodiments shown in FIGS. 1 and 3 to 8, MOS transistors and resistors having various structures are shown.
It is also possible to form a high-performance semiconductor device by an appropriate combination in consideration of the specifications required for the semiconductor device and the characteristics of each element structure. For example, in a semiconductor device having two or more power supply systems, an appropriate structure is selected and combined from the element structures described above according to the voltage band, including the gate oxide film thickness, if necessary. is there.

Although the embodiment of the present invention has been described with reference to the example using the P-type semiconductor substrate, the polarity of the substrate is reversed, and the N-type substrate P-type P + using the N-type semiconductor substrate is used.
It is also possible to provide a semiconductor device with low voltage operation, low power consumption, and low cost in the same manner as described above using a single-pole gate CMOS.

[0075]

As described above, the present invention relates to a CMOS, a power management semiconductor device including a resistor and a fuse for laser trimming, and an analog semiconductor device.
The conductivity type of the gate electrode of both NMOS and PMOS is P-type monopolar polycrystalline silicon or P-type polycide structure which is a laminated structure of P-type polycrystalline silicon and refractory metal silicide.
MOS is a surface channel type, so it is possible to shorten the channel and lower the threshold voltage, and it is a buried channel type
Since NMOS can use arsenic with a small diffusion coefficient as an impurity for controlling the threshold, it becomes an extremely shallow buried channel, which makes it easy to shorten the channel and lower the threshold voltage, and furthermore, a resistor and a laser used in a voltage dividing circuit and a CR circuit. By making the fuse for trimming the same layer of polycrystalline silicon as the gate electrode, the conventional N + polycrystalline silicon gate monopolar C
Unipolar gate CMO with the same polarity of the gate electrode as the MOS and the channel
It is possible to realize a power management semiconductor device and an analog semiconductor device which are more advantageous in terms of cost, construction time, and element performance than S.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing one embodiment of a CMOS semiconductor device of the present invention.

FIG. 2 is an outline of a regular VR configuration using a semiconductor device.

FIG. 3 is a schematic sectional view showing another embodiment of the CMOS semiconductor device of the present invention.

FIG. 4 is a schematic sectional view showing another embodiment of the CMOS semiconductor device of the present invention.

FIG. 5 is a schematic sectional view showing another embodiment of the CMOS semiconductor device of the present invention.

FIG. 6 is a schematic sectional view showing another embodiment of the CMOS semiconductor device of the present invention.

FIG. 7 is a schematic sectional view showing another embodiment of the CMOS semiconductor device of the present invention.

FIG. 8 is a schematic sectional view showing another embodiment of the CMOS semiconductor device of the present invention.

FIG. 9 is a schematic cross-sectional view of a conventional CMOS semiconductor device.

FIG. 10 is a schematic sectional view of a conventional CMOS semiconductor device.

FIG. 11 is a schematic cross-sectional view of a conventional CMOS semiconductor device.

[Explanation of symbols]

 101, 201 P-type semiconductor substrate 102, 202 N well 103, 203 N + 104, 204 P + 105, 205 Gate insulating film 106, 206 Field insulating film 107 P + polycrystalline silicon 108 P + polycrystalline silicon 109, 209 N + polycrystalline silicon 110 P-polysilicon 111, 211N-polycrystalline silicon 112, 212 PMOS 113, 213 NMOS 114 P-resistor 115, 215N-resistor 116, 216 Refractory metal silicide 117 P + resistor 118N + resistor 119N- Reference Signs List 120 P− 121 Side spacer 122 Insulating film 123 Reference voltage circuit 124 Error amplifier 125 PMOS output element 126 Input terminal 127 Ground terminal 128 Output terminal 129 Resistor 130 Voltage dividing circuit 231 N + polycrystalline silicon 232 P + polycrystalline silicon 4 01 Fuse for laser trimming 501 Fuse for laser trimming 502 Laser beam irradiation area

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/04 H01L 27/04 V 21/822 B 21/8234 27/06 102A 27/06 27/08 321E 29/43 29/62 GF term (reference) 4M104 BB01 CC05 DD04 DD26 EE09 FF13 FF14 GG09 GG10 GG19 HH16 HH20 5F038 AR09 AR10 AR28 AV02 AV06 AV15 BB04 BB05 EZ20 5F048 AA05 AA07 AB08 AB10 AC02 AC03 BB08BB10 BB BC06 BC07 BC18 BD05 BE03 BG12 5F064 CC12 CC22 FF27 FF30 FF42

Claims (30)

[Claims] 1. A complementary MOS semiconductor device having an N-channel MOS transistor, a P-channel MOS transistor, a resistor, and a laser trimming fuse, wherein the conductivity type of a gate electrode of the N-channel MOS transistor is P-type. A complementary MOS semiconductor device, wherein a conductivity type of a gate electrode of the P-channel MOS transistor is P-type. 2. An N-channel MOS transistor having a P
2. The complementary MOS semiconductor device according to claim 1, wherein the P-type gate electrode of the P-channel MOS transistor and the P-type gate electrode of the P-channel MOS transistor are made of first polycrystalline silicon. 3. The P-channel MOS transistor of the N-channel type MOS transistor.
2. The complementary structure according to claim 1, wherein the P-type gate electrode of the P-channel MOS transistor and the P-type gate electrode of the P-channel MOS transistor have a polycide structure composed of a stack of first polycrystalline silicon and a first refractory metal silicide. Type MOS semiconductor device. 4. The complementary MOS semiconductor device according to claim 1, wherein said resistor is said first polycrystalline silicon. 5. The device according to claim 1, wherein the resistor made of the first polycrystalline silicon includes a first N-type resistor having a relatively low concentration. Complementary MOS
Semiconductor device. 6. The device according to claim 1, wherein the resistor made of the first polycrystalline silicon includes a second N-type resistor having a relatively high concentration. Complementary MOS
Semiconductor device. 7. The device according to claim 1, wherein the resistor made of the first polycrystalline silicon includes a relatively low-concentration first P-type resistor. Complementary MOS
Semiconductor device. 8. The device according to claim 1, wherein the resistor made of the first polycrystalline silicon includes a second P-type resistor having a relatively high concentration. Complementary MOS
Semiconductor device. 9. The film thickness of the P-type gate electrode comprising the first polycrystalline silicon single layer is from 2000 to 6000 °.
3. The complementary MOS semiconductor device according to claim 1, wherein 10. The P-type gate electrode having the polycide structure, which is a laminate of the first polycrystalline silicon and the first refractory metal silicide, has a thickness of 500 °. And 2500 °, and the first refractory metal silicide has a thickness of 50
4. The complementary MOS semiconductor device according to claim 1, wherein the angle is in a range from 0 [deg.] To 2500 [deg.]. 11. The resistor made of the first polysilicon when the P-type gate electrode of the N-channel MOS transistor and the P-channel MOS transistor is made of the first polysilicon single layer. Has a thickness in the range of 2000 to 6000, and the P-type gate electrodes of the N-channel MOS transistor and the P-channel MOS transistor are formed of the first polycrystalline silicon and the first refractory metal silicide. The film thickness of the resistor of the first polycrystalline silicon in the case of the laminated polycide structure is from 500 ° to 2500 °.
Claims 1, 2, 3, 4,
5. The complementary MOS semiconductor device according to 5, 6, 7, 8, 9, 10. 12. The first N-type resistor having a relatively low concentration contains phosphorus or arsenic having an impurity concentration of 1 × 10 ^{14 to} 9 × 10 ¹⁸ atoms / cm ³ , and has a sheet resistance of several kΩ / cm 2. 2. The method according to claim 1, wherein the value is from □ to several tens kΩ / □.
6. The complementary MOS semiconductor device according to claim 4. 13. The relatively high-concentration second N-type resistor contains phosphorus or arsenic having an impurity concentration of 1 × 10 ¹⁹ atoms / cm ³ or more, and has a sheet resistance of about 100Ω / □ to several hundreds. Ω / □, temperature coefficient is several hundred ppm / ℃ to 1,000p
5. The method according to claim 1, wherein the temperature is about pm / ° C.
7. The complementary MOS semiconductor device according to 6. 14. The relatively low-concentration first P-type resistor contains boron or BF ₂ having an impurity concentration of 1 × 10 ^{14 to} 9 × 10 ¹⁸ atoms / cm ³ , and has a sheet resistance of several kΩ. / □
8. The complementary MOS semiconductor device according to claim 1, wherein the resistance is about tens kΩ / square. 15. The relatively high-concentration second P-type resistor contains boron or BF ₂ having an impurity concentration of 1 × 10 ¹⁹ atoms / cm ³ or more, and has a sheet resistance of several hundred Ω / □. 1k
Ω / □ and temperature coefficient of several hundred ppm / ℃ to 1,000 ppm /
9. The complementary MOS semiconductor device according to claim 1, wherein the temperature is around about ° C. 16. The complementary MOS semiconductor device according to claim 1, wherein said first refractory metal silicide is tungsten silicide, molybdenum silicide, titanium silicide or platinum silicide. . 17. The N-channel MOS transistor
The first polycrystalline silicon constituting the P-type gate electrode and the P-type gate electrode of the P-channel type MOS transistor contains boron or BF ₂ having an impurity concentration of 1 × 10 ¹⁸ atoms / cm ³ or more. 4. The complementary MOS semiconductor device according to claim 1, 2 or 3. 18. The N-channel MOS transistor and the P-channel MOS transistor have a single drain structure including a high impurity concentration diffusion layer whose source and drain overlap with the P-type gate electrode in a plane. 4. The complementary MOS semiconductor device according to claim 1, further comprising a MOS transistor having a certain first structure. 19. The N-channel MOS transistor and the P-channel MOS transistor, wherein only the drain side overlaps the P-type gate electrode in a plane or both the source and the drain are the P-type gate electrode. And a low-impurity-concentration diffusion layer that planarly overlaps, and only the drain side does not planarly overlap with the P-type gate electrode, or both the source and the drain planarly overlap with the P-type gate electrode. 4. The complementary MOS semiconductor device according to claim 1, further comprising a MOS transistor having a second structure comprising a diffusion layer having a high impurity concentration that does not overlap. 20. The N-channel MOS transistor and the P-channel MOS transistor, wherein only the drain side overlaps the P-type gate electrode in a plane or both the source and the drain have the P-type gate electrode. And a low-impurity-concentration diffusion layer that planarly overlaps, and only the drain side does not planarly overlap with the P-type gate electrode, or both the source and the drain planarly overlap with the P-type gate electrode. A MOS transistor having a third structure, comprising a diffusion layer having a high impurity concentration that does not overlap, and an insulating film between the diffusion layer having a high impurity concentration and the P-type gate electrode having a thickness greater than a gate insulating film.
3. The method according to claim 1, further comprising a transistor.
4. The complementary MOS semiconductor device according to 3. 21. The N-channel MOS transistor and the P-channel MOS transistor each include a high impurity concentration diffusion layer whose source and drain overlap the P-type gate electrode in a plane, A MOS transistor having a fourth structure including a low-impurity-concentration diffusion layer in which both the source and the drain further diffuse to the channel side than the high-concentration diffusion layer and overlap with the P-type gate electrode in plan view. 4. The complementary MOS semiconductor device according to claim 1, wherein the complementary MOS semiconductor device is included. 22. The low-impurity-concentration diffusion layer of the MOS transistor having the second structure, the MOS transistor having the third structure, and the MOS transistor having the fourth structure has an impurity concentration of 1 × 10 ¹⁶ to 1 × 10. ¹⁸ atom
s / cm ³ , the MOS transistor having the first structure, the MOS transistor having the second structure, the MOS transistor having the third structure, and the M transistor having the fourth structure.
22. The complementary MO according to claim 18, wherein an impurity concentration of the high impurity concentration diffusion layer in the OS transistor is 1 × 10 ¹⁹ atoms / cm ³ or more.
S semiconductor device. 23. The low-concentration impurity diffusion layer of the N-channel MOS transistor of the second structure MOS transistor, the third structure MOS transistor, and the fourth structure MOS transistor, wherein the impurity in the low impurity concentration diffusion layer is arsenic or Phosphorus, and the high impurity in the MOS transistor of the first structure, the MOS transistor of the second structure, the MOS transistor of the third structure, and the MOS transistor of the fourth structure of the N-channel MOS transistor. 18. The method according to claim 18, wherein the impurity in the concentration diffusion layer is arsenic or phosphorus.
22. The complementary MOS semiconductor device according to 9, 20, 21. 24. The low-impurity-concentration diffusion layer of the P-channel MOS transistor of the second structure MOS transistor, the third structure MOS transistor, and the fourth structure MOS transistor, wherein the impurity is boron or It is BF _2, the high in the MOS transistor of the P-channel type MOS transistor the first MOS transistor and said second MOS transistor and a MOS transistor and said fourth structure of the third structure of the structure of structure claim impurity of the impurity concentration diffusion layer is characterized in that it is a boron or BF ₂ 1
22. The complementary MOS semiconductor device according to 8, 19, 20, or 21. 25. The N-channel MOS transistor according to claim 1, wherein the N-channel MOS transistor includes a first N-channel MOS transistor whose threshold voltage is a buried channel type enhancement type. Complementary MOS
Semiconductor device. 26. The N-channel MOS transistor according to claim 1, wherein the N-channel MOS transistor includes a second N-channel MOS transistor whose threshold voltage is a buried channel type depletion type. Complementary MOS described in
Semiconductor device. 27. The P-channel MOS transistor according to claim 1, wherein the P-channel MOS transistor includes a first P-channel MOS transistor whose threshold voltage is an enhancement type of a surface channel type. Complementary MOS semiconductor device. 28. The P-channel MOS transistor according to claim 1, wherein the P-channel MOS transistor includes a second P-channel MOS transistor whose threshold voltage is a buried channel type depletion type. Complementary MOS described in
Semiconductor device. 29. The complementary MOS semiconductor device according to claim 1, wherein the conductivity type of the laser trimming fuse is P-type. 30. The N-channel MOS transistor
In the complementary MOS semiconductor device in which the P-type gate electrode and the P-type gate electrode of the P-channel MOS transistor have a polycide structure composed of a stack of a first polycrystalline silicon and a first refractory metal silicide, 4. The complementary MOS semiconductor device according to claim 3, wherein said first fuse has a structure in which a first refractory metal silicide in a region irradiated with a laser beam is removed.