JP2008277510A - Semiconductor device, and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method thereof capable of reducing a manufacturing cost by simplifying a manufacturing process. <P>SOLUTION: Into a lower part of a well region 110 of a low withstand voltage NMOS transistor 100A, impurities are injected such that impurity concentration becomes higher than that of a well region 105 of a high withstand voltage NMOS transistor 100B. Below an element separation region 102B of the high withstand voltage NMOS transistor 100B there is formed an inversion prevention region 111 with higher impurity concentration than that of a well region 105 of the high withstand voltage NMOS transistor 100B. Hereby, impurity injection with respect to the low withstand voltage NMOS transistor 100A and that with respect to the high withstand voltage NMOS transistor 100B are conducted at the same time so that the number of manufacturing processes can be reduced. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device including, for example, a MOS (metal oxide semiconductor) type transistor and a method for manufacturing the same.

  In a logic circuit transistor, miniaturization of the transistor is indispensable in order to improve the operation speed and reduce the cost, and the power supply voltage tends to decrease in order to reduce power consumption.

  On the other hand, the circuit part for power input / output interface, data write / erase in flash memory, etc., and the liquid crystal panel drive circuit requires higher withstand voltage transistors to handle higher input / output voltages than general logic circuit parts. And

In general, the following relational expressions (A) to (D) hold for a high voltage transistor.
Gate dielectric breakdown voltage: BVoxαT_ _gate ... (a)
Junction breakdown voltage: BVj∝Nb ⁻¹ (b)
Transistor _{threshold: Vthα√ (Na) × T_ gate} ... ( c)
Element isolation inversion voltage: FVth∝√ (Na ′) × _{T_field} (D)

In the above equation (a) to (d), T_ _Gate gate film thickness, Na is the surface concentration, Na 'is the isolation under the concentration, Nb is well concentration, T_ _field is isolation thickness.

  According to the relational expressions (a) to (d), the high breakdown voltage transistor needs to have a thick gate film and a low well concentration in order to ensure a breakdown voltage. The transistor dimensions and element isolation dimensions are higher than those of the low voltage transistor. There is a tendency to grow. For this reason, it is difficult to reduce the size of the high voltage circuit portion including the high voltage transistor.

  Further, from the above relational expressions (b) and (d), in order to increase the breakdown voltage, it is necessary to lower the well concentration, while the element isolation inversion voltage needs to increase the well concentration, so a trade-off relationship is established. .

  In order to avoid this trade-off relationship, a withstand voltage is secured by forming an inversion prevention layer under the element isolation region or by increasing the element isolation film thickness.

  Japanese Patent No. 2644776 (Patent Document 1) discloses a semiconductor device in which a low breakdown voltage transistor and a high breakdown voltage transistor are mixedly mounted. In this semiconductor device, a channel stopper layer is formed only in the element isolation region to improve the element isolation breakdown voltage of the high breakdown voltage transistor, thereby reducing the amount of impurities implanted on the high breakdown voltage transistor side and The pressure resistance is not adversely affected.

  In addition, the semiconductor device disclosed in Japanese Patent Laid-Open No. 9-139382 (Patent Document 2) includes a low breakdown voltage transistor, a high breakdown voltage transistor, a narrow and thin element isolation insulating film, and a wide and thick film thickness. And a thick element isolation insulating film. In manufacturing this semiconductor device, shallow impurity implantation in which impurities reach the depth of the bottom of the thin element isolation insulating film, and deep impurity implantation in which impurities reach the depth of the bottom of the thick element isolation insulating film, Is done. Thus, a channel stopper layer is formed at the bottom of each element isolation insulating film.

  Japanese Unexamined Patent Publication No. 2000-150662 (Patent Document 3) discloses a semiconductor device in which a low breakdown voltage transistor, a medium breakdown voltage transistor, and a high breakdown voltage transistor are mounted together. In this semiconductor device, the low breakdown voltage transistor, the medium breakdown voltage transistor, and the high breakdown voltage transistor share one well, and the breakdown voltage of the medium breakdown voltage transistor and the high breakdown voltage transistor is ensured. Furthermore, in the well, a high impurity concentration region is formed near the bottom of the element isolation insulating film to increase the element isolation breakdown voltage.

  However, since the semiconductor devices of Patent Documents 1 to 3 include a plurality of transistors having different withstand voltages, ion implantation must be performed for each transistor, which increases the number of processes and increases the manufacturing cost. There is a problem that it ends up.

  In Patent Document 3, a well that can secure the breakdown voltage of the high breakdown voltage transistor is formed in order to reduce the number of steps, but the impurity concentration of the well is low for the low breakdown voltage transistor.

  Therefore, in the low breakdown voltage transistor, in order to suppress the influence of the short channel effect, it is necessary to increase the gate length (source-drain distance) in order to secure the source / drain breakdown voltage.

As a result, the low breakdown voltage transistor cannot be reduced, the logic circuit becomes large, and the chip size cannot be reduced.
Japanese Patent No. 2644776 JP-A-9-139382 JP 2000-150662 A

  Therefore, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can simplify the manufacturing process and reduce the manufacturing cost.

In order to solve the above problems, a semiconductor device of the present invention is
A semiconductor device in which a plurality of transistors having different operating voltages are formed on a semiconductor substrate,
Each of the above transistors
An element isolation region formed on the surface of the semiconductor substrate;
An active region partitioned by the element isolation region;
A source region formed in the active region;
A drain region formed in the active region;
A gate insulating film formed on a region between the source region and the drain region;
A gate electrode formed on the gate insulating film,
Among the plurality of transistors, there are a low breakdown voltage transistor and a high breakdown voltage transistor whose breakdown voltage is higher than the breakdown voltage of the low breakdown voltage transistor,
Impurities are implanted below the active region of the low breakdown voltage transistor and the element isolation region of the low breakdown voltage transistor so that the impurity concentration is higher than the impurity concentration of the active region of the high breakdown voltage transistor, In addition, an inversion prevention region having an impurity concentration higher than that of the active region of the high breakdown voltage transistor is formed below the element isolation region of the high breakdown voltage transistor.

  According to the semiconductor device having the above structure, impurities are present below the active region of the low breakdown voltage transistor and the element isolation region of the low breakdown voltage transistor so that the impurity concentration is higher than the impurity concentration of the active region of the high breakdown voltage transistor. An inversion prevention region having an impurity concentration higher than the impurity concentration of the active region of the high breakdown voltage transistor is formed below the element isolation region of the high breakdown voltage transistor. And impurity implantation for the high voltage transistor can be performed simultaneously.

  Therefore, the number of manufacturing steps of the semiconductor device can be reduced, the manufacturing steps can be simplified, and the manufacturing cost can be reduced.

  Further, an inversion prevention region having an impurity concentration higher than the impurity concentration of the active region of the high breakdown voltage transistor is formed under the element isolation region of the high breakdown voltage transistor, thereby improving the punch-through breakdown voltage between the elements, The element isolation width can be reduced, and the high breakdown voltage transistor can be reduced.

A method for manufacturing a semiconductor device of the present invention includes:
A method of manufacturing a semiconductor device in which a plurality of transistors having different operating voltages are formed on a semiconductor substrate,
Each of the above transistors
An element isolation region formed on the surface of the semiconductor substrate;
An active region partitioned by the element isolation region;
A source region formed in the active region;
A drain region formed in the active region;
A gate insulating film formed on a region between the source region and the drain region;
A gate electrode formed on the gate insulating film,
Among the plurality of transistors, there are a low breakdown voltage transistor and a first high breakdown voltage transistor whose breakdown voltage is higher than the breakdown voltage of the low breakdown voltage transistor,
Impurity implantation is performed a plurality of times, and the impurity concentration is higher under the active region of the low breakdown voltage transistor and the element isolation region of the low breakdown voltage transistor than the impurity concentration of the active region of the first high breakdown voltage transistor. An inversion prevention region having an impurity concentration higher than the impurity concentration of the active region of the first high breakdown voltage transistor is formed under the element isolation region of the first high breakdown voltage transistor. It is characterized by that.

  According to the method for manufacturing a semiconductor device having the above-described structure, for example, one of the plurality of impurity implantations is a relatively high energy impurity implantation, whereby the active region of the low breakdown voltage transistor and the low breakdown voltage transistor Impurities are implanted under the element isolation region so that the impurity concentration is higher than the impurity concentration of the active region of the first high breakdown voltage transistor, and the first high breakdown voltage transistor has a first high breakdown voltage under the element isolation region. An inversion prevention region having an impurity concentration higher than that of the active region of the breakdown voltage transistor can be formed.

  Therefore, the impurity implantation for the low breakdown voltage transistor and the impurity implantation for the high breakdown voltage transistor can be performed simultaneously.

  Therefore, the number of manufacturing steps of the semiconductor device can be reduced, the manufacturing steps can be simplified, and the manufacturing cost can be reduced.

  In addition, the characteristics of the low breakdown voltage transistor are controlled without affecting the characteristics of the first high breakdown voltage transistor by making the other one of the plurality of impurity implantations a relatively low energy impurity implantation. be able to.

  In addition, since an inversion prevention region having an impurity concentration higher than the impurity concentration of the active region of the first high breakdown voltage transistor is formed under the element isolation region of the first high breakdown voltage transistor, the punch through breakdown voltage between the elements is improved. Thus, the element isolation width can be reduced, and the first high voltage transistor can be reduced.

  The relatively low energy impurity implantation may be performed after the relatively low energy impurity implantation. Alternatively, the relatively low energy impurity implantation may be performed after the relatively high energy impurity implantation. May be performed. In other words, either the relatively high energy impurity implantation or the relatively low energy impurity implantation may be performed first.

In one embodiment of a method for manufacturing a semiconductor device,
The gate insulating film of the low breakdown voltage transistor is thinner than the gate insulating film of the first high breakdown voltage transistor.

  According to the method of manufacturing the semiconductor device of the above embodiment, since the gate insulating film of the low breakdown voltage transistor is thinner than the gate insulating film of the first high breakdown voltage transistor, it is possible to prevent the operating voltage of the low breakdown voltage transistor from increasing. it can.

In one embodiment of a method for manufacturing a semiconductor device,
The inversion prevention region of the first high breakdown voltage transistor has an impurity concentration of 5 to 20 times higher than the impurity concentration of the active region.

  According to the manufacturing method of the semiconductor device of the above embodiment, since the impurity concentration of the inversion prevention region of the first high breakdown voltage transistor is more than five times higher than the impurity concentration of the active region, the breakdown voltage of the first high breakdown voltage transistor is ensured. And it can be raised sufficiently.

  In addition, since the impurity concentration of the inversion prevention region of the first high breakdown voltage transistor does not exceed 20 times the impurity concentration of the active region, the inversion voltage and punch-through breakdown voltage are increased without reducing the junction breakdown voltage of the transistor. And the element isolation width can be reduced.

In one embodiment of a method for manufacturing a semiconductor device,
The inversion prevention region of the first high breakdown voltage transistor and the active region of the low breakdown voltage transistor are formed with the same mask.

  According to the manufacturing method of the semiconductor device of the above embodiment, the inversion prevention region of the first high breakdown voltage transistor and the active region of the low breakdown voltage transistor are formed with the same mask, so that the number of manufacturing steps can be reduced. it can.

In one embodiment of a method for manufacturing a semiconductor device,
The low breakdown voltage transistor includes a lightly doped drain region formed in the active region of the low breakdown voltage transistor and having a lower impurity concentration than the source region and the drain region,
The inversion prevention region of the first high breakdown voltage transistor and the lightly doped drain region of the low breakdown voltage transistor are formed using the same mask.

  According to the method of manufacturing a semiconductor device of the above embodiment, the inversion prevention region of the first high breakdown voltage transistor and the lightly doped drain region of the low breakdown voltage transistor are formed using the same mask. Can be reduced.

In one embodiment of a method for manufacturing a semiconductor device,
Among the plurality of transistors, there is a second high breakdown voltage transistor having a higher breakdown voltage than the low breakdown voltage transistor,
The second high voltage transistor includes a drift region formed in the active region of the second high voltage transistor,
The active region of the low voltage transistor, the inversion prevention region of the first high voltage transistor, and the drift region of the second high voltage transistor are formed using the same mask.

  According to the method of manufacturing the semiconductor device of the embodiment, the active region of the low voltage transistor, the inversion prevention region of the first high voltage transistor, and the drift region of the second high voltage transistor are used using the same mask. Since it forms, the number of manufacturing processes can be reduced.

In one embodiment of a method for manufacturing a semiconductor device,
Among the plurality of transistors, there are second, third, and fourth high breakdown voltage transistors having a breakdown voltage higher than that of the low breakdown voltage transistor,
The second high voltage transistor includes a drift region formed in the active region of the second high voltage transistor,
The active region of the low-voltage transistor, the inversion prevention region of the first high-voltage transistor, the drift region of the second high-voltage transistor, the active region of the third high-voltage transistor, and the fourth The active region of the high voltage transistor is formed using the same mask.

  According to the manufacturing method of the semiconductor device of the above embodiment, the inversion prevention region of the first high breakdown voltage transistor, the drift region of the second high breakdown voltage transistor, the active region of the third high breakdown voltage transistor, and the fourth high breakdown voltage transistor. Since the active region is formed using the same mask, the number of manufacturing steps can be reduced.

In one embodiment of a method for manufacturing a semiconductor device,
Forming a protective diode for protecting the first high voltage transistor from static electricity;
The breakdown voltage of the protection diode is set to a value between the breakdown voltage of the first high breakdown voltage transistor and the operating voltage of the circuit including the first high breakdown voltage transistor.

  According to the semiconductor device manufacturing method of the above embodiment, the breakdown voltage of the protection diode is set to a value between the breakdown voltage of the first high breakdown voltage transistor and the operating voltage of the circuit including the first high breakdown voltage transistor. The surge current can be prevented from flowing inside, and the circuit can be protected.

  Note that the adjustment of the breakdown voltage of the protection diode is performed, for example, in the direction parallel to the surface of the semiconductor substrate, the distance between the end of the high concentration region on the surface of the inversion prevention region of the high breakdown voltage transistor and the high concentration region. This can be done by changing

In one embodiment of a semiconductor device or a manufacturing method thereof,
The breakdown voltage of the low breakdown voltage transistor is in the range of 1.8V to 5V,
The breakdown voltage of the first high breakdown voltage transistor is in the range of 10V to 30V.

In one embodiment of a semiconductor device or a manufacturing method thereof,
The element isolation region of the first high breakdown voltage transistor is formed by a LOCOS (silicon local oxidation) method or an STI (shallow groove type element isolation) method and has a film thickness in the range of 300 nm to 1.0 μm.

In one embodiment of a semiconductor device or a manufacturing method thereof,
The drift region of the second high voltage transistor relaxes the electric field,
The third high voltage transistor is an LD (lateral diffusion) MOS transistor,
The fourth high breakdown voltage transistor is a floating logic transistor.

  According to the semiconductor device of the present invention, impurities are implanted below the active region of the low breakdown voltage transistor and the element isolation region of the low breakdown voltage transistor so that the impurity concentration is higher than the impurity concentration of the active region of the high breakdown voltage transistor. In addition, an inversion prevention region having an impurity concentration higher than the impurity concentration of the active region of the high breakdown voltage transistor is formed under the element isolation region of the high breakdown voltage transistor. Impurity implantation for the high breakdown voltage transistor can be performed simultaneously.

  Therefore, the number of manufacturing steps of the semiconductor device can be reduced, the manufacturing steps can be simplified, and the manufacturing cost can be reduced.

  In addition, the semiconductor device of the present invention can flexibly meet the specifications of the breakdown voltage of the low breakdown voltage transistor and the high breakdown voltage transistor.

  According to the semiconductor device of the present invention, the impurity in the active region of the first high breakdown voltage transistor is provided below the active region of the low breakdown voltage transistor and the element isolation region of the low breakdown voltage transistor by one of the plurality of impurity implantations. An inversion prevention region having an impurity concentration higher than the impurity concentration of the active region of the first high breakdown voltage transistor is implanted below the element isolation region of the first high breakdown voltage transistor. Therefore, the impurity implantation for the low breakdown voltage transistor and the impurity implantation for the high breakdown voltage transistor can be performed simultaneously.

  Therefore, the number of manufacturing steps of the semiconductor device can be reduced, the manufacturing steps can be simplified, and the manufacturing cost can be reduced.

  In addition, the characteristics of the low breakdown voltage transistor can be controlled without affecting the characteristics of the first high breakdown voltage transistor by another one of the plurality of impurity implantations.

  In addition, the semiconductor device manufacturing method of the present invention can flexibly cope with the breakdown voltage specifications of the low breakdown voltage transistor and the first high breakdown voltage transistor.

(First embodiment)
A method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described below with reference to FIGS. 1A to 1L. 1A to 1L, the low breakdown voltage transistor region is a region for forming the low breakdown voltage NMOS (N-channel metal oxide semiconductor) transistor 100A of FIG. 1L, and the high breakdown voltage transistor region is the high breakdown voltage transistor region of FIG. This is a region for forming the breakdown voltage NMOS transistor 100B. The low voltage NMOS transistor 100A is an example of a low voltage transistor, and the high voltage NMOS transistor 100B is an example of a first high voltage transistor.

  When manufacturing the semiconductor device, first, as shown in FIG. 1A, element isolation regions 102A and 102B are formed on a P-type semiconductor substrate 101 by using a well-known LOCOS method or STI method to a depth of 0.3 μm to 1 μm. Formed at 0.0 μm. The element isolation region 102A is an example of an element isolation region of a low breakdown voltage transistor. The element isolation region 102B is an example of an element isolation region of the first high breakdown voltage transistor.

  Next, as shown in FIG. 1B, a sacrificial oxide film 103 is formed with a thickness of 10 nm to 30 nm on the P-type semiconductor substrate 101, and then a resist mask 104 is formed so that the high breakdown voltage transistor region is exposed.

  Subsequently, ion implantation of P-type impurities and heat treatment are performed on the high breakdown voltage transistor region to form a P-type well region 105. In the formation of the well region 105, for example, boron ions are implanted into the P-type semiconductor substrate 101. Note that a part of the well region 105 is an example of an active region of a high voltage transistor or an example of an active region of a first high voltage transistor.

  Next, after removing the sacrificial oxide film 103, the surface of the P-type semiconductor substrate 101 is thermally oxidized in an oxygen atmosphere at 850 ° C. to 950 ° C., and as shown in FIG. 1C, a gate having a thickness of 30 nm to 50 nm. An oxide film 106 is formed. The gate oxide film 106 may be formed by a CVD (chemical vapor deposition) method. In place of the gate oxide film 106, a dielectric film formed by a CVD method may be used. Part of the gate oxide film 106 becomes an example of the gate insulating film of the first high breakdown voltage transistor through a process described later.

Next, as shown in FIG. 1D, a resist mask 107 is formed on the gate oxide film 106, and phosphorus ions, which are examples of N-type impurities, are implanted at a dose of 5.0 × 10 ¹² ions / cm ^2. The well region 105 is implanted with energy of 100 KeV. As a result, an N-type drift region 108 is formed in the well region 105. Needless to say, the impurity implantation for forming the drift region 108 can be changed according to the breakdown voltage specification of the high breakdown voltage NMOS transistor.

Next, after removing the resist mask 107, a resist mask 109 is formed on the gate oxide film 106 by photolithography as shown in FIG. 1E. At this time, the distance H ₁ between the end face of the resist mask 109 and the end of the drift region 108 on the element isolation region 102B side on the surface of the P-type semiconductor substrate 101 is 0.5 μm or more.

Subsequently, boron ions, which are an example of P-type impurities, are implanted a plurality of times using the resist mask 109. That is, so-called multistage implantation of the boron ions is performed. As a result, a P-type well region 110 is formed in the low breakdown voltage transistor region, and a P-type inversion prevention region 111 is formed under the element isolation region 102B. At this time, since the distance H ₁ is equal to or greater than 0.5 [mu] m, even if a plurality of times implantation of boron ions, a negative effect on junction breakdown in the high voltage transistor region beyond.

  Impurities are implanted into the lower portion of the well region 110 (the portion opposite to the gate oxide film 106, that is, the bottom) so that the impurity concentration is higher than the impurity concentration of the well region 105, and The impurity concentration is higher than the impurity concentration of the well region 105.

More specifically, the element isolation region 102A, if the film thickness of 102B is 350 nm, the ion species boron, at ^{7 × 10 12 ions / cm 2} , 20KeV at ^{1.5 × 10 13 ions / cm 2} , 100KeV at 200KeV By performing three-stage implantation of about 5 × 10 ¹² ions / cm ² , the inversion voltage exceeds 30 V without affecting the junction breakdown voltage (> 25 V) of the high breakdown voltage portion, and the threshold voltage of the low breakdown voltage NMOS transistor 100 A is increased. Control is possible.

  In the implantation of boron ions, it goes without saying that the implantation with high energy adjusts the implantation energy and the implantation amount in accordance with the film thickness of the element isolation region 102B and the desired breakdown voltage.

  Next, after removing the resist mask 107 in the high breakdown voltage transistor region and the gate oxide film 106 in the low breakdown voltage transistor region, the surface of the low breakdown voltage transistor region is thermally oxidized in an oxygen atmosphere at 800 to 900 ° C. As shown in FIG. 1F, a gate oxide film 112 having a film thickness of 3 nm to 15 nm is formed on the low breakdown voltage transistor region. The gate oxide film 112 may be formed by a CVD method. In place of the gate oxide film 112, a dielectric film formed by a CVD method may be used. The gate oxide film 112 is an example of a gate insulating film of a low breakdown voltage transistor.

  Next, a polysilicon layer is formed on the gate oxide films 106 and 112 by a CVD method, and this polysilicon layer is patterned, thereby forming a polysilicon layer 113A on the gate oxide film 106 as shown in FIG. 1G. And a polysilicon layer 113B is formed on the gate insulating film 106. Both the polysilicon layers 113A and 113B have a thickness of 200 nm. The polysilicon layer 113A is an example of a gate electrode of a low breakdown voltage transistor, and the polysilicon layer 113B is an example of a gate electrode of a first high breakdown voltage transistor.

  Next, as shown in FIG. 1H, a resist mask 114 is formed in the high breakdown voltage transistor region using photolithography, and then LDD implantation is performed in the low breakdown voltage transistor region, thereby forming an LDD (lightly doped drain) region 115. Form. In this LDD implantation, phosphorus ions are implanted into the well region 110.

  Next, after depositing an oxide film on the entire surface by the 100 nm CDV method, gate electrode sidewalls 116A and 116B are formed on the side surfaces of the polysilicon layers 113A and 113B, as shown in FIG. .

Next, after implanting arsenic ions in a predetermined pattern at a dose of 3.0 × 10 ¹⁵ ions / cm ² and an energy of 40 KeV, heat treatment is performed in an inert gas atmosphere at 700 to 850 ° C., or RTA (rapid heat treatment) method or the like is performed. Thereby, the defect recovery by the arsenic ion implantation and the activation of the arsenic ions are performed, and the source / drain regions 117A and 117B shown in FIG. 1J are formed. At this time, the polysilicon layers 113A and 113B and the source / drain regions 117A and 117B are silicided by a known technique to reduce the resistance of the polysilicon layers 113A and 113B and the source / drain regions 117A and 117B. Also good. The source / drain region 117A is an example of a source region and a drain region of a low breakdown voltage transistor. The source / drain region 117B is an example of a source region and a drain region of the first high breakdown voltage transistor.

  Next, for example, P-SiO is deposited by 1000 nm by the CVD method, and the P-SiO is planarized by the CMP method. Thereby, as shown in FIG. 1K, an interlayer insulating film 118 covering the gate oxide films 106 and 112 and the polysilicon layers 113A and 113B is formed.

  Next, as shown in FIG. 1L, when a contact hole 119 is formed in the interlayer insulating film 118 and an electrode 120 is formed on the interlayer insulating film 118 formed with the contact hole 119, a low breakdown voltage NMOS is formed in the low breakdown voltage transistor region. A transistor 100A is obtained, and a high voltage NMOS transistor 100B is obtained in the high voltage transistor region.

  As described above, since boron ion implantation for forming the inversion prevention region 110 of the high breakdown voltage NMOS transistor 100B is performed a plurality of times, one boron ion implantation among the plurality of times is performed more than other boron ion implantations. By performing with low energy, the characteristics of the low voltage NMOS transistor 100A can be controlled without affecting the characteristics of the high voltage NMOS transistor 100B.

  Further, by performing one boron ion implantation of the plurality of times with higher energy than other boron ion implantations, an inversion prevention region having an impurity concentration higher than that of the well region 105 of the high breakdown voltage NMOS transistor 100B. 111 can be obtained reliably.

  Therefore, the well region 110 of the low breakdown voltage NMOS transistor 100A can also be formed by the step of forming the inversion prevention region 110 of the high breakdown voltage NMOS transistor 100B, so that the number of manufacturing steps can be reduced.

  As a result, the manufacturing process of the semiconductor device in which the low breakdown voltage NMOS transistor 100A and the high breakdown voltage NMOS transistor 100B are mounted together can be simplified, and the manufacturing cost can be reduced.

  Needless to say, the number of the low breakdown voltage NMOS transistors 100A and the high breakdown voltage NMOS transistors 100B may be one, or two or more.

  In the first embodiment, the low breakdown voltage NMOS transistor 100A and the high breakdown voltage NMOS transistor 100B are formed. However, the impurity type is changed in the above-described manufacturing process, and the low breakdown voltage PMOS (P channel metal oxide semiconductor) transistor and the high breakdown voltage PMOS are formed. A transistor may be formed.

  In the first embodiment, the polysilicon layers 113A and 113B are formed after forming the drift region 108. However, the drift region 108 may be formed after forming the polysilicon layers 113A and 113B.

(Second Embodiment)
A method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described below with reference to FIGS. 2A to 2G. 2A to 2G, a low breakdown voltage transistor region is a region for forming a low breakdown voltage NMOS transistor, and a high breakdown voltage transistor region is a region for forming a high breakdown voltage NMOS transistor. The low voltage NMOS transistor is an example of a low voltage transistor, and the high voltage NMOS transistor is an example of a first high voltage transistor.

  When manufacturing the semiconductor device, first, as shown in FIG. 2A, element isolation regions 202A and 202B are formed on a P-type semiconductor substrate 201 by using a well-known LOCOS method or STI method to a depth of 0.3 μm to 1 μm. Formed at 0.0 μm. The element isolation region 202A is an example of an element isolation region of a low breakdown voltage transistor. The element isolation region 202B is an example of an element isolation region of the first high breakdown voltage transistor.

  Next, as shown in FIG. 2B, a sacrificial oxide film 203 is formed with a thickness of 10 nm to 30 nm on the P-type semiconductor substrate 201, and then a resist mask 204 is formed so that the high breakdown voltage transistor region is exposed.

  Subsequently, a P-type well region 205 is formed by performing ion implantation of P-type impurities and heat treatment on the high breakdown voltage transistor region. In the formation of the well region 205, for example, boron ions are implanted into the P-type semiconductor substrate 201. Note that a part of the well region 205 is an example of an active region of the high voltage transistor or an example of an active region of the first high voltage transistor.

  Next, after removing the sacrificial oxide film 203, the surface of the P-type semiconductor substrate 201 is thermally oxidized in an oxygen atmosphere at 850 ° C. to 950 ° C., and as shown in FIG. 2C, a gate having a thickness of 30 nm to 50 nm. An oxide film 206 is formed. The gate oxide film 206 may be formed by a CVD method. In place of the gate oxide film 206, a dielectric film formed by a CVD method may be used. A part of the gate oxide film 206 becomes an example of the gate insulating film of the first high breakdown voltage transistor through a process described later.

Next, as shown in FIG. 2D, a resist mask 207 is formed on the gate oxide film 206, and phosphorus ions, which are an example of N-type impurities, are applied at a dose of 5.0 × 10 ¹² ions / cm ² and energy. Implant into the well region 205 at 100 KeV. As a result, an N-type drift region 208 is formed in the well region 205. Needless to say, the impurity implantation for forming the drift region 208 can be changed according to the breakdown voltage specification of the high breakdown voltage NMOS transistor.

  Next, after removing the resist mask 207 and the gate oxide film 206 in the low breakdown voltage transistor region, the surface of the low breakdown voltage transistor region is thermally oxidized in an oxygen atmosphere at 800 ° C. to 900 ° C., as shown in FIG. 2E. Then, a gate oxide film 212 having a thickness of 3 nm to 15 nm is formed on the low breakdown voltage transistor region. The gate oxide film 212 may be formed by a CVD method. In place of the gate oxide film 212, a dielectric film formed by a CVD method may be used. The gate oxide film 212 is an example of a gate insulating film of a low breakdown voltage transistor.

  Next, a polysilicon layer is formed on the gate oxide films 206 and 212 by the CVD method, and this polysilicon layer is patterned, thereby forming a polysilicon layer 213A on the gate oxide film 206 as shown in FIG. 2F. And a polysilicon layer 213B is formed on the gate insulating film 206. Both the polysilicon layers 213A and 213B have a film thickness of 200 nm. The polysilicon layer 213A is an example of a gate electrode of a low breakdown voltage transistor, and the polysilicon layer 213B is an example of a gate electrode of a first high breakdown voltage transistor.

Next, as shown in FIG. 2G, a resist mask 214 is formed by photolithography in the high breakdown voltage transistor region. At this time, a distance H ₂ between the end face of the resist mask 214 and the end of the drift region 208 on the surface of the P-type semiconductor substrate 201 on the element isolation region 202B side is set to 0.3 μm or more.

Subsequently, boron ions, which are an example of P-type impurities, are implanted a plurality of times using the resist mask 109. That is, so-called multistage implantation of the boron ions is performed. As a result, a P-type well region 210 is formed in the low breakdown voltage transistor region, and a P-type inversion prevention region 211 is formed under the element isolation region 202B. At this time, since the distance H ₂ is equal to or greater than 0.3 [mu] m, even if a plurality of times implantation of boron ions, a negative effect on junction breakdown in the high voltage transistor region beyond.

  Impurities are implanted into the lower portion of the well region 210 (the portion opposite to the gate oxide film 212, that is, the bottom portion) so that the impurity concentration is higher than the impurity concentration of the well region 205. The impurity concentration is higher than the impurity concentration of the well region 205.

More specifically, in the case where the element isolation regions 202A and 202B have a thickness of 350 nm and the polysilicon layers 213A and 213B have a thickness of 200 nm, the ion species boron is set to 1.5 × 10 ¹³ ions / cm ² and 160 KeV at 260 KeV. By performing the steps described later by performing three-stage implantation of 5 × 10 ¹² ions / cm ^{2 at} about 5 × 10 ¹² ions / cm ² at 80 KeV, there is no effect on the junction breakdown voltage (> 25 V) of the high voltage section. The inversion voltage exceeds 30V, and the threshold voltage 0.7V characteristic of the low breakdown voltage NMOS transistor can be ensured.

  Thereafter, the LDD region 215 is formed by performing LDD implantation in the low breakdown voltage transistor region while leaving the resist mask 214 left. In this LDD implantation, for example, phosphorus ions are implanted into the well region 210.

  Next, after annealing is performed to recover damage caused by ion implantation in the gate oxide films 206 and 212, the same steps as those in FIGS. 1I to 1L of the first embodiment are performed to obtain a low breakdown voltage transistor region. In addition, a low breakdown voltage NMOS transistor is formed, and a high breakdown voltage NMOS transistor is formed in the high breakdown voltage transistor region.

  As described above, the register mask 214 is used to form the inversion prevention region 211 and the well region 210, and the register mask 214 is also used to form the LDD region 215. Therefore, a mask is formed only for forming the LDD region 215. You don't have to.

  Therefore, since the number of manufacturing processes can be reduced by one as compared with the first embodiment, the manufacturing process of the semiconductor device can be further simplified, and the manufacturing cost can be further reduced.

  Since the well region 210, the inversion prevention region 211, and the LDD region 215 are formed after the heat treatment for forming the gate oxide film 212, the well region 210, the inversion prevention region 211, and the LDD region 215 are formed in the well region 210, the inversion prevention region 211, and the LDD region 215. Not affected by heat treatment.

  Therefore, it is possible to prevent a problem caused by thermal diffusion of impurities contained in the well region 210, the inversion prevention region 211, and the LDD region 215.

  In the second embodiment, the polysilicon layers 213A and 213B are formed after the drift region 208 is formed. However, the drift region 208 may be formed after the polysilicon layers 213A and 213B are formed.

(Third embodiment)
A method for manufacturing a semiconductor device according to the third embodiment of the present invention will be described below with reference to FIGS. 3A to 3G. 3A to 3G, the low breakdown voltage transistor region is a region for forming the low breakdown voltage NMOS transistor 300A of FIG. 3G, and the high breakdown voltage NMOS transistor region is for forming the high breakdown voltage NMOS transistor 300B of FIG. 3G. The region, the high breakdown voltage PMOS transistor region is a region for forming the high breakdown voltage PMOS transistor 300C of FIG. 3G, the LDMOS transistor region is the region for forming the LDMOS transistor 300D of FIG. 3G, and the floating logic NMOS transistor region is shown in FIG. This is a region for forming a 3G floating logic NMOS transistor 300E. The low voltage NMOS transistor 300A is an example of a low voltage transistor, the high voltage NMOS transistor 300B is an example of a first high voltage transistor, the high voltage PMOS transistor 300C is an example of a second high voltage transistor, and the LDMOS transistor 300D is a third high voltage transistor. An example of the transistor, the floating logic NMOS transistor 300E, is an example of a fourth high breakdown voltage transistor. Hereinafter, the floating logic NMOS transistor is referred to as a “FLNMOS transistor”.

  When manufacturing the semiconductor device, first, as shown in FIG. 3A, element isolation regions 302A to 302E are formed on a P-type semiconductor substrate 301 by using a well-known LOCOS method or STI method to a depth of 0.3 μm to 1 μm. Formed at 0.0 μm. The element isolation region 302A is an example of an element isolation region of a low breakdown voltage transistor. The element isolation region 302B is an example of an element isolation region of the first high breakdown voltage transistor.

  Next, as shown in FIG. 3B, a sacrificial oxide film 303 is formed to a thickness of 10 nm to 30 nm on the P-type semiconductor substrate 301, and then a resist mask 304 is formed so that the high breakdown voltage NMOS transistor region is exposed.

  Subsequently, a P-type well region 305 is formed by performing ion implantation of P-type impurities and heat treatment on the high breakdown voltage NMOS transistor region. In the formation of the well region 305, for example, boron ions are implanted into the P-type semiconductor substrate 301. Note that a part of the well region 305 is an example of an active region of a high voltage transistor or an example of an active region of a first high voltage transistor.

  Next, after removing the resist mask 304, as shown in FIG. 3C, a resist mask 304 is formed so that the high voltage PMOS transistor region, the LDMOS transistor region, and the FLNMOS transistor region are exposed.

  Subsequently, ion implantation and heat treatment of N-type impurities are performed on the high breakdown voltage PMOS transistor region, LDMOS transistor region, and FLNMOS transistor region, so that an N-type well region 331, an N-type drift region 332, and an N-type drift region 332 A well region 333 is formed.

  Next, after removing the resist mask 304 and the sacrificial oxide film 303, the surface of the P-type semiconductor substrate 301 is thermally oxidized in an oxygen atmosphere at 850 ° C. to 950 ° C., and as shown in FIG. A gate oxide film 306 of ˜50 nm is formed. The gate oxide film 306 may be formed by a CVD method. In place of the gate oxide film 306, a dielectric film formed by a CVD method may be used. A part of the gate oxide film 306 becomes an example of the gate insulating film of the first high breakdown voltage transistor through a process described later.

Next, as shown in FIG. 3E, a resist mask 307 is formed on the gate oxide film 306, and phosphorus ions which are an example of N-type impurities are energized at a dose of 5.0 × 10 ¹² ions / cm ² . Implant into the well region 305 at 100 KeV. As a result, a drift region 308 for a high breakdown voltage NMOS transistor is formed in the well region 305.

  Next, after removing the resist mask 307, as shown in FIG. 3F, a resist mask 309 is formed on the gate oxide film 306 by photolithography. At this time, the distance between the end face of the resist mask 309 and the end of the drift region 308 on the element isolation region 302B side on the surface of the P-type semiconductor substrate 301 is 0.5 μm or more. That is, the high-breakdown-voltage NMOS transistor region in the resist mask 309 is formed under the same conditions as the resist mask 109 of the first embodiment. The resist mask 309 covers only part of the high voltage PMOS transistor 300C and the LDMOS transistor 300D.

  Subsequently, using the resist mask 309, boron ions, which are an example of P-type impurities, are implanted a plurality of times. That is, so-called multistage implantation of the boron ions is performed. As a result, a P-type well region 310 is formed in the low breakdown voltage transistor region, a P-type inversion prevention region 311 is formed in the high breakdown voltage NMOS transistor region, a P-type drift region 334 is formed in the high breakdown voltage PMOS transistor region, and a P-type well is formed in the LDMOS transistor region. A P-type well region 336 is formed in the region 335 and the FLNMOS transistor region. A part of the well region 310 is an example of an active region of a low voltage transistor, a drift region 334 is an example of a drift region of a second high voltage transistor, and a part of the well region 335 is a well region of a third high voltage transistor. For example, the well region 336 is an example of a well region of the fourth high breakdown voltage transistor.

  Impurities are implanted below the well region 310 (the portion opposite to the gate oxide film 306, ie, the bottom) so that the impurity concentration is higher than the impurity concentration of the well region 305, and the inversion prevention region. The impurity concentration of 311 is higher than the impurity concentration of the well region 305.

  Next, the same steps as in FIGS. 1I to 1L of the first embodiment are performed, and as shown in FIG. 3G, the low breakdown voltage NMOS transistor 300A is formed in the low breakdown voltage transistor region and the high breakdown voltage NMOS transistor is formed in the high breakdown voltage NMOS transistor region. 300B, a high voltage PMOS transistor 300C is formed in the high voltage PMOS transistor region, an LDMOS transistor 300D is formed in the LDMOS transistor region, and a floating logic NMOS transistor 300E is formed in the floating logic NMOS transistor region.

  In FIG. 3G, 312 is a gate oxide film, 313 is a polysilicon layer, 315 is an LDD region, 316 is a gate electrode sidewall, 317 and 337 are source / drain regions, 318 is an interlayer insulating film, 319 is a contact hole, 320 is an electrode. The gate oxide film 312 is formed to be thinner than the gate oxide film 306.

  As apparent from the above, even when a semiconductor device including the low breakdown voltage NMOS transistor 300A, the high breakdown voltage NMOS transistor 300B, the high breakdown voltage PMOS transistor 300C, the LDMOS transistor 300D, and the floating logic NMOS transistor 300E is manufactured, As in the first embodiment, the manufacturing process of the semiconductor device can be simplified and the manufacturing cost can be reduced.

  Further, if the drift region 308 is formed in the step of forming the well region 310, the inversion prevention region 311, the drift region 334, the well region 335, and the well region 336, the number of manufacturing steps of the semiconductor device can be further reduced. it can.

  FIG. 4A shows a schematic cross-sectional view of the main part of the semiconductor device of the first comparative example (shown for convenience of explanation, not the conventional example). FIG. 4B is a schematic cross-sectional view of the main part of the semiconductor device of the first embodiment.

  The semiconductor device manufacturing method of the first comparative example differs from the semiconductor device manufacturing method of the first embodiment only in that the inversion prevention region is formed by one impurity implantation.

  FIG. 5A shows the impurity concentration along dotted lines (1) to (3) in FIG. 4A. FIG. 5B shows the impurity concentration along dotted lines (1 ′) to (3 ′) in FIG. 4B.

  As shown in FIG. 5A, in the low breakdown voltage transistor region of the semiconductor device of the first comparative example, the impurity concentration is high only in the vicinity of the substrate surface of the active region. In the high breakdown voltage transistor region of the semiconductor device of the first comparative example, the impurity concentration of only a part of the element isolation region is higher than the impurity concentration of the active region.

  On the other hand, as shown in FIG. 5B, in the low breakdown voltage transistor region of the semiconductor device of the first embodiment, the impurity concentration is high up to a deep portion of the active region. In the high breakdown voltage transistor region of the semiconductor device of the first embodiment, the total impurity concentration of the element isolation region is higher than the impurity concentration of the active region.

  FIG. 6 shows the relationship between the distance H from the active region to the inversion preventing region and the junction breakdown voltage in the high breakdown voltage transistor region of the semiconductor device of the present invention.

  As is apparent from FIG. 6, the junction breakdown voltage can be increased by increasing the distance H.

  FIG. 7 shows the relationship between the element isolation concentration (impurity concentration of the inversion prevention region), the junction breakdown voltage, and the inversion voltage of the semiconductor device of the second comparative example (shown for convenience of explanation and not the conventional example). Show.

  When the concentration under element isolation is increased, the inversion voltage can be increased, but the junction breakdown voltage is lowered.

  FIG. 8 shows the relationship between the impurity concentration of the inversion prevention region 111 of the semiconductor device of the first embodiment, the junction breakdown voltage, and the inversion voltage.

  If the impurity concentration of the first inversion prevention region 111 is good, a good inversion voltage and junction breakdown voltage can be obtained.

  In the semiconductor device manufacturing methods of the first to third embodiments, as shown in FIG. 9, a protection diode 901 for protecting the high voltage system circuit 900 from static electricity may be formed. The protective diode 901 is electrically connected in parallel to the high voltage system circuit 900. The high voltage system circuit 900 is a circuit including the semiconductor devices of the first to third embodiments.

  When the protection diode 901 is formed, the distance H is set so that the breakdown voltage of the protection diode 901 is a value between the breakdown voltage of the transistor used in the high breakdown voltage circuit 900 and the operating voltage of the high breakdown voltage circuit 900. Is preferred.

  The present invention is not limited to the first to third embodiments described above, and can take various embodiments. For example, the first to third embodiments described above may be combined as appropriate to form an embodiment of the present invention.

FIG. 1A is a schematic cross-sectional view of one manufacturing process of the semiconductor device of the first embodiment of the present invention. FIG. 1B is a schematic cross-sectional view of one manufacturing process of the semiconductor device of the first embodiment of the present invention. FIG. 1C is a schematic cross-sectional view of one manufacturing process of the semiconductor device of the first embodiment of the present invention. FIG. 1D is a schematic cross-sectional view of one manufacturing process of the semiconductor device of the first embodiment of the present invention. FIG. 1E is a schematic cross-sectional view of one manufacturing process of the semiconductor device of the first embodiment of the present invention. FIG. 1F is a schematic cross-sectional view of one manufacturing process of the semiconductor device of the first embodiment of the present invention. FIG. 1G is a schematic cross-sectional view of one manufacturing process of the semiconductor device of the first embodiment of the present invention. FIG. 1H is a schematic cross-sectional view of one manufacturing process of the semiconductor device of the first embodiment of the present invention. FIG. 1I is a schematic cross-sectional view of one manufacturing process of the semiconductor device of the first embodiment of the present invention. FIG. 1J is a schematic cross-sectional view of one manufacturing process of the semiconductor device of the first embodiment of the present invention. FIG. 1K is a schematic cross-sectional view of one manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG. 1L is a schematic cross-sectional view of one manufacturing process of the semiconductor device of the first embodiment of the present invention. FIG. 2A is a schematic cross-sectional view of one manufacturing process of the semiconductor device of the second embodiment of the present invention. FIG. 2B is a schematic cross-sectional view of one manufacturing process of the semiconductor device of the second embodiment of the present invention. FIG. 2C is a schematic cross-sectional view of one manufacturing process of the semiconductor device of the second embodiment of the present invention. FIG. 2D is a schematic cross-sectional view of one manufacturing process of the semiconductor device of the second embodiment of the present invention. FIG. 2E is a schematic cross-sectional view of one manufacturing process of the semiconductor device of the second embodiment of the present invention. FIG. 2F is a schematic cross-sectional view of one manufacturing process of the semiconductor device of the second embodiment of the present invention. FIG. 2G is a schematic cross-sectional view of one manufacturing process of the semiconductor device of the second embodiment of the present invention. FIG. 3A is a schematic cross-sectional view of one manufacturing process of the semiconductor device of the third embodiment of the present invention. FIG. 3B is a schematic cross-sectional view of one manufacturing process of the semiconductor device of the third embodiment of the present invention. FIG. 3C is a schematic cross-sectional view of one manufacturing process of the semiconductor device of the third embodiment of the present invention. FIG. 3D is a schematic cross-sectional view of one manufacturing process of the semiconductor device of the third embodiment of the present invention. FIG. 3E is a schematic cross-sectional view of one manufacturing process of the semiconductor device of the third embodiment of the present invention. FIG. 3F is a schematic cross-sectional view of one manufacturing process of the semiconductor device of the third embodiment of the present invention. FIG. 3G is a schematic cross-sectional view of one manufacturing process of the semiconductor device of the third embodiment of the present invention. FIG. 4A is a schematic cross-sectional view of the main part of the semiconductor device of the first comparative example. FIG. 4B is a schematic cross-sectional view of a main part of the semiconductor device of the first embodiment. FIG. 5A is a graph of impurity concentration along dotted lines (1) to (3) in FIG. 4A. FIG. 5B is a graph of impurity concentration along dotted lines (1 ') to (3') in FIG. 4B. FIG. 6 is a graph showing the relationship between the distance from the active region to the inversion prevention region and the junction breakdown voltage in the high breakdown voltage transistor region of the semiconductor device of the present invention. FIG. 7 is a graph showing the relationship between the element isolation concentration, the junction breakdown voltage, and the inversion voltage of the semiconductor device of the second comparative example. FIG. 8 is a graph showing the relationship between the impurity concentration of the inversion preventing region, the junction breakdown voltage, and the inversion voltage of the semiconductor device of the first embodiment. FIG. 9 is a circuit diagram for explaining a modification of the semiconductor device of the first to third embodiments.

Explanation of symbols

100A, 300A Low breakdown voltage NMOS transistors 100B, 300B High breakdown voltage NMOS transistors 101, 201, 301 P-type semiconductor substrates 102A, 102B, 202A, 202B, 302A, 302B, 302C, 302D,
106, 112, 206, 212, 306, 312 Gate oxide films 113A, 113B, 213A, 213B, 313 Polysilicon layers 117A, 117B, 317, 337 Source / drain regions 105, 205, 305, 310, 335, 336 Well regions 215 LDD region 300C high voltage PMOS transistor 300D LDMOS transistor 300E floating logic NMOS transistor 302E element isolation region 334 drift region

Claims (9)

A semiconductor device in which a plurality of transistors having different operating voltages are formed on a semiconductor substrate,
Each of the above transistors
An element isolation region formed on the surface of the semiconductor substrate;
An active region partitioned by the element isolation region;
A source region formed in the active region;
A drain region formed in the active region;
A gate insulating film formed on a region between the source region and the drain region;
A gate electrode formed on the gate insulating film,
Among the plurality of transistors, there are a low breakdown voltage transistor and a high breakdown voltage transistor whose breakdown voltage is higher than the breakdown voltage of the low breakdown voltage transistor,
Impurities are implanted below the active region of the low breakdown voltage transistor and the element isolation region of the low breakdown voltage transistor so that the impurity concentration is higher than the impurity concentration of the active region of the high breakdown voltage transistor, The semiconductor device is characterized in that an inversion prevention region having an impurity concentration higher than that of the active region of the high breakdown voltage transistor is formed under the element isolation region of the high breakdown voltage transistor. A method of manufacturing a semiconductor device in which a plurality of transistors having different operating voltages are formed on a semiconductor substrate,
Each of the above transistors
An element isolation region formed on the surface of the semiconductor substrate;
An active region partitioned by the element isolation region;
A source region formed in the active region;
A drain region formed in the active region;
A gate insulating film formed on a region between the source region and the drain region;
A gate electrode formed on the gate insulating film,
Among the plurality of transistors, there are a low breakdown voltage transistor and a first high breakdown voltage transistor whose breakdown voltage is higher than the breakdown voltage of the low breakdown voltage transistor,
Impurity implantation is performed a plurality of times, and the impurity concentration is higher under the active region of the low breakdown voltage transistor and the element isolation region of the low breakdown voltage transistor than the impurity concentration of the active region of the first high breakdown voltage transistor. An inversion prevention region having an impurity concentration higher than the impurity concentration of the active region of the first high breakdown voltage transistor is formed under the element isolation region of the first high breakdown voltage transistor. A method for manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 2,
The method of manufacturing a semiconductor device, wherein the gate insulating film of the low breakdown voltage transistor is thinner than the gate insulating film of the first high breakdown voltage transistor. In the manufacturing method of the semiconductor device according to claim 2 or 3,
The method of manufacturing a semiconductor device, wherein the inversion prevention region of the first high breakdown voltage transistor has an impurity concentration of 5 to 20 times higher than that of the active region. In the manufacturing method of the semiconductor device according to any one of claims 2 to 4,
A method of manufacturing a semiconductor device, wherein the inversion prevention region of the first high breakdown voltage transistor and the active region of the low breakdown voltage transistor are formed with the same mask. In the manufacturing method of the semiconductor device according to any one of claims 2 to 5,
The low breakdown voltage transistor includes a lightly doped drain region formed in the active region of the low breakdown voltage transistor and having a lower impurity concentration than the source region and the drain region,
A method of manufacturing a semiconductor device, wherein the inversion prevention region of the first high breakdown voltage transistor and the lightly doped drain region of the low breakdown voltage transistor are formed using the same mask. In the manufacturing method of the semiconductor device according to any one of claims 2 to 6,
Among the plurality of transistors, there is a second high breakdown voltage transistor having a higher breakdown voltage than the low breakdown voltage transistor,
The second high voltage transistor includes a drift region formed in the active region of the second high voltage transistor,
The active device of the low voltage transistor, the inversion prevention region of the first high voltage transistor, and the drift region of the second high voltage transistor are formed using the same mask. Manufacturing method. In the manufacturing method of the semiconductor device according to any one of claims 2 to 7,
Among the plurality of transistors, there are second, third, and fourth high breakdown voltage transistors having a breakdown voltage higher than that of the low breakdown voltage transistor,
The second high voltage transistor includes a drift region formed in the active region of the second high voltage transistor,
The active region of the low-voltage transistor, the inversion prevention region of the first high-voltage transistor, the drift region of the second high-voltage transistor, the active region of the third high-voltage transistor, and the fourth A method for manufacturing a semiconductor device, wherein the active region of a high voltage transistor is formed using the same mask. In the manufacturing method of the semiconductor device according to any one of claims 2 to 8,
Forming a protective diode for protecting the first high voltage transistor from static electricity;
A method of manufacturing a semiconductor device, characterized in that a breakdown voltage of the protection diode is set to a value between a breakdown voltage of the first high breakdown voltage transistor and an operating voltage of a circuit including the first high breakdown voltage transistor.

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