CN105845733A - P-type dynamic threshold transistor, preparation method and method for increasing operating voltage - Google Patents
P-type dynamic threshold transistor, preparation method and method for increasing operating voltage Download PDFInfo
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- CN105845733A CN105845733A CN201610236397.3A CN201610236397A CN105845733A CN 105845733 A CN105845733 A CN 105845733A CN 201610236397 A CN201610236397 A CN 201610236397A CN 105845733 A CN105845733 A CN 105845733A
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- 238000000034 method Methods 0.000 title claims abstract description 19
- 238000002360 preparation method Methods 0.000 title claims abstract description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 3
- 239000004065 semiconductor Substances 0.000 claims description 16
- 229920005591 polysilicon Polymers 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 239000013078 crystal Substances 0.000 claims 1
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000012212 insulator Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/783—Field effect transistors with field effect produced by an insulated gate comprising a gate to body connection, i.e. bulk dynamic threshold voltage MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Abstract
The invention provides a P-type dynamic threshold transistor, a preparation method and a method for increasing operating voltage. The P-type dynamic threshold transistor comprises a substrate structure, a PMOS device and a PN junction device, wherein an N region of the PN junction device is connected with a body contact region of the PMOS device, and a P region of the PN junction device is connected with a gate of the PMOS device. According to the preparation method, twice P-type heavy doping are carried out in an N-type intrinsic region to form source and drain regions of the PMOS device and the PN junction device, and N-type heavy doping is carried out to form the body contact region of the PMOS device; a gate oxidation layer and a polycrystalline silicon layer are sequentially formed on a channel region, the polycrystalline silicon layer is subjected to P-type heavy doping to form the gate; and the gate of the PMOS device is connected with the P region of the PN junction device through a through hole and metal. According to the P-type dynamic threshold transistor, the preparation method and the method for increasing the operating voltage, a reverse-biased junction is formed on a gate body connection passage, thus voltage of the body contact region is increased, threshold voltage is decreased, driving current is increased, the increase of the operating voltage is achieved, and the application value of the P-type dynamic threshold transistor in the field of low-power-consumption circuit design is extended.
Description
Technical field
The present invention relates to technical field of semiconductor device, particularly relate to a kind of p-type dynamic threshold transistor, preparation method and carry
The method of high working voltage.
Background technology
At whole semicon industry during the development of new generation of semiconductor device, chip manufacturer is faced with stern challenge.
Concretely, produce high performance chips manufacturer's facing challenges to speed faster, temperature lower chip design need
Ask.For the chip manufacturer of Mobile solution it is desirable that the less semiconductor device of power consumption.In order to tackle these challenges, mostly
The leading device manufacturer of number all have selected silicon-on-insulator (SOI, the Silicon On with low-power consumption advantage at high speed
Insulator) technology.
The body contact area of silicon-on-insulator can with floating, or draw receive on a fixed potential position.When body contact area voltage liter
Gao Shi, device threshold voltage reduces, can effectively increase large-drive-current.SOI dynamic threshold transistor (DTMOS, Dynamic
Threshold Metal Oxide Semiconductor) it is that body contact area and grid are connected, it is achieved the dynamic adjustment of threshold voltage.
The type device threshold dynamically changeable, when device is opened, body contact area voltage raises, and causes threshold value to reduce, and electric current drives energy
Power improves, and when device is off state, has higher threshold voltage, thus reduces leakage current.But body contact area with
The PN junction that source, drain region are formed, if grid voltage is higher than this PN junction conducting voltage, causes electric current to increase suddenly, causes power consumption
Increase.Due to the existence of this parasitic diode, cause dynamic threshold transistor running voltage relatively low, typically at below 0.7V,
Therefore can not share supply voltage with traditional transistor, also limit the application of dynamic threshold transistor.
Radio-frequency technique is to power consumption and performance rdativery sensitive, although SOI DTMOS transistor can provide relatively low power consumption and higher
Performance, but its running voltage is relatively low, for running voltage higher time can not directly use.
Therefore, the running voltage how improving SOI dynamic threshold transistor has become those skilled in the art's problem demanding prompt solution
One of.
Summary of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to provide a kind of p-type dynamic threshold transistor, preparation
Method and the method improving running voltage are low for solving the running voltage of SOI dynamic threshold transistor in prior art, it is impossible to
Share supply voltage with traditional transistor, to such an extent as to limited the problems such as application.
For achieving the above object and other relevant purposes, the present invention provides a kind of p-type dynamic threshold transistor, and described p-type is dynamic
Threshold transistor at least includes:
Substrat structure, is positioned at the PMOS device on described substrat structure and PN junction device；
The N district of described PN junction device is connected with the body contact area of described PMOS device, the P district of described PN junction device and institute
The grid stating PMOS device connect；Wherein, the body contact area of described PMOS device is N-type heavily doped region, described PN junction device
The N district of part is N-type intrinsic region, and the P district of described PN junction device is p-type heavily doped region.
Preferably, described substrat structure at least includes semiconductor base and is positioned at the oxide layer on described semiconductor base.
Preferably, described PMOS device is n PMOS in parallel, and n is the natural number more than or equal to 1.
It is highly preferred that n the PN junction diode that the PMOS that described PN junction device is in parallel with n connects one to one.
It is highly preferred that described PN junction device is 1 PN junction diode.
Preferably, described PMOS device also include the channel region being positioned on described substrat structure, be positioned at described channel region and grid it
Between gate oxide, and be positioned at source region and the drain region of channel region both sides；Wherein, described channel region is N-type intrinsic region, described
Grid are p-type heavily doped region, and described source region and described drain region are p-type heavily doped region.
Preferably, described PMOS device and described PN junction device are connected by through hole and metal.
For achieving the above object and other relevant purposes, the present invention also provides for the preparation method of a kind of p-type dynamic threshold transistor,
The preparation method of described p-type dynamic threshold transistor at least includes:
One substrat structure is provided, described substrat structure is prepared N-type intrinsic region；
Twice p-type heavy doping is carried out to form the source of PMOS device, drain region and PN junction device respectively in described N-type intrinsic region
Part, carries out N-type heavy doping to form the body contact area of described PMOS device, described PN junction device in described N-type intrinsic region
The N district of part is connected with the body contact area of described PMOS device, wherein, is ditch between the source of described PMOS device, drain region
Road district；
Above the channel region of described PMOS device, form gate oxide, described gate oxide forms polysilicon layer, to institute
State polysilicon layer and carry out p-type heavy doping to form the grid of described PMOS device；
The P district of the grid of described PMOS device with described PN junction device is connected with metal by through hole.
For achieving the above object and other relevant purposes, the present invention also provides for a kind of improving p-type dynamic threshold transistor running voltage
Method, it is characterised in that the method for described raising p-type dynamic threshold transistor running voltage at least includes:
Connecting PN junction device between the grid and body contact area of PMOS device, the anode of described PN junction device connects described
The grid of PMOS device, the negative electrode of described PN junction device connects the body contact area of described PMOS device, so that described PMOS
The body contact area voltage of device raises, and then reduces threshold voltage, improves driving electric current, it is achieved the raising of running voltage.
As it has been described above, the p-type dynamic threshold transistor of the present invention, preparation method and the method for raising running voltage, have following
Beneficial effect:
The method of the p-type dynamic threshold transistor of the present invention, preparation method and raising running voltage is by grid body connecting path
Form a reverse biased pn junction, carry out lifting body contact area voltage, reduce threshold voltage, raising driving electric current, it is achieved running voltage
Raising, extend the p-type dynamic threshold transistor using value at low consumption circuit design field.
Accompanying drawing explanation
Fig. 1 is shown as the schematic top plan view of the p-type dynamic threshold transistor domain of the embodiment of the present invention one and embodiment three.
Fig. 2 is shown as the AA ' of the p-type dynamic threshold transistor domain of the embodiment of the present invention one to cross-sectional schematic.
Fig. 3 is shown as many finger-cross structure domain of the p-type dynamic threshold transistor of the embodiment of the present invention two.
Fig. 4 is shown as the principle schematic of the method for the raising p-type dynamic threshold transistor running voltage of the embodiment of the present invention four.
Element numbers explanation
1 p-type dynamic threshold transistor
11 substrat structures
111 semiconductor bases
112 oxide layers
12 PMOS device
121 channel regions
122 gate oxides
123 grid
124 source regions
125 drain regions
126 body contact areas
13 PN junction devices
131 N districts
132 P districts
14 through holes
15 metals
S1～S4 step
Detailed description of the invention
Below by way of specific instantiation, embodiments of the present invention being described, those skilled in the art can be by disclosed by this specification
Content understand other advantages and effect of the present invention easily.The present invention can also be added by the most different detailed description of the invention
To implement or application, the every details in this specification can also be based on different viewpoints and application, in the essence without departing from the present invention
Various modification or change is carried out under god.
Refer to Fig. 1～Fig. 4.It should be noted that the diagram provided in the present embodiment illustrates the present invention's the most in a schematic way
Basic conception, the most graphic in component count time only display with relevant assembly in the present invention rather than is implemented according to reality, shape and
Size is drawn, and during its actual enforcement, the kenel of each assembly, quantity and ratio can be a kind of random change, and its assembly layout type
State is likely to increasingly complex.
Embodiment one
As shown in Fig. 1～Fig. 2, the present invention provides a kind of p-type dynamic threshold transistor 1, described p-type dynamic threshold transistor 1
At least include:
Substrat structure 11, is positioned at the PMOS device 12 on described substrat structure 11 and PN junction device 13.
As in figure 2 it is shown, described substrat structure 11 is positioned at bottom, as the substrate preparing semiconductor device.
Specifically, as in figure 2 it is shown, in the present embodiment, described substrat structure 11 at least includes semiconductor base 111 and is positioned at
Oxide layer 112 on described semiconductor base 111.Described semiconductor base 111 includes but not limited to the material such as silicon, silicon dioxide
Material.Described substrat structure 11 can also include that other improve the semiconductor layer of device performance, is not limited with the present embodiment.
As shown in Fig. 1～Fig. 2, described PMOS device 12 is positioned on described substrat structure 11, including channel region 121, grid oxygen
Change layer 122, grid 123, source region 124, drain region 125, and body contact area 126.
Specifically, as in figure 2 it is shown, described channel region 121 is positioned on described substrat structure 11, described channel region 121 is N
Type intrinsic region.Described gate oxide 122 is positioned on described channel region 121, and in the present embodiment, described gate oxide 122 is adopted
With the material of high-k.Described grid 123 are positioned at above described gate oxide 122, and described grid 123 are that p-type is heavily doped
Polysilicon, wherein right part does not carries out p-type heavy doping to play the effect of isolation.As it is shown in figure 1, described source region 124 He
Described drain region 125 lays respectively at the both sides of described channel region 121, for p-type heavily doped region.Described body contact area 126 is with described
Channel region 121 connects, and described body contact area 126 is N-type heavily doped region.
As shown in Fig. 1～Fig. 2, described PN junction device 13 is positioned on described substrat structure 11, including district 132 of N district 131 and P.
Specifically, as in figure 2 it is shown, described N district 131 is connected with the body contact area 126 of described PMOS device 12, described
N district 131 is N-type intrinsic region.Described P district 132 is connected with described N district 131, forms PN junction, and described P district 132 is
P-type heavily doped region.
As shown in Fig. 1～Fig. 2, the N district 131 of described PN junction device 13 and the body contact area 126 of described PMOS device 12
Connection, the grid 123 of the P district 132 of described PN junction device 13 and described PMOS device 12 are by through hole 14 and metal
15 connect.
Embodiment two
As it is shown on figure 3, in the present embodiment, it is provided that the p-type dynamic threshold transistor of a kind of many finger-cross structure, meet radio frequency
The gain of transistor and power requirement.
Specifically, the p-type dynamic threshold transistor of described many finger-cross structure includes mainly being formed by the PMOS of n parallel connection
PMOS device 12, and PN junction device 13, n is the natural number more than or equal to 1.In the present embodiment, n value is 4,
In actual design, determine the occurrence of n with the requirement of gain and power, be not limited with the present embodiment.Described PN junction device
Part 13 can be 1 PN junction diode being connected respectively with grid and the body contact area of n PMOS, it is also possible to be and n
N the PN junction diode that PMOS in parallel connects one to one.Described PMOS device 12 and described PN junction diode
The structure of 13 is consistent with embodiment one with annexation, repeats the most one by one at this.
Embodiment three
The present invention also provides for the preparation method of a kind of p-type dynamic threshold transistor as shown in Figure 2, and described p-type dynamic threshold is brilliant
The preparation method of body pipe at least includes:
Step S1: provide a substrat structure 11, prepares p-type intrinsic region on described substrat structure 11.
Specifically, as in figure 2 it is shown, in the present embodiment, described substrat structure 11 includes semiconductor base 111 and is positioned at described
Oxide layer 112 on semiconductor base 111.Described substrat structure 11 can also include that other improve the semiconductor layer of device performance,
It is not limited with the present embodiment.
Step S2: carry out in described N-type intrinsic region twice p-type heavy doping with formed respectively PMOS device 12 source region 124,
Drain region 125 and PN junction device 13, carry out p-type heavy doping to form the body of described PMOS device in described N-type intrinsic region
Contact area 126, the N district 131 of described PN junction device is connected with the body contact area 126 of described PMOS device 12, wherein,
It is channel region 121 between the source region 124 of described PMOS device 12, drain region 125.
Specifically, as in figure 2 it is shown, in the present embodiment, described N-type intrinsic region carries out p-type heavy doping and forms PMOS
The source region 124 of device 12 and drain region 125 (not showing in Fig. 2).P-type heavy doping formation is carried out in described N-type intrinsic region
The P district 132 of described PN junction device 13, to form PN junction device 13, the wherein conduct of N-type intrinsic region with N-type intrinsic region
The N district 131 of PN junction device 13.P-type heavy doping is carried out to form described PMOS device 12 in described N-type intrinsic region
Body contact area 126, the body contact area 126 of described PMOS device 12 is between the channel region 121 of described PMOS device 12
And between the N district 131 of described PN junction device 13.
Step S3: form gate oxide 122 above the channel region 121 of described PMOS device 12, at described gate oxide
Form polysilicon layer on 122, described polysilicon layer is carried out p-type heavy doping to form the grid 123 of described PMOS device 12.
Specifically, at the channel region 121 disposed thereon high dielectric constant material of described PMOS device 12 to form gate oxide
122.Deposit polycrystalline silicon layer on described gate oxide 122, carries out p-type heavy doping to form described PMOS to described polysilicon layer
The grid 123 of device 12, wherein, the polysilicon layer closing on part with described body contact area 126 does not carries out p-type heavy doping, to incite somebody to action
P-type doping is isolated with n-type doping.
Step S4: by through hole 14 and metal 15 by the grid 123 of described PMOS device 12 and described PN junction device 13
P district 132 is connected.
Embodiment four
As shown in Figure 4, the present invention also provides for a kind of method improving p-type dynamic threshold transistor running voltage, described raising P
The method of type dynamic threshold transistor running voltage at least includes:
Connecting PN junction device 13 between the grid and body contact area of PMOS device 12, the anode of described PN junction device 13 is even
Connecing the grid of described PMOS device 12, the negative electrode of described PN junction device 13 connects the body contact area of described PMOS device 12,
So that the body contact area voltage of described PMOS device 12 raises, and then reduce threshold voltage, improve driving electric current, it is achieved work
Make the raising of voltage.
Specifically, as shown in Figure 4, in order to meet gain and the power requirement of RF transistors, described PMOS device 12 is wrapped
Including n PMOS in parallel, n is the natural number more than or equal to 1.As shown in Figure 4, n value is 3, in actual design,
The occurrence of n is determined with the requirement of gain and power.The reverse-biased grid in described PMOS device 12 of described PN junction device 13,
On body connecting path, when grid voltage is negative voltage, and when reaching the threshold voltage of PMOS device 12, PMOS device 12
Opening, the change of grid voltage will affect the voltage of channel region；Owing to PN junction can bear bigger voltage, flow through this PN junction device
The electric current of part 13 is the least, and PN junction device 13 is not turned on, and is equivalent to access an electricity between the grid, body of PMOS device 12
Container piece, when grid voltage increases (i.e. negative voltage absolute value increases), channel region voltage increases the most therewith, and body contact area
Being connected with channel region, therefore body contact area voltage can necessarily be promoted；Simultaneously as grid voltage and body contact area voltage
When all increasing, the threshold voltage of PMOS device reduces, and it drives electric current to have also been obtained raising, so that the p-type of the present invention is moved
State threshold transistor running voltage improves, and reaches about 0.7V, it is possible to share supply voltage with traditional transistor, extend P
The application of type dynamic threshold transistor.
As it has been described above, the p-type dynamic threshold transistor of the present invention, preparation method and the method for raising running voltage, have following
Beneficial effect:
The method of the p-type dynamic threshold transistor of the present invention, preparation method and raising running voltage is by grid body connecting path
Form a reverse biased pn junction, carry out lifting body contact area voltage, reduce threshold voltage, raising driving electric current, it is achieved running voltage
Raising, extend the p-type dynamic threshold transistor using value at low consumption circuit design field.
In sum, the method for the p-type dynamic threshold transistor of the present invention, preparation method and raising running voltage is by grid body
Form a reverse biased pn junction on connecting path, carry out lifting body contact area voltage, reduce threshold voltage, raising driving electric current, real
The raising of existing running voltage, extends the p-type dynamic threshold transistor using value at low consumption circuit design field.So,
The present invention effectively overcomes various shortcoming of the prior art and has high industrial utilization.
The principle of above-described embodiment only illustrative present invention and effect thereof, not for limiting the present invention.Any it is familiar with this skill
Above-described embodiment all can be modified under the spirit and the scope of the present invention or change by the personage of art.Therefore, such as
All that in art, tool usually intellectual is completed under without departing from disclosed spirit and technological thought etc.
Effect is modified or changes, and must be contained by the claim of the present invention.
Claims (9)
1. a p-type dynamic threshold transistor, it is characterised in that described p-type dynamic threshold transistor at least includes:
Substrat structure, is positioned at the PMOS device on described substrat structure and PN junction device；
The N district of described PN junction device is connected with the body contact area of described PMOS device, the P district of described PN junction device with
The grid of described PMOS device connect；Wherein, the body contact area of described PMOS device is N-type heavily doped region, described PN
The N district of junction device is N-type intrinsic region, and the P district of described PN junction device is p-type heavily doped region.
P-type dynamic threshold transistor the most according to claim 1, it is characterised in that described substrat structure at least includes quasiconductor
Substrate and be positioned at the oxide layer on described semiconductor base.
P-type dynamic threshold transistor the most according to claim 1, it is characterised in that described PMOS device is n parallel connection
PMOS, n is the natural number more than or equal to 1.
P-type dynamic threshold transistor the most according to claim 3, it is characterised in that described PN junction device is in parallel with n
N PN junction diode connecting one to one of PMOS.
5. according to the p-type dynamic threshold transistor described in claim 1 or 3, it is characterised in that described PN junction device is 1 PN
Junction diode.
P-type dynamic threshold transistor the most according to claim 1, it is characterised in that described PMOS device also includes being positioned at
Channel region on described substrat structure, the gate oxide between described channel region and grid, and it is positioned at channel region both sides
Source region and drain region；Wherein, described channel region is N-type intrinsic region, and described grid are p-type heavily doped region, described source region and institute
Stating drain region is p-type heavily doped region.
P-type dynamic threshold transistor the most according to claim 1, it is characterised in that described PMOS device and described PN junction
Device is connected by through hole and metal.
8. the preparation method of a p-type dynamic threshold transistor, it is characterised in that the preparation method of described p-type dynamic threshold transistor
At least include:
One substrat structure is provided, described substrat structure is prepared N-type intrinsic region；
Twice p-type heavy doping is carried out to form the source of PMOS device, drain region and PN respectively in described N-type intrinsic region
Junction device, carries out the N-type heavy doping body contact area with the described PMOS device of formation in described N-type intrinsic region, described
The N district of PN junction device is connected with the body contact area of described PMOS device, wherein, and the source of described PMOS device, leakage
It it is channel region between district；
Above the channel region of described PMOS device, form gate oxide, described gate oxide formed polysilicon layer,
Described polysilicon layer is carried out p-type heavy doping to form the grid of described PMOS device；
The P district of the grid of described PMOS device with described PN junction device is connected with metal by through hole.
9. the method improving p-type dynamic threshold transistor running voltage, it is characterised in that described raising p-type dynamic threshold crystal
The method of pipe running voltage at least includes:
Connecting PN junction device between the grid and body contact area of PMOS device, the anode of described PN junction device connects described
The grid of PMOS device, the negative electrode of described PN junction device connects the body contact area of described PMOS device, so that described PMOS
The body contact area voltage of device raises, and then reduces threshold voltage, improves driving electric current, it is achieved the raising of running voltage.
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