CN203644788U - SOI technology-based back-gate drain/source semi-floating front gate P-MOSPFET radio frequency switch zero-loss device - Google Patents
SOI technology-based back-gate drain/source semi-floating front gate P-MOSPFET radio frequency switch zero-loss device Download PDFInfo
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Abstract
The utility model discloses an SOI technology-based back-gate drain/source semi-floating front gate P-MOSPFET radio frequency switch zero-loss device. An SOIPMOS device drain/source region is transformed. The junction depth of the drain/source region is arranged to be slightly smaller than N-type top-layer silicon thickness, that is, an N-type channel region. Taking back-gate drain semi floating as an example, the junction depth of the source region is deep, the junction depth of the drain region is arranged to be slightly smaller than P-type top-layer silicon thickness, and a parasitic diode is formed. Isolation of applying direct current signals to the drain electrode is formed. Through bias arrangement of body and back gate, the back gate MOSFET channel enters a conduction state. The structure adjusts impedance in a front gate MOSFET open state, the radio frequency loss of the front gate P-MOSFET applied in an open state as a switch is reduced, and even a zero-loss radio frequency switch is formed. When generation of self-heating effects of the device causes the back gate MOSFET to form negative impedance or when the back gate MOSFET works in an amplification state, the front gate coupling signals can be amplified directly, energy loss in the front gate open state can be remedied and ultra low-loss and zero-loss radio frequency switch is formed.
Description
Technical field
The utility model belongs to technical field of semiconductors, relates to a kind of based on SOI(semiconductor on insulator) grid P-MOSFET(N type metal-oxide semiconductor transistor before the back of the body grid leak/source half of technique is floating) radio-frequency (RF) switch zero loss device.
Background technology
SOI PMOS device is owing to adopting medium isolation, eliminate latch-up, and the insulating buried layer structure that it is unique, reduce to a great extent the ghost effect of device, greatly improve the performance of circuit, there is the advantages such as parasitic capacitance is little, integration density is high, speed is fast, technique is simple, short-channel effect is little, be widely used in low-voltage and low-power dissipation, at a high speed, anti-irradiation, the field such as high temperature resistant.The structure of conventional SOI PMOS device is the sandwich structure of dielectric substrate, buried regions, top monocrystalline silicon layer, forms the source of device while making device at top monocrystalline silicon layer, leaks the structures such as channel region.When this SOI PMOS device is normally worked, the logical raceway groove forming of a source leakage conductance top layer front surface in N-type channel region, and be lateral channel, grid field plate is covered on gate oxide, cause on-state power consumption high, device inefficiency, while utilization as radio-frequency (RF) switch loss large, be unfavorable for improving the overall performance of device and system.
Utility model content
For above-mentioned technological deficiency, the utility model proposes the floating front grid P-MOSFET radio-frequency (RF) switch zero loss device in back of the body grid leak/source half based on SOI technique
In order to solve the problems of the technologies described above, the technical solution of the utility model is as follows:
Grid P-MOSFET radio-frequency (RF) switch zero loss device before back of the body grid leak based on SOI technique half is floating, it is characterized in that, comprise P type semiconductor substrate 1, bury oxide layer 2, N-type channel region 12 and deep trench isolation region (4-1,4-2), burying oxide layer 2 covers on P type semiconductor substrate 1, N-type channel region 12 is arranged on buries in oxide layer 2, and deep trench isolation region (4-1,4-2) is arranged on and buries in oxide layer 2 and around the surrounding in N-type channel region 12, P type source region 3 and P type drain region 11;
Arrange near a side of N-type channel region 12 one compared with heavy doping P type semiconductor district the P type source region 3 as MOS device, junction depth is darker; Opposite side arrange one compared with heavy doping P type semiconductor district the P type drain region 11 as MOS device, this drain region junction depth is less than the thickness of N-type channel region 12 or deep trench isolation region (4-1,4-2); Skim lateral oxidation layer is arranged on N-type channel region 12 as gate oxide 9, cover 3 tops, P type source region part, N-type channel region 12 top all, the part at 11 tops, P type drain region; One polysilicon layer is arranged on gate oxide 9 as mos gate 8;
, P type source region 3 tops parts whole at 4-1 top, deep trench isolation region cover the first field oxide 5-1; Cover the second field oxide 5-2 in P type source region 3 top parts, gate oxide 9 one sides, mos gate 8 one sides, mos gate 8 top parts; Cover the 3rd field oxide 5-3 in mos gate 8 top parts, mos gate 8 one sides, gate oxide 9 one sides, P type drain region 11 top parts; All cover the 4th field oxide 5-4 at P type drain region 11 top parts, 4-2 top, deep trench isolation region; The remainder covering metal layer at 3 tops, P type source region is as source electrode 6, the top of source electrode 6 cover part the first field oxide 5-1, the top of part the second field oxide 5-2; The remainder covering metal layer at mos gate 8 tops is as gate electrode 7, the top of gate electrode 7 cover part the second field oxide 5-2, the top of part the 3rd field oxide 5-3; The remainder covering metal layer at 11 tops, P type drain region is as drain electrode 10, the top of drain electrode 10 cover parts the 3rd field oxide 5-3, the top of part the 4th field oxide 5-4.
2, the floating front grid P-MOSFET radio-frequency (RF) switch zero loss device in the back of the body grid source based on SOI technique half, it is characterized in that, comprise P type semiconductor substrate 1, bury oxide layer 2, N-type channel region 12 and deep trench isolation region (4-1,4-2), burying oxide layer 2 covers on P type semiconductor substrate 1, N-type channel region 12 is arranged on buries in oxide layer 2, and deep trench isolation region (4-1,4-2) is arranged on and buries in oxide layer 2 and around the surrounding in N-type channel region 12, P type source region 3 and P type drain region 11;
Arrange near a side of N-type channel region 12 one compared with heavy doping P type semiconductor district the P type drain region 11 as MOS device, junction depth is darker; Opposite side arrange one compared with heavy doping P type semiconductor district the P type source region 3 as MOS device, this source region junction depth is less than the thickness of N-type channel region 12 or deep trench isolation region (4-1,4-2); Skim lateral oxidation layer is arranged on N-type channel region 12 as gate oxide 9, cover 3 tops, P type source region part, N-type channel region 12 top all, the part at 11 tops, P type drain region; One polysilicon layer is arranged on gate oxide 9 as mos gate 8;
, P type source region 3 tops parts whole at 4-1 top, deep trench isolation region cover the first field oxide 5-1; Cover the second field oxide 5-2 in P type source region 3 top parts, gate oxide 9 one sides, mos gate 8 one sides, mos gate 8 top parts; Cover the 3rd field oxide 5-3 in mos gate 8 top parts, mos gate 8 one sides, gate oxide 9 one sides, N-type drain region 11 top parts; All cover the 4th field oxide 5-4 at P type drain region 11 top parts, 4-2 top, deep trench isolation region; The remainder covering metal layer at 3 tops, P type source region is as source electrode 6, the top of source electrode 6 cover part the first field oxide 5-1, the top of part the second field oxide 5-2; The remainder covering metal layer at mos gate 8 tops is as gate electrode 7, the top of gate electrode 7 cover part the second field oxide 5-2, the top of part the 3rd field oxide 5-3; The remainder covering metal layer at 11 tops, N-type drain region is as drain electrode 10, the top of drain electrode 10 cover parts the 3rd field oxide 5-3, the top of part the 4th field oxide 5-4.
The beneficial effects of the utility model are, SOI PMOS device leakage/source region is transformed, and it is N-type channel region that the junction depth setting in source (or leakage) district is slightly less than to N-type top layer silicon thickness.Partly float as example taking back of the body grid leak, source region junction depth is darker, the junction depth setting in drain region is slightly less than P type top layer silicon thickness, form parasitic diode, form the isolation that drain electrode is applied to direct current signal, pass through body, the setting of back of the body gate bias, make to carry on the back gate MOSFET raceway groove and enter conducting state, front grid P-MOSFET drain region AC signal can be coupled on back of the body gate MOSFET, because back of the body gate MOSFET works in conducting state, this structure forms and adjusts the impedance under front gate MOSFET ON state, front grid P-MOSFET is reduced as the radio frequency loss under the application of switch ON state, even form zero loss radio-frequency (RF) switch, in the time that device self-heating effect produces, causes carrying on the back gate MOSFET formation negative impedance, maybe in the time that back of the body gate MOSFET works in magnifying state, front grid coupled signal can directly be amplified, and the energy loss under grid ON state before compensation, forms ultralow, zero loss radio-frequency (RF) switch.
This device has different source-drain area junction depths, with single device, form ultralow even zero loss switch application, than adopting compensating circuit method for designing, there is lower power consumption, more small size, low cost more, be compatible with standard SOI technique, technique is easy to the features such as realization simultaneously.
Brief description of the drawings
Fig. 1 is the floating front grid P-MOSFET radio-frequency (RF) switch zero loss device of a kind of back of the body grid leak based on SOI technique half;
Fig. 2 is the floating front grid P-MOSFET radio-frequency (RF) switch zero loss device in a kind of back of the body grid source based on SOI technique half.
Embodiment
Below in conjunction with the drawings and specific embodiments, the utility model is described further:
As shown in Figure 1, grid P-MOSFET radio-frequency (RF) switch zero loss device before back of the body grid leak based on SOI technique half is floating, it is characterized in that, comprise P type semiconductor substrate 1, bury oxide layer 2, N-type channel region 12 and deep trench isolation region (4-1,4-2), burying oxide layer 2 covers on P type semiconductor substrate 1, N-type channel region 12 is arranged on buries in oxide layer 2, and deep trench isolation region (4-1,4-2) is arranged on and buries in oxide layer 2 and around the surrounding in N-type channel region 12, P type source region 3 and P type drain region 11;
Arrange near a side of N-type channel region 12 one compared with heavy doping P type semiconductor district the P type source region 3 as MOS device, junction depth is darker; Opposite side arrange one compared with heavy doping P type semiconductor district the P type drain region 11 as MOS device, this drain region junction depth is less than the thickness of N-type channel region 12 or deep trench isolation region (4-1,4-2); Skim lateral oxidation layer is arranged on N-type channel region 12 as gate oxide 9, cover 3 tops, P type source region part, N-type channel region 12 top all, the part at 11 tops, P type drain region; One polysilicon layer is arranged on gate oxide 9 as mos gate 8;
, P type source region 3 tops parts whole at 4-1 top, deep trench isolation region cover the first field oxide 5-1; Cover the second field oxide 5-2 in P type source region 3 top parts, gate oxide 9 one sides, mos gate 8 one sides, mos gate 8 top parts; Cover the 3rd field oxide 5-3 in mos gate 8 top parts, mos gate 8 one sides, gate oxide 9 one sides, P type drain region 11 top parts; All cover the 4th field oxide 5-4 at P type drain region 11 top parts, 4-2 top, deep trench isolation region; The remainder covering metal layer at 3 tops, P type source region is as source electrode 6, the top of source electrode 6 cover part the first field oxide 5-1, the top of part the second field oxide 5-2; The remainder covering metal layer at mos gate 8 tops is as gate electrode 7, the top of gate electrode 7 cover part the second field oxide 5-2, the top of part the 3rd field oxide 5-3; The remainder covering metal layer at 11 tops, P type drain region is as drain electrode 10, the top of drain electrode 10 cover parts the 3rd field oxide 5-3, the top of part the 4th field oxide 5-4.
As shown in Figure 2, grid P-MOSFET radio-frequency (RF) switch zero loss device before back of the body grid source based on SOI technique half is floating, it is characterized in that, comprise P type semiconductor substrate 1, bury oxide layer 2, N-type channel region 12 and deep trench isolation region (4-1,4-2), burying oxide layer 2 covers on P type semiconductor substrate 1, N-type channel region 12 is arranged on buries in oxide layer 2, and deep trench isolation region (4-1,4-2) is arranged on and buries in oxide layer 2 and around the surrounding in N-type channel region 12, P type source region 3 and P type drain region 11;
Arrange near a side of N-type channel region 12 one compared with heavy doping P type semiconductor district the P type drain region 11 as MOS device, junction depth is darker; Opposite side arrange one compared with heavy doping P type semiconductor district the P type source region 3 as MOS device, this source region junction depth is less than the thickness of N-type channel region 12 or deep trench isolation region (4-1,4-2); Skim lateral oxidation layer is arranged on N-type channel region 12 as gate oxide 9, cover 3 tops, P type source region part, N-type channel region 12 top all, the part at 11 tops, P type drain region; One polysilicon layer is arranged on gate oxide 9 as mos gate 8;
, P type source region 3 tops parts whole at 4-1 top, deep trench isolation region cover the first field oxide 5-1; Cover the second field oxide 5-2 in P type source region 3 top parts, gate oxide 9 one sides, mos gate 8 one sides, mos gate 8 top parts; Cover the 3rd field oxide 5-3 in mos gate 8 top parts, mos gate 8 one sides, gate oxide 9 one sides, N-type drain region 11 top parts; All cover the 4th field oxide 5-4 at P type drain region 11 top parts, 4-2 top, deep trench isolation region; The remainder covering metal layer at 3 tops, P type source region is as source electrode 6, the top of source electrode 6 cover part the first field oxide 5-1, the top of part the second field oxide 5-2; The remainder covering metal layer at mos gate 8 tops is as gate electrode 7, the top of gate electrode 7 cover part the second field oxide 5-2, the top of part the 3rd field oxide 5-3; The remainder covering metal layer at 11 tops, N-type drain region is as drain electrode 10, the top of drain electrode 10 cover parts the 3rd field oxide 5-3, the top of part the 4th field oxide 5-4.
The utility model is transformed SOI PMOS device leakage/source region, and the junction depth setting in source (or leakage) district is slightly less than to N-type top layer silicon thickness.Partly float as example taking back of the body grid leak, source region junction depth is darker, the junction depth setting in drain region is slightly less than N-type top layer silicon thickness, form parasitic diode, form the isolation that drain electrode is applied to direct current signal, pass through body, the setting of back of the body gate bias, make to carry on the back gate MOSFET raceway groove and enter conducting state, front grid P-MOSFET drain region AC signal can be coupled on back of the body gate MOSFET, because back of the body gate MOSFET works in conducting state, this structure forms and adjusts the impedance under front gate MOSFET ON state, front grid P-MOSFET is reduced as the radio frequency loss under the application of switch ON state, even form zero loss radio-frequency (RF) switch, in the time that device self-heating effect produces, causes carrying on the back gate MOSFET formation negative impedance, maybe in the time that back of the body gate MOSFET works in magnifying state, front grid coupled signal can directly be amplified, and the energy loss under grid ON state before compensation, forms ultralow, zero loss radio-frequency (RF) switch.
The above is only preferred implementation of the present utility model; it should be pointed out that for those skilled in the art, without departing from the concept of the premise utility; can also make some improvements and modifications, these improvements and modifications also should be considered as in the utility model protection range.
Claims (2)
1. the floating front grid P-MOSFET radio-frequency (RF) switch zero loss device of the back of the body grid leak based on SOI technique half, it is characterized in that, comprise P type semiconductor substrate (1), bury oxide layer (2), N-type channel region (12) and deep trench isolation region (4-1,4-2), burying oxide layer (2) covers on P type semiconductor substrate (1), N-type channel region (12) is arranged on that to bury oxide layer (2) upper, and deep trench isolation region (4-1,4-2) is arranged on that to bury oxide layer (2) upper and around the surrounding in N-type channel region (12), P type source region (3) and P type drain region (11);
Arrange near a side of N-type channel region (12) one compared with heavy doping P type semiconductor district the P type source region (3) as MOS device, junction depth is darker; Opposite side arrange one compared with heavy doping P type semiconductor district the P type drain region (11) as MOS device, this drain region junction depth is less than the thickness of N-type channel region (12) or deep trench isolation region (4-1,4-2); It is upper that skim lateral oxidation layer is arranged on N-type channel region (12) as gate oxide (9), cover top, P type source region (3) part, N-type channel region (12) top all, the part at top, P type drain region (11); One polysilicon layer is arranged on gate oxide (9) as mos gate (8);
In deep trench isolation region, (4-1) top all, top, P type source region (3) part covers the first field oxide (5-1); Cover the second field oxide (5-2) in top, P type source region (3) part, gate oxide (9) one sides, mos gate (8) one sides, mos gate (8) top part; Cover the 3rd field oxide (5-3) in mos gate (8) top part, mos gate (8) one sides, gate oxide (9) one sides, top, P type drain region (11) part; All cover the 4th field oxide (5-4) at top, P type drain region (11) part, top, deep trench isolation region (4-2); The remainder covering metal layer at top, P type source region (3) is as source electrode (6), the top of the top of source electrode (6) cover part the first field oxide (5-1), part the second field oxide (5-2); The remainder covering metal layer at mos gate (8) top is as gate electrode (7), the top of the top of gate electrode (7) cover part the second field oxide (5-2), part the 3rd field oxide (5-3); The remainder covering metal layer at top, P type drain region (11) is as drain electrode (10), the top of drain electrode (10) cover part the 3rd field oxide (5-3), the top of part the 4th field oxide (5-4).
2. the floating front grid P-MOSFET radio-frequency (RF) switch zero loss device in the back of the body grid source based on SOI technique half, it is characterized in that, comprise P type semiconductor substrate (1), bury oxide layer (2), N-type channel region (12) and deep trench isolation region (4-1,4-2), burying oxide layer (2) covers on P type semiconductor substrate (1), N-type channel region (12) is arranged on that to bury oxide layer (2) upper, and deep trench isolation region (4-1,4-2) is arranged on that to bury oxide layer (2) upper and around the surrounding in N-type channel region (12), P type source region (3) and P type drain region (11);
Arrange near a side of N-type channel region (12) one compared with heavy doping P type semiconductor district the P type drain region (11) as MOS device, junction depth is darker; Opposite side arrange one compared with heavy doping P type semiconductor district the P type source region (3) as MOS device, this source region junction depth is less than the thickness of N-type channel region (12) or deep trench isolation region (4-1,4-2); It is upper that skim lateral oxidation layer is arranged on N-type channel region (12) as gate oxide (9), cover top, P type source region (3) part, N-type channel region (12) top all, the part at top, P type drain region (11); One polysilicon layer is arranged on gate oxide (9) as mos gate (8);
In deep trench isolation region, (4-1) top all, top, P type source region (3) part covers the first field oxide (5-1); Cover the second field oxide (5-2) in top, P type source region (3) part, gate oxide (9) one sides, mos gate (8) one sides, mos gate (8) top part; Cover the 3rd field oxide (5-3) in mos gate (8) top part, mos gate (8) one sides, gate oxide (9) one sides, top, N-type drain region (11) part; All cover the 4th field oxide (5-4) at top, P type drain region (11) part, top, deep trench isolation region (4-2); The remainder covering metal layer at top, P type source region (3) is as source electrode (6), the top of the top of source electrode (6) cover part the first field oxide (5-1), part the second field oxide (5-2); The remainder covering metal layer at mos gate (8) top is as gate electrode (7), the top of the top of gate electrode (7) cover part the second field oxide (5-2), part the 3rd field oxide (5-3); The remainder covering metal layer at top, N-type drain region (11) is as drain electrode (10), the top of drain electrode (10) cover part the 3rd field oxide (5-3), the top of part the 4th field oxide (5-4).
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320869591.7U CN203644788U (en) | 2013-12-26 | 2013-12-26 | SOI technology-based back-gate drain/source semi-floating front gate P-MOSPFET radio frequency switch zero-loss device |
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| CN201320869591.7U CN203644788U (en) | 2013-12-26 | 2013-12-26 | SOI technology-based back-gate drain/source semi-floating front gate P-MOSPFET radio frequency switch zero-loss device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103700701A (en) * | 2013-12-26 | 2014-04-02 | 杭州电子科技大学 | Silicon on insulator (SOI) process-based back gate drain/source semi-floating front gate P type metal-oxide-semiconductor field effect transistor (P-MOSFET) radio frequency switch zero loss device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103700701A (en) * | 2013-12-26 | 2014-04-02 | 杭州电子科技大学 | Silicon on insulator (SOI) process-based back gate drain/source semi-floating front gate P type metal-oxide-semiconductor field effect transistor (P-MOSFET) radio frequency switch zero loss device |
| CN103700701B (en) * | 2013-12-26 | 2016-09-28 | 杭州电子科技大学 | The floating front gate P-MOSFET RF switching devices in backgate leakage/source based on SOI technology half |
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