CN103762237A - Transverse power device with field plate structure - Google Patents
Transverse power device with field plate structure Download PDFInfo
- Publication number
- CN103762237A CN103762237A CN201310749145.7A CN201310749145A CN103762237A CN 103762237 A CN103762237 A CN 103762237A CN 201310749145 A CN201310749145 A CN 201310749145A CN 103762237 A CN103762237 A CN 103762237A
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- China
- Prior art keywords
- source electrode
- field plate
- medium layer
- plate structure
- grid
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- 239000000758 substrate Substances 0.000 claims abstract description 26
- 239000004065 semiconductor Substances 0.000 claims abstract description 24
- 229910052751 metal Inorganic materials 0.000 claims abstract description 9
- 239000002184 metal Substances 0.000 claims abstract description 9
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- 230000005684 electric field Effects 0.000 abstract description 12
- 230000015556 catabolic process Effects 0.000 abstract 1
- 230000004907 flux Effects 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
A transverse power device with a field plate structure comprises a semiconductor substrate, a grid medium layer on the surface of the semiconductor substrate, a grid electrode on the surface of the grid medium layer, a source electrode, a drain electrode, a first medium layer, a second medium layer and a metal field plate, the source electrode and the drain electrode are arranged on the two sides of the grid electrode, the first medium layer is arranged on the surface of the grid medium layer, the second medium layer is arranged between the first medium layer and the grid medium layer, and the metal field plate is arranged on the surface of the first medium layer and the surface of the second medium layer. The end, close to the source electrode, of the metal field plate makes contact with the grid electrode, the distance between the end face, facing the source electrode, of the first medium layer and the source electrode is larger than the distance between the end face, facing the source electrode, of the second medium layer and the source electrode, and the device has the advantages that a plurality of electric field peak values are introduced so as to weaken the peak value electric field of the edge of the field plate and further improve the breakdown voltages, and meanwhile the power consumption of the device is reduced.
Description
Technical field
The present invention relates to a kind of lateral power with field plate structure, particularly a kind of lateral power with high-K gate dielectric and complex media ladder field plate structure, belongs to microelectronics and solid electronics technical field.
Background technology
Power integrated circuit also claims high voltage integrated circuit sometimes, it is the important branch that hyundai electronics is learned, can be various power conversions and energy processing unit provides the new-type circuit of high speed, high integration, low-power consumption and anti-irradiation, is widely used in many key areas such as the current consumption fields such as electric control system, automotive electronics, display device driving, communication and illumination and national defence, space flight.The rapid expansion of its range of application, also has higher requirement to the high tension apparatus of its core.In power integrated circuit, lateral double diffusion metal oxide semiconductor field effect transistor (LDMOS) plays an important role.Transversary is more conducive to the integrated application of high-density power of new generation, is the focus of contemporary power device research.
Field plate structure is a kind of technology that improves power device puncture voltage.Field plate structure is widely used in lateral high-voltage device, can make the electric flux in semiconductor surface part region transfer to another part, especially the electric flux of power line close quarters can be optimized to the weak region of electric field, realize the object that optimised devices built-in potential line distributes.
In order to improve puncture voltage, some field plate structures are suggested, and comprise ramp type field plate structure and single field plate structure etc.Ramp type field plate structure can regulate the electric flux of device inside to distribute, and realize the object that optimised devices built-in potential line distributes, but its shortcoming is to be difficult to realize in technique.Single field plate structure can be introduced peak electric field, but DeGrain need to be optimized the structure of device.
Summary of the invention
Technical problem to be solved by this invention is, a kind of lateral power with field plate structure is provided, by introducing a plurality of peak electric field, to weaken the peak value electric field at field plate edge, further to improve puncture voltage.
In order to address the above problem, a lateral power with field plate structure, comprises Semiconductor substrate, at the gate dielectric layer of described semiconductor substrate surface, at the grid on described gate dielectric layer surface, at the source electrode of described grid both sides and drain electrode, at the first medium layer on described gate dielectric layer surface, second medium layer between described first medium layer and described gate dielectric layer be positioned at described first medium layer and the Metal field plate on described second medium layer surface; Described Metal field plate is near one end and the described gate contact of source electrode; The distance of described first medium aspect to the end face of described source electrode to source electrode is greater than the distance of described second medium aspect to the end face of described source electrode to source electrode.
Alternatively, described semiconductor substrate surface comprises at the source electrode of described source electrode opposite position, in the drain electrode of described drain electrode opposite position, the well region under described grid, the He Ti contact zone, drift region between described well region and described drain electrode, described body contact zone is positioned at by described source electrode, contact with described well region, described source electrode, described drain electrode and described drift region all have the first conduction type, and described well region and described body contact zone have the second conduction type.
Alternatively, described the first conduction type is N-type, and described the second conduction type is P type.
Alternatively, described the first conduction type is P type, and described the second conduction type is N-type.
Alternatively, described Semiconductor substrate comprises support substrates, active layer and the insulating buried layer between described support substrates and active layer.
Alternatively, described first medium layer is SiO
2dielectric layer, described second medium layer is Si
3n
4dielectric layer.
The invention has the advantages that, on the basis of traditional single field plate structure, adopt the structure of multi-ladder field plate, introduce a plurality of peak electric field, the level and smooth Electric Field Distribution of whole drift region, has improved the voltage endurance capability of device.
Accompanying drawing explanation
Accompanying drawing 1 illustrates according to the schematic diagram of the lateral power with field plate structure of embodiment.
Embodiment
Below in conjunction with accompanying drawing, the embodiment with the lateral power of field plate structure provided by the invention is elaborated.
With reference to being according to the schematic diagram of the lateral power with field plate structure of this embodiment shown in accompanying drawing 1, comprise Semiconductor substrate 14, at the gate dielectric layer 5 on described Semiconductor substrate 14 surfaces, at the grid 16 on described gate dielectric layer 5 surfaces, at the source electrode 1 of described grid 16 both sides and drain electrode 6, at the first medium layer 3 on described gate dielectric layer 5 surfaces, second medium layer 4 between described first medium layer 3 and described gate dielectric layer 5 be positioned at described first medium layer 3 and the Metal field plate 2 on described second medium layer 4 surface; Described Metal field plate 2 contacts with described grid 16 near one end of source electrode 1; The distance of described first medium layer 3 towards the end face of described source electrode 1 to source electrode 1 is greater than the distance of described second medium layer 4 towards the end face of described source electrode 1 to source electrode 1.
Semiconductor substrate 14 in this embodiment is monocrystalline substrate, and in other execution mode, described Semiconductor substrate 14 can be also germanium silicon, strained silicon and other compound semiconductor substrate, as gallium nitride or GaAs etc.Also can be the MULTILAYER COMPOSITE substrat structure that semi-conducting material above-mentioned and that other are common forms.
Gate dielectric layer 5 in this embodiment is high-K gate dielectric layer, adopts high-K gate dielectric layer obtaining under the prerequisite of identical threshold voltage, to use higher channel doping concentration.The raising of channel doping concentration, is conducive to reduce the risk that channel punchthrough punctures, and can keep, under the prerequisite of voltage endurance capability, shortening channel length, thereby reduce the ON resistance of device.
In this embodiment, described Semiconductor substrate 14 surfaces comprise source electrode 12 at described source electrode 1 opposite position, in the drain electrode 7 of described drain electrode 6 opposite positions, the P trap 10 under described grid 16, N-type drift region 13 and the P type body contact zone 11 between described P trap 10 and described drain electrode 7, it is other that described P type body contact zone 11 is positioned at described source electrode 12, contact with described P trap 10, described source electrode 12, described drain electrode 7 are N-type doping.The unnecessary electric charge that described P type body contact zone 11 is assembled for drawing described P trap 10, avoids floater effect.In power integrated circuit, lateral double diffusion metal oxide semiconductor field effect transistor (LDMOS) has various structures, present embodiment is only preferred embodiment a kind of, also can select the lateral double diffusion metal oxide semiconductor field effect transistor (LDMOS) of other structures or have other variation when concrete making.
In this embodiment, described Semiconductor substrate 14 comprises support substrates 9, active layer 15 and the insulating buried layer 8 between described support substrates 9 and active layer 15.The existence of described insulating buried layer 8 can realize medium isolation, effectively realizes high and low power model, and the isolation between high-low voltage device, thoroughly eliminates electrical interference, simplifies the structural design of device.Yet in other embodiment, described Semiconductor substrate can be also the body substrate that does not comprise insulating buried layer, and this does not affect following adopted field plate techniques device is carried out to performance optimization.
The layer of first medium described in this embodiment 3 is SiO
2dielectric layer, described second medium layer 4 is Si
3n
4dielectric layer.Present embodiment is only preferred embodiment a kind of, also can select other dielectric materials to make field plate dielectric layers or have other variation when concrete making.
In this embodiment, adopt two layers of ladder field plate structure, also can make multi-step field plate structure in the specific implementation, present embodiment is only preferred embodiment a kind of, while specifically making, also can have other variation.
The advantage with the lateral power of field plate structure provided by the invention is: field plate structure can make the electric flux in semiconductor surface part region transfer to another part, especially the electric flux of power line close quarters can be optimized to the weak region of electric field, realize the object that optimised devices built-in potential line distributes.Meanwhile, multi-ladder field plate structure is introduced extra a plurality of peak electric field in drift region, thereby the level and smooth Electric Field Distribution of whole drift region has improved the voltage endurance capability of device.Meanwhile, the field plate thickness of dielectric layers by source to drain terminal constantly increases, and is conducive to the less gate leakage capacitance of maintenance, to guarantee the switching speed of device.And because the electric field strength of raceway groove/drift region position is suppressed, can use higher drift region doping content, this is conducive to reduce device drift zone resistance, thereby realize the object that reduces device power consumption.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (6)
1. a lateral power with field plate structure, comprise Semiconductor substrate, be positioned at described semiconductor substrate surface gate dielectric layer, be positioned at the grid on described gate dielectric layer surface and be positioned at source electrode and the drain electrode of described grid both sides, it is characterized in that, comprise first medium layer, the second medium layer between described first medium layer and described gate dielectric layer on described gate dielectric layer surface and be positioned at described first medium layer and the Metal field plate on described second medium layer surface; Described Metal field plate is near one end and the described gate contact of source electrode; The distance of described first medium aspect to the end face of described source electrode to source electrode is greater than the distance of described second medium aspect to the end face of described source electrode to source electrode.
2. the lateral power with field plate structure according to claim 1, it is characterized in that, described semiconductor substrate surface comprises the source electrode that is positioned at described source electrode opposite position, be positioned at the drain electrode of described drain electrode opposite position, be positioned at the well region under described grid, He Ti contact zone, drift region between described well region and described drain electrode, described body contact zone is positioned at by described source electrode, contact with described well region, described source electrode, described drain electrode and described drift region all have the first conduction type, described well region and described body contact zone have the second conduction type.
3. the lateral power with field plate structure according to claim 2, is characterized in that, described the first conduction type is N-type, and described the second conduction type is P type.
4. the lateral power with field plate structure according to claim 2, is characterized in that, described the first conduction type is P type, and described the second conduction type is N-type.
5. the lateral power with field plate structure according to claim 1, is characterized in that, described Semiconductor substrate comprises support substrates, active layer and the insulating buried layer between described support substrates and active layer.
6. the lateral power with field plate structure according to claim 1, is characterized in that, described first medium layer is SiO
2dielectric layer, described second medium layer is Si
3n
4dielectric layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310749145.7A CN103762237A (en) | 2013-12-31 | 2013-12-31 | Transverse power device with field plate structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310749145.7A CN103762237A (en) | 2013-12-31 | 2013-12-31 | Transverse power device with field plate structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103762237A true CN103762237A (en) | 2014-04-30 |
Family
ID=50529446
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310749145.7A Pending CN103762237A (en) | 2013-12-31 | 2013-12-31 | Transverse power device with field plate structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103762237A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111180528A (en) * | 2020-02-14 | 2020-05-19 | 重庆邮电大学 | Three-order inclined mesa junction terminal structure of SiC Schottky diode |
| CN112635541A (en) * | 2019-10-08 | 2021-04-09 | 无锡华润上华科技有限公司 | LDMOS device and preparation method thereof |
| CN116913963A (en) * | 2023-09-06 | 2023-10-20 | 深圳智芯微电子科技有限公司 | Gallium nitride device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101079446A (en) * | 2007-06-01 | 2007-11-28 | 安徽大学 | Horizontal dispersion oxide semiconductor of heterogeneous bar multi-step field electrode board |
| US20080303057A1 (en) * | 2007-06-07 | 2008-12-11 | Fuji Electric Device Technology Co., Ltd. | Semiconductor device and method of manufacturing thereof |
| US20120280319A1 (en) * | 2009-11-03 | 2012-11-08 | Georg Roehrer | High-Voltage Transistor having Multiple Dielectrics and Production Method |
-
2013
- 2013-12-31 CN CN201310749145.7A patent/CN103762237A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101079446A (en) * | 2007-06-01 | 2007-11-28 | 安徽大学 | Horizontal dispersion oxide semiconductor of heterogeneous bar multi-step field electrode board |
| US20080303057A1 (en) * | 2007-06-07 | 2008-12-11 | Fuji Electric Device Technology Co., Ltd. | Semiconductor device and method of manufacturing thereof |
| US20120280319A1 (en) * | 2009-11-03 | 2012-11-08 | Georg Roehrer | High-Voltage Transistor having Multiple Dielectrics and Production Method |
Non-Patent Citations (1)
| Title |
|---|
| 刘磊等: "高压LDMOS场极板的分析与设计", 《半导体技术》, vol. 31, no. 10, 31 October 2006 (2006-10-31) * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112635541A (en) * | 2019-10-08 | 2021-04-09 | 无锡华润上华科技有限公司 | LDMOS device and preparation method thereof |
| CN112635541B (en) * | 2019-10-08 | 2022-08-12 | 无锡华润上华科技有限公司 | LDMOS device and preparation method thereof |
| US11923453B2 (en) | 2019-10-08 | 2024-03-05 | Csmc Technologies Fab2 Co., Ltd. | LDMOS device and method for preparing same |
| CN111180528A (en) * | 2020-02-14 | 2020-05-19 | 重庆邮电大学 | Three-order inclined mesa junction terminal structure of SiC Schottky diode |
| CN116913963A (en) * | 2023-09-06 | 2023-10-20 | 深圳智芯微电子科技有限公司 | Gallium nitride device |
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Application publication date: 20140430 |