CN205752182U - A kind of semiconductor power device structure - Google Patents
A kind of semiconductor power device structure Download PDFInfo
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- CN205752182U CN205752182U CN201520626991.4U CN201520626991U CN205752182U CN 205752182 U CN205752182 U CN 205752182U CN 201520626991 U CN201520626991 U CN 201520626991U CN 205752182 U CN205752182 U CN 205752182U
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 33
- 229910052751 metal Inorganic materials 0.000 claims abstract description 33
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 28
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 28
- 239000001301 oxygen Substances 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims description 21
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 230000005684 electric field Effects 0.000 abstract description 25
- 230000015556 catabolic process Effects 0.000 abstract description 21
- 238000002347 injection Methods 0.000 description 9
- 239000007924 injection Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 6
- 238000002360 preparation method Methods 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 238000010301 surface-oxidation reaction Methods 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
The utility model discloses a kind of semiconductor power device structure, introduce, in the Trench layer of traditional lateral power Trench LDMOS structure, the longitudinal metal field plate that many layer depth are different, in drift region, introduce one layer of highly doped n-type layer simultaneously, in terms of improving device electric breakdown strength, the Metal field plate that multilamellar length does not waits can introduce multiple new peak electric field in drift region, surface height electric field is introduced internal, it is to avoid device punctures in advance on surface simultaneously；Highly doped n-type layer after fully-depleted improves Trench layer surface charge density, improves Trench layer and drift region electric field, improves device electric breakdown strength, and in terms of reducing device on-resistance, deep oxygen Trench layer reduces lateral drift section length.
Description
Technical field
This utility model relates to the technical field of quasiconductor, particularly relates to a kind of semiconductor power device structure
Preparation structure.
Background technology
Power integrated circuit is sometimes referred to as high voltage integrated circuit, is the important branch of modern electronics, can be
Various power conversions and energy processing means provide the novel of high speed, high integration, low-power consumption and Flouride-resistani acid phesphatase
Circuit, is widely used in electric control system, automotive electronics, display device drive, communicate and illumination etc.
Current consumption field and many key areas such as national defence, space flight.The rapid expansion of its range of application, right
The high tension apparatus of its core it is also proposed higher requirement.
For power device MOSFET, on the premise of ensureing breakdown voltage, it is necessary to as much as possible
The conducting resistance reducing device improves device performance.But there is one between breakdown voltage and conducting resistance
Approximation quadratic relationship, forms so-called " silicon limit ".In order to break " silicon limit ", improve device performance, carry
Having gone out various new device architecture, typical structure has: super-junction structure and IGBT structure.Superjunction is base
In three-dimensional RESURF technology, its drift region is constituted by heavily doped P, N post is alternate.The reason of this technology
Opinion basis is charge compensation principle, when drain voltage reaches certain value, and the N-type region of drift region and P
Type district exhausts each other, is finally reached completely depleted, effectively raises drift region electric field, improves device
The breakdown voltage of part, further, since drift region N-type region and p type island region exhaust each other, is effectively increased
Drift doping concentration, reduces the conducting resistance of device.But, super-junction structure complex process, device
Can be very sensitive to charge imbalance, especially for breakdown voltage in the application of more than 600V, it is repeatedly
The technique that extension is injected also makes production cost remain high.IGBT structure is based on conductance modulation principle,
Its device architecture is to change the N-type drained in traditional structure into p-type, and other structures are constant, therefore, and device
The breakdown voltage of part almost can keep constant.When break-over of device, owing to drain electrode has made p-type into, because of
This can inject substantial amounts of hole to drift region, modulates drift region carrier concentration, increases conducting electric current, fall
The conducting resistance of low device.But, during due to break-over of device, drift region also exists substantial amounts of hole,
When device turns off, the compound and extraction of few son needs the regular hour, the most so-called few sub-storage effect,
So-called " tail currents " can be formed so that the turn-off time of device is longer, affect the high frequency of device
Energy.
Utility model content
The purpose of this utility model is to propose the structure of a kind of semiconductor power device structure, it is intended to solve
How can prepare semiconductor power device simply and easily.
For reaching this purpose, this utility model by the following technical solutions:
A kind of semiconductor power device structure, described semiconductor power device structure includes:
Source electrode, source metal, grid metal, drain electrode, drain metal, source body, polysilicon, metal field
Plate, N-type heavily doped region, oxygen Trench layer, N-type drift region, oxygen buried layer, P type substrate；
Described P type substrate is at the bottom of described semiconductor power device structure, and described oxygen buried layer is at described P
Type substrate, described N-type drift region is on described oxygen buried layer, and described N-type heavily doped region is in institute
State on N-type drift region, described oxygen Trench layer on described N-type heavily doped region, described metal
Field plate is longitudinal field plate that multilamellar length does not waits, in described N-type drift region near described oxygen Trench layer
Surface inject one layer of highly doped n-type layer.
Preferably, longitudinal field plate that described multilamellar length does not waits is longitudinal field plate that three layers of length do not wait.
This utility model is in the Trench layer of traditional lateral power Trench LDMOS structure
Introduce the longitudinal metal field plate that many layer depth are different, in drift region, introduce one layer of highly doped n-type layer simultaneously,
In terms of improving device electric breakdown strength, the Metal field plate that multilamellar length does not waits can introduce many in drift region
Individual new peak electric field, introduces internal by surface height electric field, it is to avoid device punctures in advance on surface simultaneously；
Highly doped n-type layer after fully-depleted improves Trench layer surface charge density, improves Trench layer
With drift region electric field, improve device electric breakdown strength；In terms of reducing device on-resistance, deep oxygen Trench
Layer reduces lateral drift section length, and multilayer field plate can be formed low on Trench layer surface when break-over of device
The introducing of resistance current channel and heavily doped n-type area can effectively reduce the conducting resistance of device,
Improving device performance, this device architecture is the most applicable for Si base, SOI base, SiC base substrate.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of this utility model embodiment semiconductor power device structure；
Fig. 2 is the another kind of schematic diagram of this utility model embodiment semiconductor power device structure；
Fig. 3 is the schematic diagram of this utility model embodiment semiconductor power device electric field；
Fig. 4 is the flow process signal of the preparation method of this utility model embodiment semiconductor power device structure
Figure.
10 mark source metals, 11 mark grid metals, 12 mark drain metal, 13 mark drain electrodes, 14
Mark oxygen Trench floor, 15 mark N-type heavily doped regions, 16 mark N-type skew districts, 17 marks are buried
Oxygen district, 18 mark P type substrate, 19 coding metal field plates, 20 mark polysilicons, 21 mark source electrode bodies
District, 22 mark source electrodes.
Detailed description of the invention
Further illustrate technical side of the present utility model below in conjunction with the accompanying drawings and by detailed description of the invention
Case.
Embodiment one
It is the schematic diagram of this utility model embodiment semiconductor power device structure with reference to Fig. 1, Fig. 1.
In embodiment one, described semiconductor power device structure includes:
Source electrode, source metal, grid metal, drain electrode, drain metal, source body, polysilicon, metal field
Plate, N-type heavily doped region, oxygen Trench layer, N-type drift region, oxygen buried layer, P type substrate；
Described P type substrate is at the bottom of described semiconductor power device structure, and described oxygen buried layer is at described P
Type substrate, described N-type drift region is on described oxygen buried layer, and described N-type heavily doped region is in institute
State on N-type drift region, described oxygen Trench layer on described N-type heavily doped region, described metal
Field plate is longitudinal field plate that multilamellar length does not waits, in described N-type drift region near described oxygen Trench layer
Surface inject one layer of highly doped n-type layer.
Preferably, longitudinal field plate that described multilamellar length does not waits is longitudinal field plate that three layers of length do not wait.
Concrete, tradition Trench LDMOS device is to insert the oxygen of a layer depth in the middle part of drift region
Trench layer, can effectively reduce drift region length, reduces device on-resistance, but device is in
During OFF state, electric field major part is all gathered in device surface, and internal electric field is less, and device easily carries on surface
Before puncture, limit the further raising of breakdown voltage, the utility model proposes a kind of new device junction
Structure, if Fig. 1 is as a example by SOI base substrate, it introduces on the basis of tradition Trench LDMOS device
Longitudinal field plate that multilamellar length does not waits, injects one layer of weight simultaneously in drift region near the surface of Trench layer
Doped n-type layer.Device be in reverse pressure time, each of which layer field plate all can introduce in drift region
One or more new peak electric field, such as Fig. 1, leave after the heavily doped n-layer fully-depleted of drift region
Substantial amounts of positive charge, the negative charge introduced in conjunction with field plate, effectively raise the electric field of Trench layer, from
And further increase the average electric field of drift region, improve device electric breakdown strength.When break-over of device, grid
The existence of pressure can make to form electron accumulation near the surface of Trench layer, thus forms the electricity of a low-resistance
Circulation road, it addition, the assisted depletion effect of Trench layer can effectively improve drift doping concentration,
Reduce device on-resistance.In device designs, by optimize drift region concentration, each longitudinal field plate deep
Degree and distance, while improving breakdown voltage, can reduce the conducting resistance of device, improve device
Energy.This device architecture is the most applicable for Si base, SOI base, SiC base substrate.
Embodiment two
It is the another kind of signal of this utility model embodiment semiconductor power device structure with reference to Fig. 2, Fig. 2
Figure.
Fig. 3 is the schematic diagram of this utility model embodiment semiconductor power device electric field.
Concrete, the breakdown voltage of lateral power LDMOS structure is by the most pressure and longitudinal pressure
Together decide on, and in certain scope, the most pressure and drift region length of device is directly proportional, and drift
Move district's doping content to be inversely proportional to, the conducting resistance of device then contrast, therefore, lateral power
Breakdown voltage and conducting resistance between mutually restrict, there is a contradictory relation.
Embodiment three
It it is the flow process of the preparation method of embodiment of the present invention semiconductor power device structure with reference to Fig. 4, Fig. 4
Schematic diagram.
In embodiment three, the preparation method of described semiconductor power device structure includes:
Step 401, performs etching on thick-film SOI substrate, forms Trench layer window, and to described
Thick-film SOI substrate carries out oblique angle injection and bottom is injected, and forms doped n-type drift region；
Step 402, carries out short annealing, and carries out surface oxidation after injection, at described Trench layer window
Discharge surface forms one layer of thin SiO2Layer；
Step 403, carries out SiO2Deposition, forms deep oxygen Trench layer, carries out P-well injection, enter
Row N+ injects, and carries out P+ injection and carries out short annealing；
Step 404, polysilicon opening etch, heavily doped polysilicon deposition, Metal field plate opening etch with
And metal deposit, metal etch, form source electrode, drain electrode, grid.
Concrete, device preparation flow (as a example by SOI base substrate):
(1) perform etching on thick-film SOI substrate, form Trench layer window；
(2) carrying out oblique angle injection and bottom is injected, form doped n-type drift region, implantation dosage is about
For drift region concentration 8～10 times；
(3) short annealing and surface oxidation are carried out simultaneously, form one layer of thin SiO in window surface2Layer with
And activating injection ion, temperature is 800～900 DEG C, and the time is 20～50min；
(4) SiO is carried out2Deposition, forms deep oxygen Trench layer；
(5) P-well injection is carried out；
(6) N+ injection is carried out；
(7) carry out P+ injection and carry out short annealing；
(8) polysilicon opening etch；
(9) heavily doped polysilicon deposition；
(10) Metal field plate opening etch, window width is in 0.4～0.8 μm；
(11) metal deposit；
(12) metal etch, forms source electrode, drain electrode, grid.
Concrete, tradition Trench LDMOS device is to insert the oxygen of a layer depth in the middle part of drift region
Trench layer, can effectively reduce drift region length, reduces device on-resistance, but device is in
During OFF state, electric field major part is all gathered in device surface, and internal electric field is less, and device easily carries on surface
Before puncture, limit the further raising of breakdown voltage, the utility model proposes a kind of new device junction
Structure, if Fig. 1 is as a example by SOI base substrate, it introduces on the basis of tradition Trench LDMOS device
Longitudinal field plate that multilamellar length does not waits, injects one layer of weight simultaneously in drift region near the surface of Trench layer
Doped n-type layer.Device be in reverse pressure time, each of which layer field plate all can introduce in drift region
One or more new peak electric field, such as Fig. 3, leave after the heavily doped n-layer fully-depleted of drift region
Substantial amounts of positive charge, the negative charge introduced in conjunction with field plate, effectively raise the electric field of Trench layer, from
And further increase the average electric field of drift region, improve device electric breakdown strength.When break-over of device, grid
The existence of pressure can make to form electron accumulation near the surface of Trench layer, thus forms the electricity of a low-resistance
Circulation road, it addition, the assisted depletion effect of Trench layer can effectively improve drift doping concentration,
Reduce device on-resistance.In device designs, by optimize drift region concentration, each longitudinal field plate deep
Degree and distance, while improving breakdown voltage, can reduce the conducting resistance of device, improve device
Energy.This device architecture is the most applicable for Si base, SOI base, SiC base substrate.
This utility model embodiment is at the Trench of traditional lateral power Trench LDMOS structure
Introduce the longitudinal metal field plate that many layer depth are different in Ceng, in drift region, introduce one layer of heavy doping n simultaneously
Type layer, in terms of improving device electric breakdown strength, the Metal field plate that multilamellar length does not waits can be in drift region
Introduce multiple new peak electric field, surface height electric field is introduced internal, it is to avoid device shifts to an earlier date on surface simultaneously
Puncture；Highly doped n-type layer after fully-depleted improves Trench layer surface charge density, improves Trench
Layer and drift region electric field, improve device electric breakdown strength；In terms of reducing device on-resistance, deep oxygen Trench
Layer reduces lateral drift section length, and multilayer field plate can be formed low on Trench layer surface when break-over of device
The introducing of resistance current channel and heavily doped n-type area can effectively reduce the conducting resistance of device,
Improving device performance, this device architecture is the most applicable for Si base, SOI base, SiC base substrate, longitudinally gold
Belong to field plate and the valid density of drift region on the one hand with assisted depletion drift region, can be improved, on the other hand at device
In highly doped n-type district, define the current channel of a low-resistance during part conducting, effectively reduce device
Conducting resistance.
This utility model embodiment is at the Trench of traditional lateral power Trench LDMOS structure
Introduce the longitudinal metal field plate that many layer depth are different in Ceng, in drift region, introduce one layer of heavy doping n simultaneously
Type layer, in terms of improving device electric breakdown strength, the Metal field plate that multilamellar length does not waits can be in drift region
Introduce multiple new peak electric field, surface height electric field is introduced internal, it is to avoid device shifts to an earlier date on surface simultaneously
Puncture；Highly doped n-type layer after fully-depleted improves Trench layer surface charge density, improves Trench
Layer and drift region electric field, improve device electric breakdown strength；In terms of reducing device on-resistance, deep oxygen Trench
Layer reduces lateral drift section length, and multilayer field plate can be formed low on Trench layer surface when break-over of device
The introducing of resistance current channel and heavily doped n-type area can effectively reduce the conducting resistance of device,
Improving device performance, this device architecture is the most applicable for Si base, SOI base, SiC base substrate.
Know-why of the present utility model is described above in association with specific embodiment.These descriptions are intended merely to
Explain principle of the present utility model, and can not be construed to by any way this utility model protection domain
Limit.Based on explanation herein, those skilled in the art need not pay performing creative labour and can join
Expecting other detailed description of the invention of the present utility model, these modes fall within protection of the present utility model
Within the scope of.
Claims (2)
1. a semiconductor power device structure, it is characterised in that described semiconductor power device structure
Including:
Source electrode, source metal, grid metal, drain electrode, drain metal, source body, polysilicon, metal field
Plate, N-type heavily doped region, oxygen Trench layer, N-type drift region, oxygen buried layer, P type substrate；
Described P type substrate is at the bottom of described semiconductor power device structure, and described oxygen buried layer is at described P
Type substrate, described N-type drift region is on described oxygen buried layer, and described N-type heavily doped region is in institute
State on N-type drift region, described oxygen Trench layer on described N-type heavily doped region, described metal
Field plate is longitudinal field plate that multilamellar length does not waits, in described N-type drift region near described oxygen Trench layer
Surface inject one layer of highly doped n-type layer.
Semiconductor power device structure the most according to claim 1, it is characterised in that described many
Longitudinal field plate that layer length does not waits is longitudinal field plate that three layers of length do not wait.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105070758A (en) * | 2015-08-19 | 2015-11-18 | 工业和信息化部电子第五研究所华东分所 | Preparation method for semiconductor power device structure, and structure |
| WO2021135265A1 (en) * | 2019-12-31 | 2021-07-08 | 无锡华润上华科技有限公司 | Ldmos device and manufacturing method therefor |
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2015
- 2015-08-19 CN CN201520626991.4U patent/CN205752182U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105070758A (en) * | 2015-08-19 | 2015-11-18 | 工业和信息化部电子第五研究所华东分所 | Preparation method for semiconductor power device structure, and structure |
| CN105070758B (en) * | 2015-08-19 | 2018-07-24 | 工业和信息化部电子第五研究所华东分所 | A kind of preparation method and structure of semiconductor power device structure |
| WO2021135265A1 (en) * | 2019-12-31 | 2021-07-08 | 无锡华润上华科技有限公司 | Ldmos device and manufacturing method therefor |
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