CN203644790U

CN203644790U - SOI technology based drain/source region medium (PN junction) isolation front gate P-MOSFET radio frequency switch ultra-low-loss device

Info

Publication number: CN203644790U
Application number: CN201320890491.2U
Authority: CN
Inventors: 刘军
Original assignee: Hangzhou Electronic Science and Technology University
Current assignee: Hangzhou Dianzi University; Hangzhou Electronic Science and Technology University
Priority date: 2013-12-30
Filing date: 2013-12-30
Publication date: 2014-06-11
Anticipated expiration: 2023-12-30

Abstract

The utility model discloses an SOI technology based drain/source region medium (PN junction) isolation front gate P-MOSFET radio frequency switch ultra-low-loss device, which is characterized by transforming a source/drain region of an SOIP-MOSFET device to form a PN junction or a medium capacitor with the junction depth of the source region being high, manufacturing a P-type doped drain region or medium at the middle of the drain region, forming the PN junction or the medium capacitor, forming isolation applying DC offset to the drain region, enabling a back gate MOSFET channel to be conducted through arranging a body gate and a back gate, coupling drain region AC signals of a front gate P-MOSFET to a back gate MOSFET, adjusting impedance of the front gate MOSFET at an on-state because the back gate MOSFET operates at a conduction state so as to enable the radio frequency loss of the front gate P-MOSFET acting as a switch in on-site application to be reduced, thereby being an ultra-low-loss radio frequency switch; and when a self-heating effect occurs and the back gate MOSFET is caused to form negative impedance, or the back gate MOSFET operates at an amplification state, the front gate coupling signals can be directly amplified, energy loss of the front gate at the on-state is compensated, and the loss is enabled to be further reduced.

Description

Grid P-MOSFET radio-frequency (RF) switch ultra-low loss device before leakage/source region medium (PN junction) isolation based on SOI technique

Technical field

The utility model belongs to technical field of semiconductors, relates to a kind of front grid P-MOSFETP type metal-oxide semiconductor transistor radio-frequency (RF) switch ultra-low loss device of leakage (source) district's medium (diode) isolation based on SOI semiconductor on insulator technique.

Background technology

SOI P-MOSFET device is owing to adopting medium isolation, eliminate latch-up, and the insulating buried layer structure that it is unique, reduce to a great extent the ghost effect of device, greatly improve the performance of circuit, there is the advantages such as parasitic capacitance is little, integration density is high, speed is fast, technique is simple, short-channel effect is little, be widely used in low-voltage and low-power dissipation, at a high speed, anti-irradiation, the field such as high temperature resistant.The structure of conventional SOI P-MOSET device is the sandwich structure of dielectric substrate, buried regions, top monocrystalline silicon layer, forms the source of device while making device at top monocrystalline silicon layer, leaks the structures such as channel region.When this SOI P-MOSFET device is normally worked, the logical raceway groove forming of a source leakage conductance top layer front surface in N-type channel region, and be lateral channel, grid field plate is covered on gate oxide, cause on-state power consumption high, device inefficiency, while utilization as radio-frequency (RF) switch loss large, be unfavorable for improving the overall performance of device and system.

Utility model content

For above-mentioned technological deficiency, the utility model proposes a kind of front grid P-MOSFET radio-frequency (RF) switch ultra-low loss device of leakage/source region medium/PN junction isolation based on SOI technique

In order to solve the problems of the technologies described above, the technical solution of the utility model is as follows:

Grid P-MOSFET radio-frequency (RF) switch ultra-low loss device before the isolation of drain region medium (PN junction) based on SOI technique, comprises P type semiconductor substrate 1, buries oxide layer 2, the P type drain region 13 of the P type drain region 11 of N-type channel region 12, P type source region 3, front gate MOSFET, back of the body gate MOSFET, P type drain region isolated area 14 and deep trench isolation region (4-1,4-2); Burying oxide layer 2 covers on P type semiconductor substrate 1, N-type channel region 12 is arranged on buries in oxide layer 2, and deep trench isolation region (4-1,4-2) is arranged on and buries in oxide layer 2 and around P type drain region 11, the back of the body P type drain region 13 of gate MOSFET and the surrounding of P type drain region isolated area 14 of N-type channel region 12, P type source region 3, front gate MOSFET;

Arrange near a side of N-type channel region 12 one compared with heavy doping P type semiconductor district as front grid and the back of the body the shared P type source region 3 of gate MOSFET, junction depth is darker; Opposite side arrange upper and lower two compared with heavy doping P type semiconductor district respectively as the P type drain region 11 of front gate MOSFET and the P type drain region 13 of back of the body gate MOSFET, the junction depth summation thickness in the P type drain region 13 of the P type drain region 11 of front gate MOSFET and back of the body gate MOSFET is less than the thickness of N-type channel region 12 or deep trench isolation region (4-1,4-2); Thereby a dielectric area or formation P type drain region, N-type district isolated area 14 are set between the P of front gate MOSFET type drain region 11 and the P type drain region 13 of back of the body gate MOSFET, the isolation of described P type drain region isolated area 14 to front grid P type drain region 11 and back of the body grid P type drain region 13; Skim lateral oxidation layer is arranged on N-type channel region 12 as gate oxide 9, and the top of part, N-type channel region 12 that covers 3 tops, P type source region is whole, the part at 11 tops, P type drain region of front gate MOSFET; One polysilicon layer is arranged on gate oxide 9 as mos gate 8;

, P type source region 3 tops parts whole at 4-1 top, deep trench isolation region cover the first field oxide 5-1; Cover the second field oxide 5-2 in P type source region 3 top parts, gate oxide 9 one sides, mos gate 8 one sides, mos gate 8 top parts; In the P type drain region of mos gate 8 top parts, mos gate 8 one sides, gate oxide 9 one sides, front gate MOSFET, 11 top parts cover the 3rd field oxide 5-3; All cover the 4th field oxide 5-4 at the P of front gate MOSFET type drain region 11 top parts, 4-2 top, deep trench isolation region; The remainder covering metal layer at 3 tops, P type source region is as source electrode 6, the top of source electrode 6 cover part the first field oxide 5-1, the top of part the second field oxide 5-2; The remainder covering metal layer at mos gate 8 tops is as gate electrode 7, the top of gate electrode 7 cover part the second field oxide 5-2, the top of part the 3rd field oxide 5-3; The remainder covering metal layer at 11 tops, P type drain region of front gate MOSFET is as drain electrode 10, the top of drain electrode 10 cover parts the 3rd field oxide 5-3, the top of part the 4th field oxide 5-4.

Grid P-MOSFET radio-frequency (RF) switch ultra-low loss device before the isolation of source region medium (PN junction) based on SOI technique, comprises P type semiconductor substrate 1, buries oxide layer 2, N-type channel region 12, P type drain region 11, the P type source region 3-1 of front gate MOSFET, P type source region 13-1, P type source region isolated area 14-1 and deep trench isolation region (4-1, the 4-2) of back of the body gate MOSFET; Burying oxide layer 2 covers on P type semiconductor substrate 1, N-type channel region 12 is arranged on buries in oxide layer 2, and deep trench isolation region (4-1,4-2) is arranged on and buries in oxide layer 2 and around P type source region 3-1, the back of the body P type source region 13-1 of gate MOSFET and the surrounding of P type source region isolated area 14-1 of N-type channel region 12, P type drain region 11, front gate MOSFET;

Arrange near a side of N-type channel region 12 one compared with heavy doping P type semiconductor district as front grid and the back of the body the shared P type drain region 11 of gate MOSFET, junction depth is darker; Opposite side arrange upper and lower two compared with heavy doping P type semiconductor district respectively as the P type source region 13-1 of the P type source region 3-1 of front gate MOSFET and back of the body gate MOSFET, the junction depth summation thickness of the P type source region 13-1 of the P type source region 3-1 of front gate MOSFET and back of the body gate MOSFET is less than the thickness of N-type channel region 12 or deep trench isolation region (4-1,4-2); Thereby a dielectric area or N-type district formation P type source region isolated area 14-1 are set between the P of front gate MOSFET type source region 3-1 and the P type source region 13-1 of back of the body gate MOSFET, and described P type source region isolated area 14-1 forms the isolation of the P type source region 13-1 to the P type source region 3-1 of front gate MOSFET and back of the body gate MOSFET; Skim lateral oxidation layer is arranged on N-type channel region 12 as gate oxide 9, and the top of part, N-type channel region 12 that covers 11 tops, P type drain region is whole, the part at the 3-1 top, P type source region of front gate MOSFET; One polysilicon layer is arranged on gate oxide 9 as mos gate 8;

3-1 top, a P type source region part whole at 4-1 top, deep trench isolation region, front gate MOSFET covers the first field oxide 5-1; Cover the second field oxide 5-2 in 3-1 top, the P of a front gate MOSFET type source region part, gate oxide 9 one sides, mos gate 8 one sides, mos gate 8 top parts; Cover the 3rd field oxide 5-3 in mos gate 8 top parts, mos gate 8 one sides, gate oxide 9 one sides, P type drain region 11 top parts; All cover the 4th field oxide 5-4 at P type drain region 11 top parts, 4-2 top, deep trench isolation region; The remainder covering metal layer at the 3-1 top, P type source region of front gate MOSFET is as source electrode 6, the top of source electrode 6 cover part the first field oxide 5-1, the top of part the second field oxide 5-2; The remainder covering metal layer at mos gate 8 tops is as gate electrode 7, the top of gate electrode 7 cover part the second field oxide 5-2, the top of part the 3rd field oxide 5-3; The remainder covering metal layer at 11 tops, N-type drain region is as drain electrode 10, the top of drain electrode 10 cover parts the 3rd field oxide 5-3, the top of part the 4th field oxide 5-4.

The beneficial effects of the utility model are: SOI P-MOSFET device source (leakage) district is transformed, in source, (leakage) district forms PN junction or dielectric capacitance, take the front grid P-MOSFET radio-frequency (RF) switch ultra-low loss device of drain region medium (PN junction) isolation based on SOI technique as example, source region junction depth is darker, in the middle of drain region, manufacture the doping of P type or medium, form PN junction or dielectric capacitance, form apply the isolation of direct current biasing in drain region, pass through body, the setting of back of the body gate bias, make to carry on the back gate MOSFET raceway groove and enter conducting, front grid P-MOSFET drain region AC signal is coupled on back of the body gate MOSFET, because back of the body gate MOSFET works in conducting state, this structure forms and adjusts the impedance under front gate MOSFET ON state, front grid P-MOSFET is reduced as the radio frequency loss under the application of switch ON state, ultra-low loss radio-frequency (RF) switch, in the time that device self-heating effect produces, causes carrying on the back gate MOSFET formation negative impedance, maybe, in the time that back of the body gate MOSFET works in magnifying state, front grid coupled signal can directly be amplified, and the energy loss under grid ON state before compensation, and loss is further reduced.

This device has the feature of front grid, the direct current signal isolation of back of the body gate MOSFET source (leakage) district, with single device, formation ultra-low loss switch application, than adopting compensating circuit method for designing, there is lower power consumption, more small size, low cost more, be compatible with standard SOI technique, technique is easy to the features such as realization simultaneously.

Accompanying drawing explanation

Fig. 1 is grid P-MOSFET radio-frequency (RF) switch ultra-low loss device before a kind of drain region medium/PN junction isolation based on SOI technique;

Fig. 2 is grid P-MOSFET radio-frequency (RF) switch ultra-low loss device before a kind of source region medium/PN junction isolation based on SOI technique.

Embodiment

Below in conjunction with the drawings and specific embodiments, the utility model is described further.

As shown in Figure 1, grid P-MOSFET radio-frequency (RF) switch ultra-low loss device before the isolation of drain region medium based on SOI technique/PN junction, comprises P type semiconductor substrate 1, buries oxide layer 2, the P type drain region 13 of the P type drain region 11 of N-type channel region 12, P type source region 3, front gate MOSFET, back of the body gate MOSFET, P type drain region isolated area 14 and deep trench isolation region (4-1,4-2); Burying oxide layer 2 covers on P type semiconductor substrate 1, N-type channel region 12 is arranged on buries in oxide layer 2, and deep trench isolation region 4-1,4-2 are arranged on and bury in oxide layer 2 and around P type drain region 11, the back of the body P type drain region 13 of gate MOSFET and the surrounding of P type drain region isolated area 14 of N-type channel region 12, P type source region 3, front gate MOSFET;

As shown in Figure 2, grid P-MOSFET radio-frequency (RF) switch ultra-low loss device before the isolation of source region medium based on SOI technique/PN junction, comprises P type semiconductor substrate 1, buries oxide layer 2, N-type channel region 12, P type drain region 11, the P type source region 3-1 of front gate MOSFET, P type source region 13-1, P type source region isolated area 14-1 and deep trench isolation region (4-1, the 4-2) of back of the body gate MOSFET; Burying oxide layer 2 covers on P type semiconductor substrate 1, N-type channel region 12 is arranged on buries in oxide layer 2, and deep trench isolation region 4-1,4-2 are arranged on and bury in oxide layer 2 and around P type source region 3-1, the back of the body P type source region 13-1 of gate MOSFET and the surrounding of P type source region isolated area 14-1 of N-type channel region 12, P type drain region 11, front gate MOSFET;

The utility model is transformed SOI P-MOSFET device source (leakage) district, in source, (leakage) district forms PN junction or dielectric capacitance, take the front grid P-MOSFET radio-frequency (RF) switch ultra-low loss device of drain region medium (PN junction) isolation based on SOI technique as example, source region junction depth is darker, in the middle of drain region, manufacture the doping of P type or medium, form PN junction or dielectric capacitance, form apply the isolation of direct current biasing in drain region, pass through body, the setting of back of the body gate bias, make to carry on the back gate MOSFET raceway groove and enter conducting, front grid P-MOSFET drain region AC signal is coupled on back of the body gate MOSFET, because back of the body gate MOSFET works in conducting state, this structure forms and adjusts the impedance under front gate MOSFET ON state, front grid P-MOSFET is reduced as the radio frequency loss under the application of switch ON state, ultra-low loss radio-frequency (RF) switch, in the time that device self-heating effect produces, causes carrying on the back gate MOSFET formation negative impedance, maybe, in the time that back of the body gate MOSFET works in magnifying state, front grid coupled signal can directly be amplified, and the energy loss under grid ON state before compensation, and loss is further reduced.

The above is only preferred implementation of the present utility model; it should be pointed out that for those skilled in the art, without departing from the concept of the premise utility; can also make some improvements and modifications, these improvements and modifications also should be considered as in the utility model protection range.

Claims

1. grid P-MOSFET radio-frequency (RF) switch ultra-low loss device before the isolation of the drain region medium (PN junction) based on SOI technique, it is characterized in that, comprise P type semiconductor substrate (1), bury oxide layer (2), the P type drain region (13) of the P type drain region (11) of N-type channel region (12), P type source region (3), front gate MOSFET, back of the body gate MOSFET, P type drain region isolated area (14) and deep trench isolation region (4-1,4-2); Burying oxide layer (2) covers on P type semiconductor substrate (1), N-type channel region (12) is arranged on that to bury oxide layer (2) upper, and deep trench isolation region (4-1,4-2) is arranged on that to bury oxide layer (2) upper and around P type drain region (11), the back of the body P type drain region (13) of gate MOSFET and the surrounding of P type drain region isolated area (14) of N-type channel region (12), P type source region (3), front gate MOSFET;

Arrange near a side of N-type channel region (12) one compared with heavy doping P type semiconductor district as front grid and the back of the body the shared P type source region (3) of gate MOSFET, junction depth is darker; Opposite side arrange upper and lower two compared with heavy doping P type semiconductor district respectively as the P type drain region (13) of the P type drain region (11) of front gate MOSFET and back of the body gate MOSFET, the P type drain region (11) of front gate MOSFET and the junction depth summation thickness of carrying on the back the P type drain region (13) of gate MOSFET are less than the thickness of N-type channel region (12) or deep trench isolation region (4-1,4-2); In the P type drain region (13) of the P of front gate MOSFET type drain region (11) and back of the body gate MOSFET thus between a dielectric area or N-type district be set form P type drain region isolated area (14), described P type drain region isolated area (14) is to front grid P type drain region (11) and carry on the back the isolation in grid P type drain region (13); It is upper that skim lateral oxidation layer is arranged on N-type channel region (12) as gate oxide (9), and the top of part, N-type channel region (12) that covers top, P type source region (3) is whole, the part at the top, P type drain region (11) of front gate MOSFET; One polysilicon layer is arranged on gate oxide (9) as mos gate (8);

In deep trench isolation region, (4-1) top all, top, P type source region (3) part covers the first field oxide (5-1); Cover the second field oxide (5-2) in top, P type source region (3) part, gate oxide (9) one sides, mos gate (8) one sides, mos gate (8) top part; At the top, P type drain region (11) of mos gate (8) top part, mos gate (8) one sides, gate oxide (9) one sides, front gate MOSFET, a part covers the 3rd field oxide (5-3); All cover the 4th field oxide (5-4) at top, the P of front gate MOSFET type drain region (11) part, top, deep trench isolation region (4-2); The remainder covering metal layer at top, P type source region (3) is as source electrode (6), the top of the top of source electrode (6) cover part the first field oxide (5-1), part the second field oxide (5-2); The remainder covering metal layer at mos gate (8) top is as gate electrode (7), the top of the top of gate electrode (7) cover part the second field oxide (5-2), part the 3rd field oxide (5-3); The remainder covering metal layer at the top, P type drain region (11) of front gate MOSFET is as drain electrode (10), the top of drain electrode (10) cover part the 3rd field oxide (5-3), the top of part the 4th field oxide (5-4).

2. grid P-MOSFET radio-frequency (RF) switch ultra-low loss device before the isolation of the source region medium (PN junction) based on SOI technique, it is characterized in that, comprise P type semiconductor substrate (1), bury oxide layer (2), the P type source region (13-1) of the P type source region (3-1) of N-type channel region (12), P type drain region (11), front gate MOSFET, back of the body gate MOSFET, P type source region isolated area (14-1) and deep trench isolation region (4-1,4-2); Burying oxide layer (2) covers on P type semiconductor substrate (1), N-type channel region (12) is arranged on that to bury oxide layer (2) upper, and deep trench isolation region (4-1,4-2) is arranged on that to bury oxide layer (2) upper and around P type source region (3-1), the back of the body P type source region (13-1) of gate MOSFET and the surrounding of P type source region isolated area (14-1) of N-type channel region (12), P type drain region (11), front gate MOSFET;

Arrange near a side of N-type channel region (12) one compared with heavy doping P type semiconductor district as front grid and the back of the body the shared P type drain region (11) of gate MOSFET, junction depth is darker; Opposite side arrange upper and lower two compared with heavy doping P type semiconductor district respectively as the P type source region (13-1) of the P type source region (3-1) of front gate MOSFET and back of the body gate MOSFET, the P type source region (3-1) of front gate MOSFET and the junction depth summation thickness of carrying on the back the P type source region (13-1) of gate MOSFET are less than the thickness of N-type channel region (12) or deep trench isolation region (4-1,4-2); In the P type source region (13-1) of the P of front gate MOSFET type source region (3-1) and back of the body gate MOSFET thus between a dielectric area or N-type district be set form P type source region isolated area (14-1), described P type source region isolated area (14-1) forms the P type source region (3-1) to front gate MOSFET and carries on the back the isolation in the P type source region (13-1) of gate MOSFET; It is upper that skim lateral oxidation layer is arranged on N-type channel region (12) as gate oxide (9), and the top of part, N-type channel region (12) that covers top, P type drain region (11) is whole, the part at the top, P type source region (3-1) of front gate MOSFET; One polysilicon layer is arranged on gate oxide (9) as mos gate (8);

In deep trench isolation region, (4-1) top top, P type source region (3-1) parts whole, front gate MOSFET cover the first field oxide (5-1); Cover the second field oxide (5-2) in top, the P of front gate MOSFET type source region (3-1) part, gate oxide (9) one sides, mos gate (8) one sides, mos gate (8) top part; Cover the 3rd field oxide (5-3) in mos gate (8) top part, mos gate (8) one sides, gate oxide (9) one sides, top, P type drain region (11) part; All cover the 4th field oxide (5-4) at top, P type drain region (11) part, top, deep trench isolation region (4-2); The remainder covering metal layer at the top, P type source region (3-1) of front gate MOSFET is as source electrode (6), the top of the top of source electrode (6) cover part the first field oxide (5-1), part the second field oxide (5-2); The remainder covering metal layer at mos gate (8) top is as gate electrode (7), the top of the top of gate electrode (7) cover part the second field oxide (5-2), part the 3rd field oxide (5-3); The remainder covering metal layer at top, N-type drain region (11) is as drain electrode (10), the top of drain electrode (10) cover part the 3rd field oxide (5-3), the top of part the 4th field oxide (5-4).