CN112820775A - SOI-LDMOS device with electron accumulation effect - Google Patents

SOI-LDMOS device with electron accumulation effect Download PDF

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CN112820775A
CN112820775A CN202110018192.9A CN202110018192A CN112820775A CN 112820775 A CN112820775 A CN 112820775A CN 202110018192 A CN202110018192 A CN 202110018192A CN 112820775 A CN112820775 A CN 112820775A
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region
isolation layer
ldmos
soi
drain
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陈伟中
黄元熙
黄垚
李顺
黄义
张红升
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Chongqing University of Post and Telecommunications
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Chongqing University of Post and Telecommunications
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    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors

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Abstract

The invention relates to an SOI-LDMOS device with an electron accumulation effect, and belongs to the technical field of semiconductors. The device comprises an LDMOS structure, a PNP structure, an oxidation isolation layer, metal aluminum and a substrate; the LDMOS structure is positioned in front of the oxidation isolation layer and sequentially comprises a source electrode P + region, a source electrode N + region, a P-body, a drift region and a drain electrode N + region from left to right; the PNP structure is positioned behind the oxidation isolation layer and sequentially comprises a grid electrode P + region, a grid electrode P region, a drift region, a drain electrode N + region and a drain electrode P + region from left to right; the metal aluminum is arranged at the upper right corner of the oxidation isolation layer and is connected with the drain N + region in front of the oxidation isolation layer and the drain P + region behind the oxidation isolation layer; and a substrate is arranged right below the P-body, the grid P + region, the grid P region, the drift region and the oxidation isolation layer. The device of the invention reduces the specific on-resistance Ron,spMeanwhile, the breakdown voltage can be kept high.

Description

SOI-LDMOS device with electron accumulation effect
Technical Field
The invention belongs to the technical field of semiconductors, and relates to an SOI-LDMOS device with an electron accumulation effect.
Background
As the demand for power semiconductor devices continues to increase, the development of power semiconductor devices is promoted. The lateral double-diffused field effect transistor (LDMOS) used for processing medium-low power plays a very important role in the process, and the manufacturing process of the LDMOS can be compatible with the traditional CMOS process, and the manufacturing process is simple and has good stability. Since the LDMOS is a voltage-controlled device, the input impedance is high and the driving circuit is much easier compared to a device controlled by current (e.g. power bipolar transistor, conventional thyristor). And it only has the majority carrier conduction and no minority carrier storage effect, and can obtain higher switching speed, so that its working frequency can have higher working frequency than other devices whose several carriers are conductive. These advantages of LDMOS also make it extremely competitive in the power semiconductor industry, while driving the benign development of power semiconductor devices. The LDMOS is used for carrying out medium-low power processing, so that the electric energy can be utilized more efficiently, the energy is saved, and the effect is improved.
In addition, due to the unique structural characteristics of the SOI (Silicon-On-Insulator) base substrate, the defects of a plurality of bulk Silicon materials are overcome, and the potential of the Silicon integrated circuit technology can be fully exerted when the SOI substrate is used in an integrated circuit. High Voltage Integrated Circuits (HVICs) based on SOI substrates integrate SOI technology, microelectronics and power electronics, and thus are rapidly developed, and have a very wide application prospect in weaponry, aerospace, industrial automation, power electronics and other High and new technology industries. One of the cornerstone and core portions of an SOI HVIC is an SOI-LDMOS (silicon-on-insulator-Metal-Oxide-Semiconductor) device, which has a major problem in the current time in the specific on-resistance Ron,sp∝BV2.5. In order to achieve a high Breakdown Voltage (BV), a long and low concentration lateral drift region is inevitably required, and hence the specific on-resistance (R) of the deviceon,sp) Higher, BV and Ron,spThe contradiction between the two methods is more prominent. To better measure the overall performance of the device, a Baliga figure of merit was usedBecomes an important index FOM (figure of merit) for evaluating devices, wherein FOM is BV2/Ron,sp。
In order to solve this contradiction, break through the electrical performance limit of the silicon device, a structure with an electron accumulation effect is needed, and a larger FOM can be obtained by reducing the specific on-resistance of the device and keeping a higher BV.
Disclosure of Invention
Accordingly, the present invention is directed to an SOI-LDMOS device with electron accumulation effect, which reduces the specific on-resistance Ron,spMeanwhile, the breakdown voltage can be kept high.
In order to achieve the purpose, the invention provides the following technical scheme:
an SOI-LDMOS device having an electron accumulation effect, comprising: the structure comprises an LDMOS structure, a PNP structure, an oxidation isolation layer 6, metal aluminum 9, a buried oxide layer 11 and a substrate 12;
the LDMOS structure is positioned in front of the oxidation isolation layer 6 and sequentially comprises a source electrode P + region 1, a source electrode N + region 2, a P-body3, a drift region 7 and a drain electrode N + region 8 from left to right;
the PNP structure is positioned behind the oxidation isolation layer 6 and sequentially comprises a grid electrode P + region 4, a grid electrode P region 5, a drift region 7, a drain electrode N + region 8 and a drain electrode P + region 10 from left to right;
the metal aluminum 9 is arranged at the upper right corner of the oxidation isolation layer 6 and is connected with a drain N + region 8 in front of the oxidation isolation layer 6 and a drain P + region 10 behind the oxidation isolation layer 6; a buried oxide layer 11 is arranged right below the P-body3, the grid P + region 4, the grid P region 5, the drift region 7 and the oxidation isolation layer 6; directly below the buried oxide layer 11 is a substrate 12.
Optionally, the SOI-LDMOS device may add a structure identical to the PNP structure in front of the LDMOS structure in front of the oxide isolation layer 6 to form a structure in which two PNP structures sandwich the LDMOS structure.
Optionally, the SOI-LDMOS device may be provided with a gate oxide layer 13 and a gate electrode on the upper surface of the P-body3 between the source N + region 2 and the drift region 7 in front of the oxide isolation layer 6.
Optionally, the drift region 7 of the SOI-LDMOS device located in front of the oxide isolation layer 6 or behind the oxide isolation layer 6 can be added with a P-type region 14, and the RESURF technology is used for improving the performance of the device.
Optionally, the SOI-LDMOS device may add a super junction P-type region 15 in the drift region 7 located in front of the oxide isolation layer 6 or behind the oxide isolation layer 6, and the super junction technology is used to improve the device performance.
Alternatively, the SOI-LDMOS device may not use the buried oxide layer 11, with the substrate 12 in direct contact with the drift region 7.
Optionally, the SOI-LDMOS device structure is also suitable for a VDMOS device or an IGBT device.
Alternatively, the doping concentration of the gate P + region 4 may be varied as desired.
Alternatively, the gate P + region 4 may be changed to other conductive materials as desired, including but not limited to aluminum and polysilicon.
Alternatively, the aluminum metal 9 may be changed to other conductive materials as needed, including but not limited to polysilicon, highly doped N-type silicon, and highly doped P-type silicon, and the aluminum metal 9 may change the contact area with the drain N + region 8 and the drain P + region 10 as needed.
Alternatively, the drain N + region 8 and the drain P + region 10 may have their doping concentrations and structural sizes changed as needed.
Alternatively, the thickness of the PNP structure in the Z direction behind the oxide isolation layer 6 can be changed as desired.
Alternatively, the thickness of the oxidation isolation layer 6 in the Z direction may be changed as needed.
Alternatively, the LDMOS structure located in front of the oxide isolation layer 6 may be sandwiched by the PNP structure behind the oxide isolation layer 6.
The invention has the beneficial effects that: the device of the invention separates the traditional LDMOS device by the oxidation isolation layer in the Z direction, so that the upper part of the buried oxide layer of the LDMOS device can be divided into three parts, namely the oxidation isolation layer, a PNP structure behind the oxidation isolation layer and an LDMOS structure in front of the oxidation isolation layer. When the device is in forward conduction, a gate voltage is added to the gate P + region, the PN junctions of the P-body and the drift region are forward biased, and the PN junctions of the drain N + region and the drain P + region are reverse biased, so that the voltage of the gate voltage from the gate P + region to the drain N + region behind the oxidation isolation layer is reduced little through the voltage of the P-body and the drift region in front of the oxidation isolation layer, an electron accumulation layer is formed in the P-body and the drift region close to the oxidation isolation layer when the device is in forward conduction, the specific conduction resistance of the device is greatly reduced, and the gate and the drain are also not in conduction due to the existence of the PN reverse biased junctions of the drain N + region and the drain P + region. When the device is turned off, PN junctions of the drain N + region and the drain P + region are forward biased, and the whole device is the reverse biased PN junction withstand voltage of the P-body and the drift region. Meanwhile, the parameters of the P-body, the drift region and the drain electrode N + region on the two sides of the oxidation isolation layer are the same, so that the voltage change of the same position before and after the oxidation isolation layer is not large, the oxidation isolation layer of the drift region cannot be broken down in advance, and a larger breakdown voltage can still be obtained.
The invention greatly reduces the specific on-resistance of the device and enables the device to have larger breakdown voltage. The irreconcilable contradiction between the on-resistance and the voltage resistance of the traditional MOSFET is solved, and the silicon limit is broken.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the means of the instrumentalities and combinations particularly pointed out hereinafter.
Drawings
For the purposes of promoting a better understanding of the objects, aspects and advantages of the invention, reference will now be made to the following detailed description taken in conjunction with the accompanying drawings in which:
FIG. 1 is a schematic structural view of an SOI-LDMOS device of embodiment 1;
FIG. 2 is a schematic structural view of an SOI-LDMOS device of embodiment 2;
FIG. 3 is a schematic structural view of an SOI-LDMOS device of embodiment 3;
FIG. 4 is a schematic structural view of an SOI-LDMOS device of embodiment 4;
FIG. 5 is a schematic structural view of an SOI-LDMOS device of embodiment 5;
FIG. 6 shows the SOI-LDMOS device of example 1 with the new structure and the conventional SOI-LDMOS device having the drift region doping concentration of 2 × 1015cm-3To 3.8X 1015cm-3Breakdown voltage comparison graph between;
FIG. 7 shows the drift region doping concentrations of the SOI-LDMOS device (right) and the conventional SOI-LDMOS device (left) of the new structure of example 1 are 2 × 1015cm-3Distribution of electric field lines at breakdown;
FIG. 8 shows the drift region doping concentrations of the SOI-LDMOS device (right) and the conventional SOI-LDMOS device (left) of the new structure of example 1 are 2.6 × 1015cm-3Distribution of electric field lines at breakdown;
FIG. 9 shows the drift region doping concentrations of the SOI-LDMOS device (right) and the conventional SOI-LDMOS device (left) of the new structure of example 1 are 3.1 × 1015cm-3Distribution of electric field lines at breakdown;
FIG. 10 shows the drift region doping concentrations of the SOI-LDMOS device (right) and the conventional SOI-LDMOS device (left) of the new structure of example 1 are 3.6 × 1015cm-3Distribution of electric field lines at breakdown;
FIG. 11 shows the SOI-LDMOS device of example 1 with a new structure and a doping concentration of 2 × 10 in the drift region15cm-3The doping concentration of the drift region of the traditional SOI-LDMOS device is 2 multiplied by 1015cm-3、2.6×1015cm-3、3.1×1015cm-3And 3.6X 1015cm-3A drain voltage versus drain current graph of;
FIG. 12 shows the SOI-LDMOS device of example 1 with a new structure and a doping concentration of 2 × 10 in the drift region15cm-3The doping concentration of the drift region of the traditional SOI-LDMOS device is 2 multiplied by 1015cm-3、2.6×1015cm-3、3.1×1015cm-3And 3.6X 1015cm-3The transfer characteristic curve of (1);
FIG. 13 shows the drift region doping concentration of 3.1X 10 in example 115cm-3The doping concentration of the SOI-LDMOS device (right) and the drift region with the new structure is 3.1 multiplied by 1015cm-3Conventional SOI-LDMOS deviceElement (left) when conducting in the forward direction (Z ═ 0.49 μm), the current density plots for both devices, the darker the color in the drift region representing the greater the current density;
FIG. 14 shows the drift region doping concentration of 3.1X 10 in example 115cm-3The doping concentration of the SOI-LDMOS device (right) and the drift region with the new structure is 3.1 multiplied by 1015cm-3When the conventional SOI-LDMOS device (left) is conducted in the forward direction (Y is 10 mu m), the current density of the two devices is increased according to the current density graph of the two devices, wherein the deeper the color in the drift region is;
FIG. 15 shows the SOI-LDMOS device of example 1 with the new structure and the conventional SOI-LDMOS device having the drift region doping concentration of 2 × 1015cm-3To 3.8X 1015cm-3A comparison graph of specific on-resistance between;
FIG. 16 shows the SOI-LDMOS device of example 1 with the new structure and the conventional SOI-LDMOS device having the drift region doping concentration of 2 × 1015cm-3To 3.8X 1015cm-3Baliga figure of merit FOM comparison between;
fig. 17 is a voltage distribution diagram of the new SOI-LDMOS device of example 1 along the Y axis at a gate voltage of 10V and a drain voltage of 0V, where X is 0.2 μm and Z is 0.65 μm;
fig. 18 is a graph comparing electron densities of a drift region (Y13 to 17 μm) at a gate voltage of 10V and a drain voltage of 0V in the new-structure SOI-LDMOS device and the conventional SOI-LDMOS device of example 1, where X is 0.1 μm and Z is 0.49 μm;
FIG. 19 shows the breakdown states of the SOI-LDMOS device of example 1 and the conventional SOI-LDMOS device in the case of Nd ═ 3.1 × 1015cm-3Comparing the surface electric field intensity of the device at the position where X is 0.1 μm and Z is 0.3 μm;
FIG. 20 is an equivalent circuit diagram of a SOI-LDMOS device of a new structure of embodiment 1;
FIG. 21 is a schematic view showing the main process flow of the SOI-LDMOS device of embodiment 1;
reference numerals: the transistor comprises a 1-source P + region, a 2-source N + region, a 3-P-body, a 4-grid P + region, a 5-grid P region, a 6-oxidation isolation layer, a 7-drift region, an 8-drain N + region, 9-metal aluminum, a 10-drain P + region, an 11-buried oxide layer, a 12-substrate, a 13-grid oxide layer, a 14-P type region and a 15-super-junction P type region.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention in a schematic way, and the features in the following embodiments and examples may be combined with each other without conflict.
Wherein the showings are for the purpose of illustrating the invention only and not for the purpose of limiting the same, and in which there is shown by way of illustration only and not in the drawings in which there is no intention to limit the invention thereto; to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
The same or similar reference numerals in the drawings of the embodiments of the present invention correspond to the same or similar components; in the description of the present invention, it should be understood that if there is an orientation or positional relationship indicated by terms such as "upper", "lower", "left", "right", "front", "rear", etc., based on the orientation or positional relationship shown in the drawings, it is only for convenience of description and simplification of description, but it is not an indication or suggestion that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes, and are not to be construed as limiting the present invention, and the specific meaning of the terms may be understood by those skilled in the art according to specific situations.
Example 1:
as shown in FIG. 1, the SOI-LDMOS device with the electron accumulation effect of the present invention comprises a source P + region 1, a source N + region 2, a P-body3, a gate P + region 4, a gate P region 5, an oxide isolation layer 6, a drift region 7, a drain N + region 8, aluminum metal 9, a drain P + region 10, a buried oxide layer 11 and a substrate 12.
1) The upper part of the device is as follows: the upper part of the device can be divided into three parts, namely an oxidation isolation layer 6 part, an oxidation isolation layer 6 front part and an oxidation isolation layer 6 rear part. The method comprises the following specific steps:
oxidation of the barrier layer 6 part: the oxidation isolation layer mainly comprises an oxidation isolation layer 6, and metal aluminum 9 at the upper right corner of the oxidation isolation layer 6 is additionally arranged.
Front part of the oxidation isolation layer 6: this portion is a conventional LDMOS structure, which is, from left to right, a source P + region 1, a source N + region 2, a P-body3, a drift region 7, and a drain N + region 8. Wherein, the source P + region 1 and the source N + region 2 are positioned at the upper left corner of the whole region and are surrounded by the P-body 3; the right side of the P-body3 is in contact with the left side of the drift region 7; the drain N + region 8 is located in the upper right corner of the overall region, surrounded by the drift region 7.
Oxidation of the rear part of the barrier layer 6: this portion is a PNP structure, and from left to right are a gate P + region 4, a gate P + region 5, a drift region 7, a drain N + region 8, and a drain P + region 10 in that order. Wherein the right side of gate P + region 4 is in contact with the left side of gate P region 5; the right side of the gate P region 5 is in contact with the left side of the drift region 7; the drain N + region 8 is located in the upper right portion of the overall region, surrounded by the drift region 7, and also surrounds the drain P + region 10 located in the upper right corner of the overall region.
2) The middle part of the device: the device middle part is located below the device upper part and above the device bottom part, this layer consisting of a buried oxide layer 11.
3) Device bottom part: the bottom portion of the device is located below the middle portion of the device and this layer is comprised of the substrate 12.
Wherein the substrate 12 is doped silicon with a thickness of 2 μm, a width of 19 μm and a doping concentration of 8 × 1014cm-3Boron (b) in the presence of boron. The buried oxide layer 11 is silicon dioxide with a thickness of 2 μm and a width of 19 μm.
In the upper part of the device, the source P + region 1 has a length of 1 μm in the x-direction, 1 μm in the y-direction and 0.5 μm in the z-direction, and is dopedThe impurity concentration is 1X 1019cm-3(ii) a The source N + region 2 has a length of 1 μm in the x direction, a length of 1 μm in the y direction, and a length of 0.5 μm in the z direction, and has a doping concentration of 1X 1019cm-3(ii) a The length of the P-body3 in the x direction was 5 μm, the length in the y direction was 3 μm, and the length in the z direction was 0.5 μm, with a doping concentration of 1X 1017cm-3(ii) a The drift region 7 has a length of 5 μm in the x-direction, a length of 16 μm in the y-direction and a length of 0.5 μm in the z-direction, and a doping concentration of 3X 1015cm-3(ii) a The drain N + region 8 has a length of 1 μm in the x direction, a length of 2 μm in the y direction, and a length of 0.5 μm in the z direction, and has a doping concentration of 1X 1019cm-3(ii) a The length of the oxidation isolation layer 5 in the x direction is 5 μm, the length in the y direction is 19 μm, and the length in the z direction is 0.1 μm; the gate P + region 4 has a length of 5 μm in the x-direction, a length of 2 μm in the y-direction, and a length of 0.4 μm in the z-direction, and has a doping concentration of 1X 1019cm-3(ii) a The gate P region 5 has a length of 5 μm in the x direction, a length of 1 μm in the y direction, and a length of 0.4 μm in the z direction, and has a doping concentration of 1X 1017cm-3(ii) a The drain P + region 10 has a length of 0.5 μm in the x-direction, a length of 1 μm in the y-direction, and a length of 0.5 μm in the z-direction, and has a doping concentration of 1X 1019cm-3(ii) a The metallic aluminum 9 had a length of 0.2 μm in the x-direction, a length of 0.5 μm in the y-direction, and a length of 0.1 μm in the z-direction.
Example 2:
as shown in FIG. 2, the SOI-LDMOS device with the electron accumulation effect of the present invention comprises a source P + region 1, a source N + region 2, a P-body3, a gate P + region 4, a gate P region 5, an oxide isolation layer 6, a drift region 7, a drain N + region 8, aluminum metal 9, a drain P + region 10, a buried oxide layer 11 and a substrate 12.
On the basis of the structure of embodiment 1, a PNP structure identical to the PNP structure behind the oxide isolation layer 6 is added in front of the LDMOS structure in front of the original oxide isolation layer 6 to form a double-PNP structure sandwiching the LDMOS structure. The newly added PNP structure is completely consistent with the original PNP structure in terms of parameters, but can also be changed according to actual needs.
Example 3:
as shown in FIG. 3, the SOI-LDMOS device with the electron accumulation effect in the invention comprises a source P + region 1, a source N + region 2, a P-body3, a gate P + region 4, a gate P region 5, an oxidation isolation layer 6, a drift region 7, a drain N + region 8, aluminum metal 9, a drain P + region 10, a buried oxide layer 11, a substrate 12 and a gate oxide layer 13.
On the basis of the structure of embodiment 1, a gate oxide layer is further added on the upper surface of the P-body3 between the source N + region 2 and the drift region 7 and is connected with the gate, so that an electronic channel is increased when the forward conduction is performed, and the specific on-resistance is further reduced. Wherein the gate oxide layer has a thickness of 0.1 μm in the x-direction, a length of 1.4 μm in the y-direction, and a length of 0.5 μm in the z-direction.
Example 4:
as shown in FIG. 4, the SOI-LDMOS device with the electron accumulation effect of the present invention comprises a source P + region 1, a source N + region 2, a P-body3, a gate P + region 4, a gate P region 5, an oxide isolation layer 6, a drift region 7, a drain N + region 8, aluminum metal 9, a drain P + region 10, a buried oxide layer 11, a substrate 12 and a P-type region 14.
On the basis of the structure of the embodiment 1, a P-type region 14 is added in the drift region of the device, and the specific on-resistance and the breakdown voltage of the device are optimized by using a RESURF technology. The position, size and doping concentration of the P-type region 14 in the drift region can be changed according to actual conditions.
Example 5:
as shown in fig. 5, a preferred SOI-LDMOS device with an electron accumulation effect according to an embodiment of the present invention includes a source P + region 1, a source N + region 2, a P-body3, a gate P + region 4, a gate P region 5, an oxide isolation layer 6, a drift region 7, a drain N + region 8, aluminum metal 9, a drain P + region 10, a buried oxide layer 11, a substrate 12, and a super junction P-type region 15.
On the basis of the structure of embodiment 1, a super junction P-type region 15 is added in the drift region of the device, so that the doping concentration of the device can be further improved by using a super junction technology, and the specific on-resistance and the breakdown voltage of the device are optimized. The position, size and doping concentration of the super junction P-type region 15 in the drift region can be changed according to actual conditions.
Simulation experiment:
referring to fig. 6 to 21, simulation comparison between the conventional SOI-LDMOS and the novel SOI-LDMOS of embodiment 1 can be performed by using Sentaurus simulation software, and simulation parameters of the two structures are consistent during simulation, wherein the total thickness of the drift region is 5 μm, the distance between the drain and the P-body is 14 μm, the ambient temperature is 300K, and the doping concentration N of the drift region is NdThe doping concentration of the grid electrode P + region, the thickness of the oxidation isolation layer, the thickness of the LDMOS structure and the thickness of the PNP structure in the Z direction can be adjusted.
TABLE 1 basic structural parameters of two devices
Figure BDA0002887749050000071
Figure BDA0002887749050000081
FIG. 6 shows that the drift region concentration is 2X 10 at room temperature when T is 300K15cm-3To 3.8X 1015cm-3And comparing the voltage endurance of the conventional LDMOS (CON-LDMOS) with that of the SOI-LDMOS device (EA-LDMOS) with the new structure in an avalanche breakdown state. The data results obtained from the Sentaurus simulation are further plotted by the Origin tool in the comparison graphs shown in fig. 7-10, and it can be seen that: the breakdown voltage of both the CON-LDMOS and the EA-LDMOS shows a tendency of increasing and decreasing along with the increase of the concentration of the drift region, wherein the CON-LDMOS is at 2.6 multiplied by 1015cm-3Where the maximum value is reached, EA-LDMOS at 3 x 1015cm-3The maximum value is reached, and the maximum breakdown voltages of the two are not greatly different.
Fig. 15 shows that the drift region concentration is from 2 × 10 at room temperature T300K15cm-3To 3.8X 1015cm-3In the meantime, the specific on-resistance of the conventional LDMOS (CON-LDMOS) and the SOI-LDMOS device (EA-LDMOS) with the new structure are compared in the forward on state. It can be seen from fig. 15 that the specific on-resistance of the CON-LDMOS showed a rapid decrease with increasing concentration of the drift region, with a final value close to 16; in addition, the concentration of the drift region is changedThe specific on-resistance of the EA-LDMOS still shows a descending trend on the whole, but the influence of the concentration of the drift region in a range on the specific on-resistance of the EA-LDMOS is not large, because the drift region in the PNP structure has an electron accumulation effect on the drift region in the LDMOS structure when the PNP structure is conducted in the forward direction, the electron concentration in the LDMOS structure close to the oxidation isolation layer is large, namely heavy doping with large doping concentration is performed, the specific on-resistance of the device is greatly reduced, and the specific on-resistance of the EA-LDMOS in the concentration range is smaller along with the change of the concentration of the drift region.
Fig. 16 shows that the drift region concentration is from 2 × 10 at room temperature T300K15cm-3To 3.8X 1015cm-3In the meantime, the Baliga figure of merit (FOM) of the conventional LDMOS (CON-LDMOS) and the SOI-LDMOS device (EA-LDMOS) with the new structure are compared. It can be seen from FIG. 16 that FOM of the CON-LDMOS device rises first and then falls to 2.9 × 1015cm-3A maximum of 3.4MW/cm is obtained2Similarly, the FOM of the EA-LDMOS device rises first and then falls at 3X 1015cm-3A maximum of 21MW/cm is obtained2Comparing the two structures, the FOM of EA-LDMOS is much higher than that of CON-LDMOS.
TABLE 2 FOM figure of merit for two devices at different drift region doping concentrations
Figure BDA0002887749050000082
Figure BDA0002887749050000091
FIG. 17 shows the gate voltage VgWhen the drain voltage is 0V, X is 0.2 μm and Z is 0.65 μm, the potential profile of the PNP structure behind the oxide isolation layer in the Y direction is shown. It can be seen that the potentials of the gate P + region, the gate P region, the drift region and the drain N + region are all around 10V, and rapidly drop to 0V in the drain P + region. This makes the electron density in the LDMOS structure close to the oxide spacer very high, which enables a large reduction in the specific on-resistance。
FIG. 18 shows the electron density distribution of CON-LDMOS and EA-LDMOS in the drift region, when the gate voltage V isg10V, drain voltage VdThe method comprises the following steps that 0V is obtained, EA-LDMOS is selected at a position close to an oxidation isolation layer in an LDMOS structure, finally X of CON-LDMOS and EA-LDMOS is 8.9 mu m, Z is 0.49 mu m, and Y is 13-17 mu m. As can be seen from the figure, the electron density of EA-LDMOS is 5.3 × 1017cm-3Relative to CON-LDMOS electron density of 3.1 × 1015cm-3The method is greatly improved.
FIG. 19 simulates the concentration of 3.1X 10 in the drift region15cm-3And the distribution of the surface electric field of the device along the Y direction at the position of 0.1 μm and 0.3 μm of X and Z of the CON-LDMOS and the EA-LDMOS. It can be seen that the electric field distribution of the two structures is similar, but the EA-LDMOS still has a sharp electric field at the drain, and the breakdown voltages of the two structures are substantially similar.
The present invention provides an SOI-LDMOS device with electron accumulation effect, which is illustrated in fig. 1, and the main process flow thereof is shown in fig. 21. The specific implementation method comprises the following steps: firstly, adopting the processes of ion implantation, diffusion and the like to complete the P-body and drain N + region of the novel SOI-LDMOS on an SOI silicon chip; then, the manufacturing of a source electrode P + region and a grid electrode P + region is completed by using the processes of ion implantation, diffusion and the like; then, grooving and growing an oxidation isolation layer; then, the manufacturing of a source electrode N + region and a drain electrode P + region is completed by using the processes of ion implantation, diffusion and the like; and finally, punching and depositing a drain metal contact on the right upper corner of the etching oxidation isolation layer.
Finally, the above embodiments are only intended to illustrate the technical solutions of the present invention and not to limit the present invention, and although the present invention has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that modifications or equivalent substitutions may be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions, and all of them should be covered by the claims of the present invention.

Claims (10)

1. An SOI-LDMOS device having an electron accumulation effect, comprising: the structure comprises an LDMOS structure, a PNP structure, an oxidation isolation layer (6), metal aluminum (9) and a substrate (12);
the LDMOS structure is positioned in front of the oxidation isolation layer (6), and is sequentially provided with a source electrode P + region (1), a source electrode N + region (2), a P-body (3), a drift region (7) and a drain electrode N + region (8) from left to right;
the PNP structure is positioned behind the oxidation isolation layer (6), and a grid electrode P + region (4), a grid electrode P region (5), a drift region (7), a drain electrode N + region (8) and a drain electrode P + region (10) are sequentially arranged from left to right;
the metal aluminum (9) is arranged at the upper right corner of the oxidation isolation layer (6) and is connected with a drain N + region (8) in front of the oxidation isolation layer (6) and a drain P + region (10) behind the oxidation isolation layer (6); and a substrate (12) is arranged right below the P-body (3), the grid P + region (4), the grid P region (5), the drift region (7) and the oxidation isolation layer (6).
2. SOI-LDMOS device with electron accumulation effect according to claim 1, characterized in that in front of the LDMOS structure in front of the oxide isolation layer (6) a structure identical to the PNP structure is added, forming a structure with two PNP structures sandwiching the LDMOS structure.
3. SOI-LDMOS device with electron accumulation effect according to claim 1, characterized in that the gate oxide (13) and the gate are added on the upper surface of the P-body (3) between the source N + region (2) and the drift region (7) in front of the oxide isolation layer (6).
4. SOI-LDMOS device with electron accumulation effect according to claim 1, characterized in that the P-type region (14) is added in the drift region (7) located in front of the oxide isolation layer (6) or behind the oxide isolation layer (6), using RESURF technique to improve the device performance.
5. SOI-LDMOS device with electron accumulation effect according to claim 1, characterized in that a superjunction P-type region (15) is added in the drift region (7) located in front of the oxide isolation layer (6) or behind the oxide isolation layer (6), using superjunction technology to improve the device performance.
6. SOI-LDMOS device with electron accumulation effect according to any of claims 1-5, characterized in that it further comprises a buried oxide layer (11) directly under the P-body (3), the gate P + region (4), the gate P region (5), the drift region (7) and the oxide isolation layer (6), directly over the substrate (12).
7. SOI-LDMOS device with electron accumulation effect according to claim 6, characterized in that the device structure is suitable for VDMOS devices or IGBT devices.
8. SOI-LDMOS device with electron accumulation effect according to claim 6, characterized in that the gate P + region (4) has a doping concentration and a conductive material that are varied as desired; the drain N + region (8) and the drain P + region (10) change the doping concentration and the structure size of the two regions according to requirements.
9. SOI-LDMOS device with electron accumulation effect according to claim 6, characterized in that the metallic aluminum (9) changes the conductive material and the contact area with the drain N + region (8) and the drain P + region (10) as required;
10. SOI-LDMOS device with electron accumulation effect according to claim 6, characterized in that the thickness of the oxide isolation layer (6) and the PNP structure in the Z direction is varied as desired.
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