CN112466955B - Thin-layer SOI-LDMOS device with in-vivo conductive channel - Google Patents
Thin-layer SOI-LDMOS device with in-vivo conductive channel Download PDFInfo
- Publication number
- CN112466955B CN112466955B CN202011407861.3A CN202011407861A CN112466955B CN 112466955 B CN112466955 B CN 112466955B CN 202011407861 A CN202011407861 A CN 202011407861A CN 112466955 B CN112466955 B CN 112466955B
- Authority
- CN
- China
- Prior art keywords
- region
- oxide layer
- contact
- soi
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000001727 in vivo Methods 0.000 title claims description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 111
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 55
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 55
- 239000000758 substrate Substances 0.000 claims description 20
- 239000012535 impurity Substances 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 241001354791 Baliga Species 0.000 abstract description 6
- 238000005530 etching Methods 0.000 abstract description 4
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 230000005669 field effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 104
- 230000015556 catabolic process Effects 0.000 description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 230000005684 electric field Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000009826 distribution Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- 241001089723 Metaphycus omega Species 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000005253 cladding Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 238000000992 sputter etching Methods 0.000 description 2
- 238000000927 vapour-phase epitaxy Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000004576 sand Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention relates to a thin-layer SOI-LDMOS device with an internal conductive channel, belonging to the technical field of semiconductor power devices. On the basis of a traditional thin-layer SOI-LDMOS device, a surface grid is transferred into a buried oxide layer to form an internal grid, and an internal conductive channel is formed on the lower surface of a P-body. Meanwhile, silicon dioxide is etched and filled in a drift region of the device, and the device has the following advantages: when conducting in forward direction, the control ability of internal gate voltage to current is greatly improved, and transconductance g of the device mMAX Compared with the traditional device and the traditional super junction device, the field effect transistor has the advantages that 298.7% and 87.1% are respectively improved, the doping concentration of the drift region can be improved by further etching and filling silicon dioxide in the drift region, the specific on-resistance of the device is further reduced, and finally the Baliga optimal value FOM of the device is improved.
Description
Technical Field
The invention belongs to the technical field of semiconductor power devices, and relates to a thin-layer SOI-LDMOS device with an internal conductive channel.
Background
SOI technology can achieve dielectric isolation of power integrated circuits by introducing dielectric layers into the device. Compared with bulk silicon technology, the SOI technology has higher integration level, extremely smaller parasitic capacitance and better isolation performance. SOI technology can greatly improve the reliability of integrated circuits, and will become a key technology in the future of manufacturing chips with high integration, high reliability, high speed and low power consumption, especially for power integrated circuits. Compared with most other novel active devices such as HEMT, HBT and the like, the LDMOS device (SOI-LDMOS: si-On-insulator lateral-diffused metal-Oxide-Semiconductor) based On the silicon-On-insulator technology has the characteristics of better CMOS process compatibility and convenient integration, and has high power, high gain, high linearity, high switching characteristic, good isolation performance, excellent radiation resistance and reliability, so the LDMOS device is widely concerned by industry workers, and the research taking SOI-LDMOS as an object has very special significance. It is mainly applied to: smart Power Integrated Circuit (SPIC), radio Frequency Integrated Circuit (RFIC), and High Voltage Integrated Circuit (HVIC).
The voltage endurance of the SOI lateral power device is determined by the smaller lateral breakdown voltage and longitudinal breakdown voltage. Generally, increasing the lateral length of the device and reducing the doping concentration of the drift region can improve the lateral withstand voltage capability of the device, but at the same time, the on-resistance of the device is increased, so that the forward on-performance of the device is reduced. However, the buried oxide layer and the top silicon layer of the SOI device cannot be too thick, which may cause difficulty in manufacturing the device, aggravation of self-heating phenomenon of the device, and heat dissipation problems if the buried oxide layer and the top silicon layer are too thick. When the buried oxide layer and the top silicon layer of the SOI device are too thin, the longitudinal voltage endurance capability of the device is reduced because the buried oxide layer prevents the depletion region of the device from extending to the substrate, so that the substrate cannot withstand voltage. The main contradiction of the device is that the specific on-resistance Ron, sp and the breakdown voltage BV: ron, sp ^ BV 2.5 . The specific on-resistance of the device is reduced by improving the doping concentration of the N-type layer of the drift region, but the breakdown voltage of the device is sharply reduced; the breakdown voltage of the device is improved, and the specific on-resistance of the device is increased. In order to better measure the overall performance index of the device, the figure of merit FOM (figure of merit) using Baliga figure of merit evaluation device has become an important performance index, i.e. FOM = BV 2 The larger the value FOM of the better the overall performance of the device is, the better the performance of the device is.
In order to solve the contradiction, the invention provides a thin-layer SOI-LDMOS device with an in-vivo conductive channel, and the device can improve the doping concentration of an N-type layer in a drift region by introducing a silicon dioxide dielectric region into the drift region, thereby reducing the specific on-resistance of the device. Meanwhile, the surface grid of the device is transferred to the internal grid of the buried oxide layer forming body, so that the injection capability of electrons is greatly improved, and the control capability of the grid voltage of the device on the current is enhanced.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a thin-layer SOI-LDMOS device with an in-body conductive channel, which can optimize electric field distribution of a drift region, increase doping concentration of an N-type layer of the drift region, and further reduce specific on-resistance of the device, and meanwhile, control the channel to be turned on by a gate voltage in a body, so as to enhance electron injection capability, thereby improving current control capability of the gate voltage.
In order to achieve the purpose, the invention provides the following technical scheme:
a thin-layer SOI-LDMOS device with an in-vivo conductive channel comprises a source contact region (1), a source P + region (2), an N-type drift region (3), a field oxide layer (4), a silicon dioxide dielectric region (5), a drain contact region (6), a drain N + region (7), a buried oxide layer (8), a substrate (9), an in-vivo gate oxide layer (10), a P-body (11), an in-vivo gate contact region (12) and a source N + region (13). The source electrode contact region (1) is positioned above the source electrode N + region (13) and the source electrode P + region (2), and the right side of the source electrode contact region (1) is closely adjacent to the left side of the field oxide layer (4); the upper side of the source P + region (2) is bordered by the lower side of the source contact region (1), the lower side and the left side of the source P + region (2) are contacted with the source N + region (13), and meanwhile, the right side of the source P + region (2) is contacted with a part of the left side of the P-body (11); the upper side of the N-type drift region (3) is adjacent to the lower side of the silicon dioxide dielectric region (5), the left side of the N-type drift region is in contact with the right lower side of the P-body (11), the right side of the N-type drift region is adjacent to the left lower side of the drain electrode N + region (7), and the lower side of the N-type drift region is in contact with the upper side of the buried oxide layer (8); the field oxide layer (4) is positioned on the upper side of the P-body (11) and the silicon dioxide dielectric region (5), the right side of the field oxide layer is close to the left side of the drain contact region (6), and the left side of the field oxide layer is in contact with the right side of the source contact region (1); the lower side of the silicon dioxide dielectric region (5) is in contact with the upper side of the N-type drift region (3), the left side of the silicon dioxide dielectric region is adjacent to the upper right side of the P-body (11), the right side of the silicon dioxide dielectric region is adjacent to the upper left side of the drain electrode N + region (7), and meanwhile, the upper side of the silicon dioxide dielectric region is in contact with the lower side of the field oxide layer (4); the drain contact region (6) is positioned right above the drain N + region (7), and the left side of the drain contact region (6) is adjacent to the right side of the field oxide layer (4); the drain electrode N + region (7) is positioned right below the drain electrode contact region (6), meanwhile, the left side of the drain electrode N + region is contacted with the silicon dioxide dielectric region (5) and the right side of the N-type drift region (3), and the lower side of the drain electrode N + region (7) is adjacent to the upper right side of the buried oxide layer (8); the lower side of the buried oxide layer (8) is close to the upper side of the substrate (9), the upper side of the buried oxide layer (8) is adjacent to the drain electrode N + region (7) and the lower side of the N-type drift region (3), meanwhile, the upper left side of the buried oxide layer (8) is close to the lower side of the in-body gate contact region (12), and the upper left side of the buried oxide layer (8) is in contact with the right sides of the in-body gate oxide layer (10) and the in-body gate contact region (12); the upper side of the substrate (9) is in contact with the lower side of the buried oxide layer (8), and the substrate is positioned at the bottom of the device; the lower edge of the internal gate oxide layer (10) is in contact with the upper edge of the internal gate contact region (12), the right side of the internal gate oxide layer is in contact with the buried oxide layer (8), and meanwhile, the upper edge of the internal gate oxide layer (10) is in contact with the lower edges of the source N + region (13) and the P-body (11); the left side of the P-body (11) is contacted with the right sides of the source N + region (13) and the source P + region (2), meanwhile, the upper side of the P-body is adjacent to the lower left side of the field oxide layer (4), and the lower side of the P-body is contacted with the upper right side of the in-vivo gate oxide layer (10); the in-body gate contact region (12) is positioned on the upper left side of the buried oxide layer (8) and the lower side of the in-body gate oxide layer (10), and the right side of the in-body gate contact region is in contact with the buried oxide layer (8). The upper left side of the source electrode N + region (13) is in contact with the lower side of the source electrode contact region (1), the lower side of the source electrode N + region (13) is in contact with the upper side of the in-vivo gate oxide layer (10), the source electrode N + region is L-shaped, meanwhile, the rightmost side of the source electrode N + region (13) is in contact with the left lower side of the P-body (11), and the source electrode N + region (13) is also in contact with the lower side and the left side of the source electrode P + region (2).
Optionally, the thickness of the silicon dioxide dielectric region (5) is 0.2-0.8 μm, which can be adjusted.
Optionally, the in-body gate contact region (12) is doped polysilicon and metal.
Optionally, the N-type drift region (3) is doped with N-type impurities with a doping concentration range of 5 × 10 15 ～5×10 16 cm -3 。
The invention has the beneficial effects that: according to the thin-layer SOI-LDMOS device with the in-body channel, the surface grid electrode of the device is transferred to the in-body grid electrode formed by the buried oxide layer, and meanwhile, a silicon dioxide medium region is formed in the N-type drift region through ion etching and medium filling. Firstly, when the grid electrode in the body is conducted in the forward direction, the capability of injecting electrons into the N-type drift region is greatly improved by the grid electrode in the body, and therefore the control capability of grid voltage to current (transconductance g) is improved m Increase); the silicon dioxide dielectric region can effectively improve the doping concentration of the N-type drift regionAnd the on-resistance of the N-type drift region is reduced, so that the forward on-performance of the device is optimized. Secondly, during breakdown, the silicon dioxide dielectric region can optimize the electric field distribution of the N-type drift region, so that the N-type drift region can be completely depleted. In conclusion, the surface grid is transferred to the buried oxide layer to form the internal grid, and the drift region is etched and filled with silicon dioxide, so that the Baliga optimal value FOM of the device is improved.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the means of the instrumentalities and combinations particularly pointed out hereinafter.
Drawings
For the purposes of promoting a better understanding of the objects, aspects and advantages of the invention, reference will now be made to the following detailed description taken in conjunction with the accompanying drawings in which:
FIG. 1 is a schematic structural diagram of a thin-layer SOI-LDMOS device according to embodiment 1 of the present invention;
FIG. 2 is a schematic structural diagram of a thin-layer SOI-LDMOS device according to embodiment 2 of the present invention;
FIG. 3 is a schematic structural diagram of a thin-layer SOI-LDMOS device according to embodiment 3 of the present invention;
FIG. 4 is a comparison graph of transfer characteristic curve and transconductance of the SOI-LDMOS device with the new structure, the conventional SOI-LDMOS device and the conventional super junction SOI-LDMOS device under forward conduction;
FIG. 5 is a comparison graph of output characteristic curves of the SOI-LDMOS device with the new structure, the conventional SOI-LDMOS device and the conventional super-junction SOI-LDMOS device under forward conduction, provided by the invention;
FIG. 6 is a comparison graph of the turn-on voltages of the SOI-LDMOS device with the new structure, the conventional SOI-LDMOS device and the conventional super-junction SOI-LDMOS device provided by the present invention;
FIG. 7 shows that the doping concentration of the SOI-LDMOS device with the new structure in the N-type drift region is 1.2 × 10 16 cm -3 、1.4×10 16 cm -3 、1.6×10 16 cm -3 、1.8×10 16 cm -3 、2.0×10 16 cm -3 And 2.2X 10 16 cm -3 The variation curves of the breakdown voltage BV and the specific on-resistance Ron and sp are obtained;
FIG. 8 is a variation curve of the breakdown voltage BV and the specific on-resistance Ron, sp of the SOI-LDMOS device with the new structure provided by the present invention when the thicknesses of the silicon dioxide dielectric regions are 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm and 0.8 μm;
FIG. 9 shows current line patterns of the SOI-LDMOS device with the new structure and the conventional SOI-LDMOS device, and the conventional super-junction SOI-LDMOS device in the forward conduction state; (a) is SOI-LDMOS with a new structure; (b) is a conventional SOI-LDMOS; (c) is a traditional super junction SOI-LDMOS;
FIG. 10 is a comparison graph of two-dimensional electric field intensity at Y =0.7 μm in breakdown state of the SOI-LDMOS device, the conventional SOI-LDMOS device and the conventional super-junction SOI-LDMOS device with the new structure provided by the present invention;
FIG. 11 is an equipotential line distribution diagram of a new structure SOI-LDMOS device, a conventional SOI-LDMOS device and a conventional super-junction SOI-LDMOS device provided by the present invention in a breakdown state; (a) is SOI-LDMOS with a new structure; (b) is a conventional SOI-LDMOS; (c) is a traditional super junction SOI-LDMOS;
FIG. 12 is a process flow diagram of the present invention; (a) Etching, oxidizing by dry oxygen, and filling to form a trench gate; (b) vapor phase epitaxy, ion implantation; (c) For depositing SiO 2 A protective layer; and (d) depositing a metal contact.
Reference numerals: the source electrode comprises a source electrode contact region 1, a source electrode P + region 2, an N-type drift region 3, a field oxide layer 4, a silicon dioxide dielectric region 5, a drain electrode contact region 6, a drain electrode N + region 7, a buried oxide layer 8, a substrate 9, an internal grid oxide layer 10, a P-body11, an internal grid contact region 12 and a source electrode N + region 13.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention in a schematic way, and the features in the following embodiments and examples may be combined with each other without conflict.
Wherein the showings are for the purpose of illustrating the invention only and not for the purpose of limiting the same, and in which there is shown by way of illustration only and not in the drawings in which there is no intention to limit the invention thereto; to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
The same or similar reference numerals in the drawings of the embodiments of the present invention correspond to the same or similar components; in the description of the present invention, it should be understood that if there is an orientation or positional relationship indicated by terms such as "upper", "lower", "left", "right", "front", "rear", etc., based on the orientation or positional relationship shown in the drawings, it is only for convenience of description and simplification of description, but it is not an indication or suggestion that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes, and are not to be construed as limiting the present invention, and the specific meaning of the terms may be understood by those skilled in the art according to specific situations.
Example 1:
as shown in fig. 1, the thin-layer SOI-LDMOS device with an in-body channel is characterized in that the device structure mainly comprises a source contact region 1, a source P + region 2, an N-type drift region 3, a field oxide layer 4, a silicon dioxide dielectric region 5, a drain contact region 6, a drain N + region 7, a buried oxide layer 8, a substrate 9, an in-body gate oxide layer 10, a P-body11, an in-body gate contact region 12 and a source N + region 13.
The source contact region 1 is positioned above the source N + region 13 and the source P + region 2, and the right side of the source contact region 1 is adjacent to the left side of the field oxide layer 4; the thickness was 0.4 μm and the length was 0.5. Mu.m.
The upper side of the source electrode P + region 2The lower side and the left side of the source P + region 2 are contacted with a source N + region 13, and the right side of the source P + region 2 is contacted with the upper left side of a P-body 11; it has a thickness of 0.2 μm and a length of 0.5 μm, and is doped with P-type impurities at a concentration of 1.0 × 10 20 cm -3 。
The upper side of the N-type drift region 3 is adjacent to the lower side of the silicon dioxide dielectric region 5, the left side of the N-type drift region is in contact with the right lower side of the P-body11, and the right side of the N-type drift region is adjacent to the left lower side of the drain electrode N + region 7; it has a thickness of 0.6 μm and a length of 7.0 μm, and is doped with N-type impurities at a concentration of 1.7X 10 16 cm -3 。
The field oxide layer 4 is positioned on the upper side of the P-body11 and the silicon dioxide dielectric region 5, the right side of the field oxide layer is adjacent to the left side of the drain contact region 6, and the left side of the field oxide layer is in contact with the right side of the source contact region 1; the thickness was 0.2 μm and the length was 8.0. Mu.m.
The lower side of the silicon dioxide dielectric region 5 is in contact with the upper side of the N-type drift region 3, the left side of the silicon dioxide dielectric region is adjacent to the upper right side of the P-body11, the right side of the silicon dioxide dielectric region is adjacent to the upper left side of the drain electrode N + region 7, and meanwhile, the upper side of the silicon dioxide dielectric region is in contact with the lower side of the field oxide layer 4; the thickness was 0.7 μm and the length was 7.0. Mu.m.
The drain contact region 6 is positioned right above the drain N + region 7, and the left side of the drain contact region 6 is adjacent to the right side of the field oxide layer 4; the thickness was 0.2 μm and the length was 1.0. Mu.m.
The drain electrode N + region 7 is positioned right below the drain electrode contact region 6, meanwhile, the left side of the drain electrode N + region is contacted with the silicon dioxide dielectric region 5 and the right side of the N-type drift region 3, and the lower side of the drain electrode N + region 7 is adjacent to the upper right side of the buried oxide layer 8; it has a thickness of 1.0 μm and a length of 1.0 μm, and is doped with N-type impurities at a concentration of 1.0X 10 20 cm -3 。
The lower side of the buried oxide layer 8 is close to the upper side of the substrate 9, the upper side of the buried oxide layer 8 is adjacent to the lower side of the drain electrode N + region 7 and the lower side of the N-type drift region 3, meanwhile, the upper left side of the buried oxide layer 8 is close to the lower side of the internal gate contact region 12, and the left upper side of the buried oxide layer 8 is in contact with the right sides of the internal gate oxide layer 10 and the internal gate contact region 12; the thickness was 2.0 μm and the length was 10.0. Mu.m.
The upper side of the substrate 9 is in contact with the lower side of the buried oxide layer 8, and the substrate is positioned at the bottom of the device; the thickness was 2.0 μm and the length was 10.0. Mu.m.
The lower edge of the internal gate oxide layer 10 is in contact with the upper edge of the internal gate contact region 12, the right side of the internal gate oxide layer is in contact with the buried oxide layer 8, and meanwhile, the upper edge of the internal gate oxide layer 10 is in contact with the lower edges of the source N + region 13 and the P-body 11; the thickness was 0.1 μm and the length was 2.0. Mu.m.
The left side of the P-body11 is contacted with the right sides of the source N + region 13 and the source P + region 2, and meanwhile, the upper side of the P-body is adjacent to the lower side of the field oxide layer 4, and the lower side of the P-body is contacted with the upper right side of the in-vivo gate oxide layer 10; it has a thickness of 1.0 μm and a length of 1.0 μm, and is doped with P-type impurities at a concentration of 1.0 × 10 17 cm -3 。
The body gate contact region 12 is positioned on the upper left side of the buried oxide layer 8 and below the source N + region 13, and the right side of the body gate contact region is also contacted with the buried oxide layer 8; polysilicon with thickness of 0.2 μm and length of 2.0 μm is doped with N-type impurity at concentration of 5.0 × 10 18 cm -3 。
The upper left side of the source N + region 13 is in contact with the lower side of the source contact region 1, the lower side of the source N + region 13 is in contact with the upper side of the body grid contact region 12, the shape of the body grid contact region is L-shaped, meanwhile, the rightmost side of the source N + region 13 is in contact with the left lower side of the P-body11, and the source N + region 13 is also adjacent to the lower side and the left side of the source P + region 2. Upper side of 0.5 μm, lower side of 1.0 μm, thickness of 1.0 μm, and N-type impurity doping concentration of 1.0 × 10 20 cm -3 。
Example 2:
the thin-layer SOI-LDMOS device with an in-vivo channel is characterized by mainly comprising a source contact region 1, a source P + region 2, an N-type drift region 3, a field oxide layer 4, a P-type covering layer 5, a drain contact region 6, a drain N + region 7, a buried oxide layer 8, a substrate 9, an in-vivo gate oxide layer 10, a P-body11, an in-vivo gate contact region 12 and a source N + region 13.
On the basis of the structure of embodiment 1, the lower side, the left side and the right side of the silicon dioxide dielectric region 5 which is replaced by the P-type covering layer 5,P type covering layer are all positioned in the N-type drift region 3 and are not adjacent to other parts, the distance from the left side of the N-type drift region to the left side is 1.0 μm, the distance from the right side of the N-type drift region to the right side is 1.0 μm, and the upper side of the silicon dioxide dielectric region is adjacent to the lower side of the field oxide layer 4; the P-type cladding layer 5 has a length of 5 μm and a thickness of 0.5 μm, and is doped withThe concentration of P-type impurity is 2.0 × 10 16 cm -3 。
Example 3:
the thin-layer SOI-LDMOS device with an in-vivo channel is characterized by mainly comprising a source contact region 1, a source P + region 2, an N-type drift region 3, a field oxide layer 4, a silicon dioxide dielectric region 5, a drain contact region 6, a drain N + region 7, a buried oxide layer 8, a substrate 9, an in-vivo gate oxide layer 10, a P-body11, an in-vivo gate contact region 12, a source N + region 13 and a P-type covering layer 14.
In addition to the structure of embodiment 1, the length of the silicon dioxide dielectric region 5 is shortened such that the lower side of the silicon dioxide dielectric region 5 contacts the upper side of the N-type drift region 3, the right side contacts the left side of the P-type cladding layer 14, the upper side contacts the lower side of the field oxide layer 4, the left side contacts the right side of the P-body11, the length of the silicon dioxide dielectric region 5 is 3.0 μm, and the thickness is 0.5 μm. The left side of the P-type covering layer 14 is contacted with the right side of the silicon dioxide dielectric region 5, the upper side is contacted with the lower side of the field oxide layer 4, the right side is contacted with the left side of the drain N + region 7, the lower side is contacted with the upper side of the N-type drift region 3, the length of the P-type covering layer 14 is 4.0 mu m, the thickness is 0.5 mu m, the concentration of doped P-type impurities is 2.0 multiplied by 10 16 cm -3 。
FIG. 4 is a graph of the voltage (V) at room temperature equal to 300k and the drain voltage d ) When the voltage is equal to 1V, the transfer characteristic curve and transconductance contrast graph of the SOI-LDMOS device with the new structure, the traditional SOI-LDMOS device and the traditional super junction SOI-LDMOS device under forward conduction is shown. The electrical characteristics of the above four devices are simulated by sentaturus simulation software, and the obtained simulation data is compared with a contrast chart drawn by an Origin tool, as shown in fig. 4. Transconductance maximum value (g) of SOI-LDMOS with novel structure mMAX ) 5.8mS/mm, and the maximum transconductance value (g) of the conventional SOI-LDMOS and the conventional super junction SOI-LDMOS mMAX ) 1.5mS/mm and 3.1mS/mm respectively, and the maximum transconductance value (g) of the new structure SOI-LDMOS, the traditional SOI-LDMOS and the traditional super-junction SOI-LDMOS mMAX ) Compared with the traditional SOI-LDMOS transconductance maximum value (g), the transconductance maximum value is increased by 4.6mS/mm and 3.0mS/mm respectively, and meanwhile, the transconductance maximum value is the traditional SOI-LDMOS transconductance maximum value mMAX ) 3.87 times of that of the traditional super junction SOI-LDMOS maximum transconductance value (g) mMAX ) 1.87 times of. In addition, the new knotThe transfer characteristic curves of the SOI-LDMOS of the structure 1 are higher than those of the traditional SOI-LDMOS and the traditional super-junction SOI-LDMOS. Therefore, the grid voltage-to-current control capability of the SOI-LDMOS with the new structure is greatly improved compared with that of the traditional SOI-LDMOS and the traditional super-junction SOI-LDMOS.
FIG. 5 shows the gate voltage V of the SOI-LDMOS device, the conventional SOI-LDMOS device and the conventional super-junction SOI-LDMOS device with the new structure g The output characteristic curve is 10V. According to the graph shown in FIG. 5, after the device is turned on, the drain saturation current of the newly-junction SOI-LDMOS is larger than that of the conventional SOI-LDMOS and that of the conventional super-junction SOI-LDMOS.
FIG. 6 shows the drain voltage V of the SOI-LDMOS device with the new structure (the structure is shown in FIG. 1), the conventional SOI-LDMOS device and the conventional super-junction SOI-LDMOS device d Graph comparing the turn-on voltage at 5V. As shown in FIG. 6, the gate oxide thickness and the drain current I are the same d Is 100A/cm 2 Meanwhile, the turn-on voltages of the traditional SOI-LDMOS device and the traditional super-junction SOI-LDMOS device are respectively 6.25V and 5.80V. However, the turn-on voltage of the SOI-LDMOS device with the new structure is 5.45V, and is respectively reduced by 12.8% and 6% compared with the traditional SOI-LDMOS device and the traditional super-junction SOI-LDMOS device; the SOI-LDMOS with the new structure has the silicon dioxide dielectric region in the drift region, the silicon dioxide dielectric region can improve the doping concentration of the drift region, the drain current of the SOI-LDMOS can be increased under the same bias voltage, and the surface grid electrode is transferred into the buried oxide layer, so that the injection capability of electrons can be enhanced. Therefore, the forward conduction performance of the SOI-LDMOS device with the new structure is superior to that of the traditional SOI-LDMOS device and the traditional super-junction SOI-LDMOS device.
The maximum transconductance values (g) of the three devices are respectively recorded in table 1 below mMAX ) Specific on-resistance R on,sp Baliga figure of merit FOM and breakdown voltage BV. The maximum transconductance value (g) of the SOI-LDMOS device with the new structure is shown in the following table mMAX ) Are both larger than the maximum transconductance value (g) of the traditional SOI-LDMOS device and the traditional super-junction SOI-LDMOS device mMAX ) The SOI-LDMOS device with the new structure is characterized in that a surface grid electrode is transferred to an inner grid of a buried oxide layer forming body on the basis of the traditional device, so that the grid electrode voltage of the device is increasedThe control capability of the current is enhanced. Specific on-resistance R of SOI-LDMOS device with novel structure on,sp Compared with the traditional SOI-LDMOS device and the traditional super junction SOI-LDMOS device, the silicon dioxide-based super junction SOI-LDMOS device is also minimum, because the silicon dioxide dielectric region exists in the N-type drift region of the device, and the silicon dioxide dielectric region can improve the doping concentration of the drift region of the device and then reduce the specific on-resistance of the device. The breakdown voltage of the SOI-LDMOS device with the new structure is slightly reduced compared with that of the traditional SOI-LDMOS device and the traditional super-junction SOI-LDMOS device. The Baliga optimal value FOM of the SOI-LDMOS device with the new structure is larger than the Baliga optimal value FOM of the traditional SOI-LDMOS device and the traditional super-junction SOI-LDMOS device.
TABLE 1 comparison of three device Properties
FIG. 7 shows the doping concentrations of the SOI-LDMOS devices with the new structure in the N-type drift region are 1.2 × 10 16 cm -3 、1.4×10 16 cm -3 、1.6×10 16 cm -3 、1.8×10 16 cm -3 、2.0×10 16 cm -3 And 2.2X 10 16 cm -3 Breakdown voltage BV and specific on-resistance R on,sp The change curve of (2). As shown in FIG. 7, the doping concentration in the N-type drift region is 1.8 × 10 16 cm -3 The breakdown voltage BV reaches a maximum value, the breakdown voltage BV is 110V, and the specific on-resistance R is at the moment on,sp Is 6.0 m.OMEGA.. Cm 2 . Specific on-resistance R on,sp The doping concentration of the N-type drift region is increased and is in a descending trend, the larger the doping concentration of the N-type drift region is, the higher the specific on-resistance R is on,sp The smaller; but when the doping concentration of the N-type drift region is more than 2.0 multiplied by 10 16 cm -3 The breakdown voltage BV is drastically reduced.
FIG. 8 shows the breakdown voltage BV and specific on-resistance R of the SOI-LDMOS device with the new structure when the thicknesses of the silicon dioxide dielectric regions are 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm and 0.8 μm respectively on,sp The change curve of (2). As can be seen from fig. 8, as the thickness of the silicon dioxide dielectric region increases, the breakdown voltage BV increases first and then decreases; in the presence of oxygenWhen the thickness of the silicon dielectric region is 0.7 μm, the breakdown voltage BV reaches a maximum value of 110V, and the specific on-resistance R is at this time on,sp Is 6.0 m.OMEGA.. Cm 2 . Specific on-resistance R on,sp The increase of the thickness of the silicon dioxide dielectric region is in an increasing trend, because the thickness of the N-type drift region is reduced due to the increase of the thickness of the silicon dioxide dielectric region, which leads to the reduction of the effective conductive area, thereby leading to the reduction of the specific on-resistance R on,sp And is increased.
FIG. 9 shows current line patterns of the SOI-LDMOS device with the new structure (the structure is shown in FIG. 1), the conventional SOI-LDMOS device and the conventional super-junction SOI-LDMOS device in a forward conduction state. As shown in FIG. 9, the conductive channel of the SOI-LDMOS device with the new structure is in the body, and current flows to the source through the channel in the body; and the conductive channel of the traditional SOI-LDMOS device and the traditional super junction SOI-LDMOS device is on the surface, and the current flows to the source electrode through the surface channel.
Fig. 10 is a comparison graph of Y =0.7 μm electric field in avalanche breakdown state for new structure SOI-LDMOS devices (the structure of which is shown in fig. 1), conventional SOI-LDMOS devices, and conventional superjunction SOI-LDMOS devices. As can be seen from fig. 10, the area enclosed by the electric field strength curve and the X axis of the conventional SOI-LDMOS device and the conventional super-junction SOI-LDMOS device is larger than that of the SOI-LDMOS device with the new structure because the doping concentration of the drift region of the conventional SOI-LDMOS device is relatively low, and the P-type pillar exists in the drift region of the conventional super-junction SOI-LDMOS device, which can assist the N-type drift region to be depleted, and therefore, the electric field strength distribution of the conventional SOI-LDMOS device and the conventional super-junction SOI-LDMOS device is uniform.
FIG. 11 is equipotential line pair distribution diagram of the new structure SOI-LDMOS device (the structure of which is shown in FIG. 1), the traditional SOI-LDMOS device and the traditional super junction SOI-LDMOS device under the avalanche breakdown state. As can be seen from FIG. 11, equipotential lines of the SOI-LDMOS device with the new structure, the conventional SOI-LDMOS device and the conventional super-junction SOI-LDMOS device are distributed very uniformly, and the equipotential lines at the middle part of the drift region of the SOI-LDMOS device with the new structure are only distributed a little sparsely.
The thin-layer SOI-LDMOS device with an in-body channel according to the present invention is illustrated in fig. 1, and the main process flow thereof is shown in fig. 12. The specific implementation method comprises the following steps: first, select SOI substrate, for SAnd etching and filling the OI substrate to form a body inner grid. And secondly, carrying out vapor phase epitaxy to grow an N-type drift region, and then carrying out ion implantation and diffusion processes to respectively form a source N + region, a P-body, a source P + region and a source N + region. Then, carrying out ion etching on the N-type drift region to form a groove, depositing silicon dioxide on the groove formed by etching by utilizing a chemical deposition method to form a silicon dioxide medium region, and depositing a layer of SiO on the upper part of the silicon dioxide medium region and the upper part of the P-body 2 The protective layer forms a field oxide layer. Finally, metal is deposited on the source electrode and the drain electrode to form good ohmic contact.
In the implementation process, according to the design requirements of specific devices, the thin-layer SOI-LDMOS device with the in-body channel provided by the invention has the advantages that when the thin-layer SOI-LDMOS device is specifically manufactured, the substrate material can be a silicon carbide SiC material, and can also be a semiconductor material such as silicon, gallium arsenide, indium phosphide or germanium silicon and the like instead of bulk silicon carbide.
Finally, the above embodiments are only intended to illustrate the technical solutions of the present invention and not to limit the present invention, and although the present invention has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that modifications or equivalent substitutions may be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions, and all of them should be covered by the claims of the present invention.
Claims (4)
1. A thin-layer SOI-LDMOS device having a conductive channel in the body, characterized in that: the field oxide layer is arranged on the silicon dioxide dielectric region (5), and comprises a source electrode contact region (1), a source electrode P + region (2), an N-type drift region (3), a field oxide layer (4), a silicon dioxide dielectric region (5), a drain electrode contact region (6), a drain electrode N + region (7), an oxygen buried layer (8), a substrate (9), an in-body gate oxide layer (10), a P-body (11), an in-body gate contact region (12) and a source electrode N + region (13); the source electrode contact region (1) is positioned above the source electrode N + region (13) and the source electrode P + region (2), and the right side of the source electrode contact region (1) is closely adjacent to the left side of the field oxide layer (4); the upper side of the source P + region (2) is bordered by the lower side of the source contact region (1), the lower side and the left side of the source P + region (2) are contacted with the source N + region (13), and meanwhile, the right side of the source P + region (2) is contacted with a part of the left side of the P-body (11); the upper side of the N-type drift region (3) is adjacent to the lower side of the silicon dioxide dielectric region (5), the left side of the N-type drift region is in contact with the right lower side of the P-body (11), the right side of the N-type drift region is adjacent to the left lower side of the drain electrode N + region (7), and the lower side of the N-type drift region is in contact with the upper side of the buried oxide layer (8); the field oxide layer (4) is positioned on the upper sides of the P-body (11) and the silicon dioxide medium region (5), the right side of the field oxide layer is close to the left side of the drain contact region (6), and the left side of the field oxide layer is in contact with the right side of the source contact region (1); the lower side of the silicon dioxide dielectric region (5) is in contact with the upper side of the N-type drift region (3), the left side of the silicon dioxide dielectric region is adjacent to the upper right side of the P-body (11), the right side of the silicon dioxide dielectric region is adjacent to the upper left side of the drain electrode N + region (7), and meanwhile, the upper side of the silicon dioxide dielectric region is in contact with the lower side of the field oxide layer (4); the drain contact region (6) is positioned right above the drain N + region (7), and the left side of the drain contact region (6) is adjacent to the right side of the field oxide layer (4); the drain electrode N + region (7) is positioned right below the drain electrode contact region (6), meanwhile, the left side of the drain electrode N + region is contacted with the silicon dioxide dielectric region (5) and the right side of the N-type drift region (3), and the lower side of the drain electrode N + region (7) is adjacent to the upper right side of the buried oxide layer (8); the lower side of the buried oxide layer (8) is close to the upper side of the substrate (9), the upper side of the buried oxide layer (8) is adjacent to the drain electrode N + region (7) and the lower side of the N-type drift region (3), meanwhile, the upper left side of the buried oxide layer (8) is close to the lower side of the in-body gate contact region (12), and the upper left side of the buried oxide layer (8) is in contact with the right sides of the in-body gate oxide layer (10) and the in-body gate contact region (12); the upper side of the substrate (9) is in contact with the lower side of the buried oxide layer (8), and the substrate is positioned at the bottom of the device; the lower edge of the internal gate oxide layer (10) is in contact with the upper edge of the internal gate contact region (12), the right side of the internal gate oxide layer is also in contact with the buried oxide layer (8), and meanwhile, the upper edge of the internal gate oxide layer (10) is in contact with the lower edges of the source N + region (13) and the P-body (11); the left side of the P-body (11) is contacted with the right sides of the source N + region (13) and the source P + region (2), meanwhile, the upper side of the P-body is adjacent to the lower left side of the field oxide layer (4), and the lower side of the P-body is contacted with the upper right side of the in-vivo gate oxide layer (10); the in-vivo gate contact region (12) is positioned on the upper left side of the buried oxide layer (8) and the lower side of the in-vivo gate oxide layer (10), and the right side of the in-vivo gate contact region is contacted with the buried oxide layer (8); the upper left side of the source electrode N + region (13) is in contact with the lower side of the source electrode contact region (1), the lower side of the source electrode N + region (13) is in contact with the upper side of the in-vivo gate oxide layer (10), the source electrode N + region is L-shaped, meanwhile, the rightmost side of the source electrode N + region (13) is in contact with the left lower side of the P-body (11), and the source electrode N + region (13) is also in contact with the lower side and the left side of the source electrode P + region (2).
2. The thin-layer SOI-LDMOS device as claimed in claim 1, wherein: the thickness of the silicon dioxide medium area (5) is in the range of 0.2-0.8 μm.
3. The thin-layer SOI-LDMOS device as claimed in claim 1, wherein: the in-body gate contact region (12) is doped polysilicon.
4. The thin-layer SOI-LDMOS device as claimed in claim 1, wherein: the N-type drift region (3) is doped with N-type impurities with a doping concentration range of 5 × 10 15 ～5×10 16 cm -3 。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011407861.3A CN112466955B (en) | 2020-12-04 | 2020-12-04 | Thin-layer SOI-LDMOS device with in-vivo conductive channel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011407861.3A CN112466955B (en) | 2020-12-04 | 2020-12-04 | Thin-layer SOI-LDMOS device with in-vivo conductive channel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112466955A CN112466955A (en) | 2021-03-09 |
| CN112466955B true CN112466955B (en) | 2022-10-11 |
Family
ID=74805490
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011407861.3A Active CN112466955B (en) | 2020-12-04 | 2020-12-04 | Thin-layer SOI-LDMOS device with in-vivo conductive channel |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112466955B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113097310B (en) * | 2021-04-02 | 2023-03-24 | 重庆邮电大学 | Fin-type EAFin-LDMOS device with electron accumulation effect |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109166915A (en) * | 2018-08-28 | 2019-01-08 | 电子科技大学 | A kind of medium superjunction MOS type power semiconductor and preparation method thereof |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB0107408D0 (en) * | 2001-03-23 | 2001-05-16 | Koninkl Philips Electronics Nv | Field effect transistor structure and method of manufacture |
| US8097880B2 (en) * | 2009-04-09 | 2012-01-17 | Infineon Technologies Austria Ag | Semiconductor component including a lateral transistor component |
| US8217452B2 (en) * | 2010-08-05 | 2012-07-10 | Atmel Rousset S.A.S. | Enhanced HVPMOS |
| CN102386211B (en) * | 2010-08-31 | 2014-01-08 | 无锡华润上华半导体有限公司 | LDMOS device and fabrication method thereof |
| CN102779836B (en) * | 2012-07-13 | 2015-02-11 | 电子科技大学 | Longitudinal power device with low specific on-resistance using high dielectric constant groove structure |
| EP2757580A1 (en) * | 2013-01-22 | 2014-07-23 | Nxp B.V. | Bipolar cmos dmos (bcd) processes |
| CN103325835B (en) * | 2013-05-28 | 2015-10-21 | 电子科技大学 | A kind of SOI power LDMOS device with junction type field plate |
| US9419130B2 (en) * | 2013-11-27 | 2016-08-16 | Infineon Technologies Austria Ag | Semiconductor device and integrated circuit |
| US9312348B2 (en) * | 2014-02-14 | 2016-04-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Ultra high voltage semiconductor device with electrostatic discharge capabilities |
| KR102248307B1 (en) * | 2014-09-01 | 2021-05-04 | 에스케이하이닉스 시스템아이씨 주식회사 | Power integrated device, and electronic device and electronic system having the power integrated device |
| CN105097936A (en) * | 2015-07-06 | 2015-11-25 | 深港产学研基地 | Silicon-on-insulator lateral double-diffused metal-oxide-semiconductor (LDMOS) power device |
| CN105789314A (en) * | 2016-03-18 | 2016-07-20 | 电子科技大学 | Transverse SOI power LDMOS |
| CN108063158A (en) * | 2017-12-06 | 2018-05-22 | 重庆邮电大学 | A kind of LDMOS device with groove profile oxide layer and horizontal superjunction |
| CN111755523A (en) * | 2020-07-09 | 2020-10-09 | 重庆邮电大学 | Super-junction SOI-LDMOS device with low-resistance N-type electronic channel |
-
2020
- 2020-12-04 CN CN202011407861.3A patent/CN112466955B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109166915A (en) * | 2018-08-28 | 2019-01-08 | 电子科技大学 | A kind of medium superjunction MOS type power semiconductor and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112466955A (en) | 2021-03-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10727334B2 (en) | Lateral DMOS device with dummy gate | |
| KR100869324B1 (en) | Power semiconductor devices having laterally extending base shielding regions that inhibit base reach through and methods of forming same | |
| WO2010036942A2 (en) | Power mosfet having a strained channel in a semiconductor heterostructure on metal substrate | |
| US20130214352A1 (en) | Dual Gate Lateral MOSFET | |
| CN109920839B (en) | P + shielding layer potential-adjustable silicon carbide MOSFET device and preparation method thereof | |
| CN111668312A (en) | Groove silicon carbide power device with low on-resistance and manufacturing process thereof | |
| CN107123684A (en) | One kind has wide bandgap material and silicon materials complex vertical double-diffusion metal-oxide-semiconductor field effect transistor | |
| CN114050187A (en) | Integrated trench gate power semiconductor transistor with low characteristic on-resistance | |
| CN112420846B (en) | Transverse super-junction thin-layer SOI-LDMOS device with surface and body double channels | |
| CN108538909A (en) | Hetero-junctions vertical double-diffusion metal-oxide-semiconductor field effect transistor and preparation method thereof with charge compensation block | |
| CN112768530B (en) | high-K gate-surrounding field medium longitudinal double-diffusion power device | |
| CN112466955B (en) | Thin-layer SOI-LDMOS device with in-vivo conductive channel | |
| CN105304693B (en) | A kind of manufacturing method of LDMOS device | |
| CN108565286B (en) | high-K dielectric groove transverse double-diffusion metal oxide semiconductor field effect transistor and manufacturing method thereof | |
| CN103311272A (en) | Lateral mosfet with dielectric isolation trench | |
| CN112993021B (en) | Lateral double-diffusion metal oxide semiconductor field effect transistor | |
| CN111477681A (en) | Double-channel uniform electric field modulation transverse double-diffusion metal oxide semiconductor field effect transistor and manufacturing method thereof | |
| CN116598361A (en) | LDMOS device with super-junction split gate | |
| CN115274859B (en) | LDMOS transistor and manufacturing method thereof | |
| CN113488525B (en) | Super-junction EA-SJ-FINFET device with charge accumulation effect | |
| CN113921611A (en) | LDMOS device with double-side super-junction trench gate | |
| CN114664934A (en) | DMOS transistor with field plate and manufacturing method thereof | |
| CN111477680A (en) | Double-channel uniform electric field modulation transverse double-diffusion metal oxide wide-band-gap semiconductor field effect transistor and manufacturing method thereof | |
| CN112164718A (en) | Split gate device with control gate protection layer and method of manufacturing the same | |
| CN111293163A (en) | Lateral diffusion metal oxide semiconductor field effect transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |