CN112466955B - Thin-layer SOI-LDMOS device with in-vivo conductive channel - Google Patents

Abstract

The invention relates to a thin-layer SOI-LDMOS device with an internal conductive channel, belonging to the technical field of semiconductor power devices. Based on the traditional thin-layer SOI-LDMOS device, the device transfers the surface gate to the buried oxide layer to form the internal gate, and forms the internal conductive channel on the lower surface of the P-body. At the same time, silicon dioxide is etched and filled in the drift region of the device. The device has the following advantages: in the forward conduction, the gate voltage in the body can greatly improve the current control ability, and the transconductance _gmMAX of the device is compared with The traditional devices and traditional superjunction devices are increased by 298.7% and 87.1% respectively. Further etching and filling silicon dioxide in the drift region can increase the doping concentration of the drift region and reduce the specific on-resistance of the device, and finally improve the Baliga of the device. Figure of merit FOM.

Description

A thin-layer SOI-LDMOS device with internal conductive channel

technical field

The invention belongs to the technical field of semiconductor power devices, and relates to a thin-layer SOI-LDMOS device with an internal conductive channel.

Background technique

SOI technology can achieve dielectric isolation of power integrated circuits by introducing a dielectric layer into the device. Compared with bulk silicon technology, SOI technology has higher integration, extremely smaller parasitic capacitance and better isolation performance. SOI technology can greatly improve the reliability of integrated circuits, and will become a key technology in the process of manufacturing high-integration, high-reliability, high-speed and low-power chips in the future, especially for power integrated circuits. LDMOS devices based on silicon-on-insulator technology (SOI-LDMOS: Si-On-Insulator Lateral Double-Diffused Metal-Oxide-Semiconductor) have better CMOS process compatibility than most other new active devices such as HEMT, HBT, etc. And the characteristics of convenient integration, and it has high power, high gain, high linearity, high switching characteristics, as well as good isolation performance, superior radiation resistance and reliability, so it has been widely concerned by industry workers, so The research on SOI-LDMOS has a very special significance. It is mainly used in: smart power integrated circuit (SmartPowerIntegratedCircuit, SPIC), radio frequency integrated circuit (RadioFrequencyIntegratedCircuit, RFIC), high voltage integrated circuit (HighVoltageIntegratedCircuit,HVIC).

The withstand voltage capability of SOI lateral power devices is determined by the smaller of the lateral breakdown voltage and the longitudinal breakdown voltage. Generally, increasing the lateral length of the device and reducing the doping concentration of the drift region can improve the lateral withstand voltage capability of the device, but at the same time increase the on-resistance of the device, thereby reducing the forward conduction performance of the device. However, since the buried oxide layer and the top silicon of the SOI device cannot be too thick, if the thickness of the buried oxide layer and the top silicon is too thick, the manufacturing process of the device will be more difficult, the self-heating phenomenon of the device will be aggravated, and heat dissipation and other problems will be caused. Therefore, The buried oxide and top silicon layers of SOI devices should not be too thick. When the buried oxide layer and the top silicon of the SOI device are too thin, the vertical withstand voltage capability of the device will be reduced, because the buried oxide layer will prevent the depletion region of the device from extending to the substrate, so that the substrate will not withstand voltage. . The main contradiction of this device is the specific on-resistance Ron,sp and the breakdown voltage BV: Ron,sp∝BV ^2.5 . By increasing the doping concentration of the N-type layer in the drift region, the specific on-resistance of the device is reduced, but at the same time, the breakdown voltage of the device will drop sharply; increasing the breakdown voltage of the device will increase the specific on-resistance of the device at the same time. big. In order to better measure the comprehensive performance indicators of the device, the use of Baliga figure of merit to evaluate the figure of merit FOM (figure of merit) of the device has become a very important performance indicator, that is, FOM=BV ² /Ron,sp, the larger the Baliga figure of merit FOM It means that the overall performance of the device is better.

In order to solve the above contradiction, the present invention proposes a thin-layer SOI-LDMOS device with an internal conductive channel, which can increase the doping concentration of the N-type layer in the drift region by introducing a silicon dioxide dielectric region into the drift region, thereby Reduce the specific on-resistance of the device. At the same time, the surface gate of the device is transferred to the buried oxide layer to form the internal gate, which greatly improves the injection ability of electrons, thereby enhancing the control ability of the gate voltage of the device on the current.

SUMMARY OF THE INVENTION

In view of this, the purpose of the present invention is to provide a thin-layer SOI-LDMOS device with a conductive channel in the body, which can optimize the electric field distribution in the drift region, increase the doping concentration of the N-type layer in the drift region, and reduce the specific on-resistance of the device. At the same time, the opening of the channel is controlled by the gate voltage in the body, so that the injection ability of electrons is enhanced, thereby improving the control ability of the gate voltage on the current.

To achieve the above object, the present invention provides the following technical solutions:

A thin-layer SOI-LDMOS device with an internal conductive channel, comprising a source contact region (1), a source P+ region (2), an N-type drift region (3), a field oxide layer (4), silicon dioxide Dielectric region (5), drain contact region (6), drain N+ region (7), buried oxide layer (8), substrate (9), internal gate oxide layer (10), P-body (11), Body gate contact region (12) and source N+ region (13). The source contact region (1) is located above the source N+ region (13) and the source P+ region (2), and the right side of the source contact region (1) is immediately adjacent to the left side of the field oxide layer (4); The upper side of the source P+ region (2) borders the lower side of the source contact region (1), and the lower and left sides of the source P+ region (2) are in contact with the source N+ region (13). The right side of the polar P+ region (2) is in contact with a part of the left side of the P-body (11); the upper side of the N-type drift region (3) is immediately adjacent to the lower side of the silicon dioxide dielectric region (5), and the left side of the N-type drift region (3) is adjacent to the lower side of the silicon dioxide dielectric region (5). The lower right side of the P-body (11) is in contact, the right side is adjacent to the lower left side of the drain N+ region (7), and the lower side is in contact with the upper side of the buried oxide layer (8); the field oxide layer (4) is located in The upper side of the P-body (11) and the silicon dioxide dielectric region (5), the right side is immediately adjacent to the left side of the drain contact region (6), and the left side is in contact with the right side of the source contact region (1); the The lower side of the silicon dioxide dielectric region (5) is in contact with the upper side of the N-type drift region (3), the left side is adjacent to the upper right side of the P-body (11), and the right side is adjacent to the upper left side of the drain N+ region (7). , at the same time, the upper side is in contact with the lower side of the field oxide layer (4); the drain contact region (6) is located directly above the drain N+ region (7), and the left side of the drain contact region (6) is adjacent to the field oxide layer The right side of layer (4); the drain N+ region (7) is located directly below the drain contact region (6), while the left side is connected to the silicon dioxide dielectric region (5) and the N-type drift region (3) The right side of the drain N+ region (7) is in contact with the upper right side of the buried oxide layer (8); the lower side of the buried oxide layer (8) is close to the upper side of the substrate (9), and the buried oxide layer (8) The upper side of the drain electrode is adjacent to the drain N+ region (7) and the lower side of the N-type drift region (3). At the same time, the upper left side of the buried oxide layer (8) is adjacent to the lower side of the body gate contact region (12), and the upper left side is adjacent to the body gate oxide layer. The layer (10) is in contact with the right side of the in-body gate contact region (12); the upper side of the substrate (9) is in contact with the lower side of the buried oxide layer (8), which is located at the bottom of the device; the in-body gate oxide layer (10) The lower side of the gate oxide layer (10) is in contact with the upper side of the in-body gate contact region (12), and the right side is in contact with the buried oxide layer (8). 11) bottom contact; the left side of the P-body (11) is in contact with the source N+ region (13) and the right side of the source P+ region (2), and at the same time, its upper side is adjacent to the field oxide layer (4) The lower left side is in contact with the upper right side of the internal gate oxide layer (10); the internal gate contact region (12) is located on the upper left side of the buried oxide layer (8) and the lower side of the internal gate oxide layer (10), which The right side is in contact with the buried oxide layer (8). The upper left side of the source N+ region (13) is in contact with the lower side of the source contact region (1), and the lower side of the source N+ region (13) is in contact with the upper side of the internal gate oxide layer (10), and its shape is L-shaped At the same time, the rightmost side of the source N+ region (13) is in contact with the lower left side of the P-body (11), and the source N+ region (13) is also in contact with the lower and left sides of the source P+ region (2).

Optionally, the thickness of the silicon dioxide dielectric region (5) is 0.2-0.8 μm, which can be adjusted.

Optionally, the in-body gate contact region (12) is doped polysilicon and metal.

Optionally, the N-type drift region (3) is doped with N-type impurities, and the doping concentration thereof ranges from 5×10 ¹⁵ to 5×10 ¹⁶ cm ⁻³ .

The beneficial effect of the present invention is that: for a thin-layer SOI-LDMOS device with an internal channel proposed by the present invention, the surface gate of the device is transferred to the buried oxide layer to form the internal gate, and at the same time, in the N-type drift region Silicon dioxide dielectric regions are formed by ion etching and dielectric filling. First of all, in the forward conduction, the ability of the internal gate to inject electrons into the N-type drift region is greatly improved, thereby improving the control ability of the gate voltage on the current (the transconductance _gm increases); the silicon dioxide dielectric region can The doping concentration of the N-type drift region is effectively increased, so that the on-resistance of the N-type drift region is reduced, thereby optimizing the forward conduction performance of the device. Second, during breakdown, the silicon dioxide dielectric region can optimize the electric field distribution of the N-type drift region, so that the N-type drift region can be completely depleted. To sum up, transferring the surface gate to the buried oxide layer to form the bulk gate and etching and filling silicon dioxide in the drift region improves the Baliga figure of merit FOM of the device.

Other advantages, objects, and features of the present invention will be set forth in the description that follows, and will be apparent to those skilled in the art based on a study of the following, to the extent that is taught in the practice of the present invention. The objectives and other advantages of the present invention may be realized and attained by the following description.

Description of drawings

In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be preferably described in detail below with reference to the accompanying drawings, wherein:

1 is a schematic structural diagram of a thin-layer SOI-LDMOS device according to Embodiment 1 of the present invention;

2 is a schematic structural diagram of a thin-layer SOI-LDMOS device according to Embodiment 2 of the present invention;

3 is a schematic structural diagram of a thin-layer SOI-LDMOS device according to Embodiment 3 of the present invention;

4 is a comparison diagram of transfer characteristic curve and transconductance under forward conduction of a new structure SOI-LDMOS device, a traditional SOI-LDMOS device and a traditional superjunction SOI-LDMOS device provided by the present invention;

5 is a comparison diagram of output characteristic curves of a new structure SOI-LDMOS device, a traditional SOI-LDMOS device and a traditional superjunction SOI-LDMOS device provided by the present invention under forward conduction;

FIG. 6 is a comparison diagram of the turn-on voltage of a new structure SOI-LDMOS device, a traditional SOI-LDMOS device and a traditional super-junction SOI-LDMOS device provided by the present invention;

7 shows the SOI-LDMOS device with the new structure provided by the present invention in the N-type drift region with the doping concentrations of 1.2×10 ¹⁶ cm ^-3 , 1.4×10 ¹⁶ cm ^-3 , 1.6×10 ¹⁶ cm ^-3 , 1.8×10 ¹⁶ Variation curves of breakdown voltage BV and specific on-resistance Ron,sp at cm ^-3 , 2.0×10 ¹⁶ cm ^-3 and 2.2×10 ¹⁶ cm ^-3 ;

Figure 8 shows the breakdown voltage BV and the specific on-resistance Ron,sp of the SOI-LDMOS device with the new structure provided by the present invention when the thickness of the silicon dioxide interposer is 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm and 0.8 μm the change curve;

9 is the current line pattern of the new structure SOI-LDMOS device provided by the present invention, the traditional SOI-LDMOS device, and the traditional superjunction SOI-LDMOS device in the forward conduction state; (a) is the new structure SOI-LDMOS; ( b) is a traditional SOI-LDMOS; (c) is a traditional super-junction SOI-LDMOS;

10 is a comparison diagram of the two-dimensional electric field intensity at Y=0.7 μm in the breakdown state of the new structure SOI-LDMOS device, the traditional SOI-LDMOS device and the traditional superjunction SOI-LDMOS device provided by the present invention;

FIG. 11 is a distribution diagram of equipotential lines in a breakdown state of a new structure SOI-LDMOS device, a traditional SOI-LDMOS device and a traditional superjunction SOI-LDMOS device provided by the present invention; (a) is a new structure SOI-LDMOS; (b) ) is a traditional SOI-LDMOS; (c) is a traditional super-junction SOI-LDMOS;

12 is a process flow diagram of the present invention; (a) is etching, dry oxygen oxidation, filling to form trench gates; (b) is vapor phase epitaxy, ion implantation; (c) is deposition of SiO ₂ protective layer; (d) ) is the deposited metal contact.

Reference numerals: source contact region 1, source P+ region 2, N-type drift region 3, field oxide layer 4, silicon dioxide dielectric region 5, drain contact region 6, drain N+ region 7, buried oxide layer 8 , substrate 9 , internal gate oxide layer 10 , P-body 11 , internal gate contact region 12 and source N+ region 13 .

Detailed ways

The embodiments of the present invention are described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the drawings provided in the following embodiments are only used to illustrate the basic idea of the present invention in a schematic manner, and the following embodiments and features in the embodiments can be combined with each other without conflict.

Among them, the accompanying drawings are only used for exemplary description, and represent only schematic diagrams, not physical drawings, and should not be construed as limitations of the present invention; in order to better illustrate the embodiments of the present invention, some parts of the accompanying drawings will be omitted, The enlargement or reduction does not represent the size of the actual product; it is understandable to those skilled in the art that some well-known structures and their descriptions in the accompanying drawings may be omitted.

The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar components; in the description of the present invention, it should be understood that if there are terms “upper”, “lower”, “left” and “right” , "front", "rear" and other indicated orientations or positional relationships are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the indicated device or element must be It has a specific orientation, is constructed and operated in a specific orientation, so the terms describing the positional relationship in the accompanying drawings are only used for exemplary illustration, and should not be construed as a limitation of the present invention. situation to understand the specific meaning of the above terms.

Example 1:

As shown in FIG. 1, a thin-layer SOI-LDMOS device with an internal channel is characterized in that the device structure mainly includes a source contact region 1, a source P+ region 2, an N-type drift region 3, and a field oxide layer. 4. Silicon dioxide dielectric region 5, drain contact region 6, drain N+ region 7, buried oxide layer 8, substrate 9, body gate oxide layer 10, P-body 11, body gate contact region 12 and source N+ region 13.

The source contact region 1 is located above the source N+ region 13 and the source P+ region 2, and the right side of the source contact region 1 is adjacent to the left side of the field oxide layer 4; its thickness is 0.4 μm and the length is 0.5 μm.

The upper side of the source P+ region 2 is in contact with the lower side of the source contact region 1 , the lower side and the left side of the source P+ region 2 are in contact with the source N+ region 13 , and the right side of the source P+ region 2 is in contact with the P-body 11 The upper left contact; its thickness is 0.2 μm, its length is 0.5 μm, and the doped P-type impurity concentration is 1.0×10 ²⁰ cm ⁻³ .

The upper side of the N-type drift region 3 is adjacent to the lower side of the silicon dioxide dielectric region 5, the left side thereof is in contact with the lower right side of the P-body 11, and the right side is adjacent to the lower left side of the drain N+ region 7; its thickness is 0.6 μm, the length is 7.0 μm, and the doped N-type impurity concentration is 1.7×10 ¹⁶ cm ⁻³ .

The field oxide layer 4 is located on the upper side of the P-body 11 and the silicon dioxide dielectric region 5, the right side is adjacent to the left side of the drain contact region 6, and the left side is in contact with the right side of the source contact region 1; its thickness is 0.2 μm, the length is 8.0 μm.

The lower side of the silicon dioxide dielectric region 5 is in contact with the upper side of the N-type drift region 3, the left side is adjacent to the upper right side of the P-body 11, the right side is adjacent to the upper left side of the drain N+ region 7, and the upper side is adjacent to the field The underside of the oxide layer 4 is in contact; its thickness is 0.7 μm and its length is 7.0 μm.

The drain contact region 6 is located just above the drain N+ region 7 , and the left side of the drain contact region 6 is immediately adjacent to the right side of the field oxide layer 4 ; its thickness is 0.2 μm and the length is 1.0 μm.

The drain N+ region 7 is located directly under the drain contact region 6 , and at the same time, its left side is in contact with the silicon dioxide dielectric region 5 and the right side of the N-type drift region 3 , and the lower side of the drain N+ region 7 is in contact with the buried oxide layer 8 It is adjacent to the upper right side; its thickness is 1.0 μm, its length is 1.0 μm, and the doped N-type impurity concentration is 1.0×10 ²⁰ cm ^-3 .

The lower side of the buried oxide layer 8 is adjacent to the upper side of the substrate 9, and the upper side of the buried oxide layer 8 is adjacent to the lower side of the drain N+ region 7 and the lower side of the N-type drift region 3. At the same time, the upper left side of the buried oxide layer 8 is adjacent to the internal gate contact. The lower and upper left sides of the region 12 are in contact with the in-body gate oxide layer 10 and the right side of the in-body gate contact region 12 ; the thickness is 2.0 μm and the length is 10.0 μm.

The upper side of the substrate 9 is in contact with the lower side of the buried oxide layer 8, which is located at the bottom of the device; its thickness is 2.0 μm and the length is 10.0 μm.

The lower side of the in-body gate oxide layer 10 is in contact with the upper side of the in-body gate contact region 12, and the right side thereof is in contact with the buried oxide layer 8. At the same time, the upper side of the in-body gate oxide layer 10 is in contact with the source N+ region 13 and the lower side of the P-body 11. Contact; its thickness is 0.1 μm and its length is 2.0 μm.

The left side of the P-body 11 is in contact with the source N+ region 13 and the right side of the source P+ region 2, and at the same time, its upper side is in close contact with the lower side of the field oxide layer 4, and the lower side is in contact with the upper right side of the internal gate oxide layer 10; It has a thickness of 1.0 μm, a length of 1.0 μm, and a concentration of doped P-type impurities of 1.0×10 ¹⁷ cm ⁻³ .

The body gate contact region 12 is located on the upper left side of the buried oxide layer 8 and the lower side of the source N+ region 13, and its right side is also in contact with the buried oxide layer 8; The N-type impurity concentration was 5.0×10 ¹⁸ cm ⁻³ .

The upper left side of the source N+ region 13 is in contact with the lower side of the source contact region 1, the lower side of the source N+ region 13 is in contact with the upper side of the gate contact region 12 in the body, and its shape is L-shaped. At the same time, the source N+ region 13 The far right is in contact with the lower left side of the P-body 11 , and the source N+ region 13 is also adjacent to the lower and left sides of the source P+ region 2 . The length of the upper side is 0.5 μm, the length of the lower side is 1.0 μm, the thickness is 1.0 μm, and the doped N-type impurity concentration is 1.0×10 ²⁰ cm ⁻³ .

Example 2:

A thin-layer SOI-LDMOS device with an internal channel, characterized in that the device structure mainly includes a source contact region 1, a source P+ region 2, an N-type drift region 3, a field oxide layer 4, and a P-type cladding layer. 5. Drain contact region 6 , drain N+ region 7 , buried oxide layer 8 , substrate 9 , body gate oxide layer 10 , P-body 11 , body gate contact region 12 and source N+ region 13 .

On the basis of the structure of Example 1, the silicon dioxide dielectric region 5 is replaced with a P-type cladding layer 5, and the lower, left and right sides of the P-type cladding layer are all located in the N-type drift region 3, which is different from other Partly adjacent, the left side is 1.0μm from the left side of the N-type drift region, the right side is 1.0μm from the right side of the N-type drift region, and the upper side is adjacent to the lower side of the field oxide layer 4; the length of the P-type cladding layer 5 is 5 μm, the thickness is 0.5 μm, and the doped P-type impurity concentration is 2.0×10 ¹⁶ cm ⁻³ .

Example 3:

A thin-layer SOI-LDMOS device with an internal channel is characterized in that the device structure mainly includes a source contact region 1, a source P+ region 2, an N-type drift region 3, a field oxide layer 4, and a silicon dioxide dielectric. region 5, drain contact region 6, drain N+ region 7, buried oxide layer 8, substrate 9, body gate oxide layer 10, P-body 11, body gate contact region 12, source N+ region 13 and P-type capping layer 14.

On the basis of the structure of Example 1, the length of the silicon dioxide dielectric region 5 is shortened, so that the lower side of the silicon dioxide dielectric region 5 is in contact with the upper side of the N-type drift region 3, and the right side is in contact with the left side of the P-type cladding layer 14. The upper side is in contact with the lower side of the field oxide layer 4, the left side is in contact with the right side of the P-body 11, and the silicon dioxide dielectric region 5 has a length of 3.0 μm and a thickness of 0.5 μm. The left side of the P-type capping layer 14 is in contact with the right side of the silicon dioxide dielectric region 5, the upper side is in contact with the lower side of the field oxide layer 4, the right side is in contact with the left side of the drain N+ region 7, and the lower side is in contact with the N-type The upper side of the drift region 3 is in contact, and the P-type cladding layer 14 has a length of 4.0 μm, a thickness of 0.5 μm, and a doped P-type impurity concentration of 2.0×10 ¹⁶ cm ⁻³ .

Figure 4 shows the new structure SOI-LDMOS (the structure of which is shown in Figure 1), the traditional SOI-LDMOS device and the traditional _{superjunction} SOI-LDMOS device in the positive Contrast graph of transfer characteristic curve and transconductance under conduction. The electrical characteristics of the above four devices are simulated by the sentaurus simulation software, and the obtained simulation data are drawn by the Origin tool for a comparison chart, as shown in Figure 4. The maximum transconductance (g _mMAX ) of the new SOI-LDMOS is 5.8mS/mm, while the maximum transconductance (g _mMAX ) of the conventional SOI-LDMOS and the conventional superjunction SOI-LDMOS are 1.5mS/mm and 3.1mS, respectively /mm, the transconductance maximum (g _mMAX ) of the new structure SOI-LDMOS is increased by 4.6mS/mm and 3.0mS/mm compared with the traditional SOI-LDMOS and the traditional superjunction SOI-LDMOS, respectively. The LDMOS transconductance maximum value (g _mMAX ) is 3.87 times and the conventional superjunction SOI-LDMOS transconductance maximum value (g _mMAX ) is 1.87 times. In addition, the transfer characteristic curves of the new structure 1SOI-LDMOS are higher than those of traditional SOI-LDMOS and traditional superjunction SOI-LDMOS. Therefore, compared with the conventional SOI-LDMOS and the conventional superjunction SOI-LDMOS, the gate voltage-to-current control capability of the new structure SOI-LDMOS is greatly improved.

FIG. 5 is a graph showing the output characteristics of the new structure SOI-LDMOS device (its structure is shown in FIG. 1 ), the conventional SOI-LDMOS device and the conventional superjunction SOI-LDMOS device when the gate voltage V _g is 10V. As shown in FIG. 5 , when the device is turned on, the drain saturation current of the new junction SOI-LDMOS is larger than that of the conventional conventional SOI-LDMOS and the conventional super-junction SOI-LDMOS.

6 is a comparison diagram of turn-on voltages of a new structure SOI-LDMOS (the structure of which is shown in FIG. 1 ), a conventional SOI-LDMOS device and a conventional superjunction SOI-LDMOS device when the drain voltage _Vd is 5V. As shown in FIG. 6 , when the gate oxide thickness and drain current I _d are 100A/cm ² , the turn-on voltages of the conventional SOI-LDMOS device and the conventional superjunction SOI-LDMOS device are 6.25V and 5.80V, respectively. However, the turn-on voltage of the new structure SOI-LDMOS device is 5.45V, which is 12.8% and 6% lower than that of the traditional SOI-LDMOS device and the traditional superjunction SOI-LDMOS device, respectively; because of the new structure and new structure SOI-LDMOS There is a silicon dioxide dielectric region in the drift region. The silicon dioxide dielectric region can increase the doping concentration of the drift region. Under the same bias voltage, its drain current will increase, and the surface gate will be transferred into the buried oxide layer. , which can enhance the electron injection ability. Therefore, the forward conduction performance of the SOI-LDMOS device with the new structure is better than that of the traditional SOI-LDMOS device and the traditional superjunction SOI-LDMOS device.

Table 1 below records the maximum value of transconductance (g _mMAX ), specific on-resistance R _on,sp , Baliga figure of merit FOM and breakdown voltage BV of the three devices, respectively. According to the table below, the maximum transconductance value (g _mMAX ) of the new structure SOI-LDMOS device is larger than that of the traditional SOI-LDMOS device and the traditional superjunction SOI-LDMOS device (g _mMAX ), because the new structure SOI On the basis of traditional devices, LDMOS devices transfer the surface gate to the buried oxide layer to form the internal gate, so that the control ability of the gate voltage of the device to the current is enhanced. Compared with the traditional SOI-LDMOS device and the traditional superjunction SOI-LDMOS device, the specific on-resistance R _on,sp of the new structure SOI-LDMOS device is also the smallest because of the presence of dioxide in the N-type drift region of the device. The silicon dielectric region and the silicon dioxide dielectric region can increase the doping concentration of the device drift region and then reduce the specific on-resistance of the device. The breakdown voltage of the SOI-LDMOS device with the new structure is slightly lower than that of the conventional SOI-LDMOS device and the conventional superjunction SOI-LDMOS device. The Baliga figure of merit FOM of the SOI-LDMOS device with the new structure is larger than that of the traditional SOI-LDMOS device and the traditional superjunction SOI-LDMOS device.

Table 1 Performance comparison of three devices

Fig. 7 shows that the doping concentrations of the SOI-LDMOS device with the new structure in the N-type drift region are 1.2×10 ¹⁶ cm ^-3 , 1.4×10 ¹⁶ cm ^-3 , 1.6×10 ¹⁶ cm ^-3 , and 1.8×10 ¹⁶ cm ^-3 , respectively , 2.0×10 ¹⁶ cm ^-3 and 2.2×10 ¹⁶ cm ^-3 , the breakdown voltage BV and the specific on-resistance R _on,sp change curve. As shown in Fig. 7, when the doping concentration of the N-type drift region is 1.8×10 ¹⁶ cm ^-3 , the breakdown voltage BV reaches a maximum value, and the breakdown voltage BV is 110V. At this time, the specific on-resistance R _{on , sp} is 6.0mΩ·cm ² . The specific on-resistance R _on,sp decreases with the increase of the doping concentration of the N-type drift region. The greater the doping concentration of the N-type drift region, the smaller the specific on-resistance R _on,sp ; When the doping concentration in the drift region is greater than 2.0×10 ¹⁶ cm ^-3 , the breakdown voltage BV decreases sharply.

Figure 8 is the change curve of the breakdown voltage BV and the specific on-resistance R _on,sp of the new structure SOI-LDMOS device when the silicon dioxide interlayer thickness is 0.4μm, 0.5μm, 0.6μm, 0.7μm and 0.8μm, respectively . It can be seen from Figure 8 that as the thickness of the silicon dioxide interposer increases, the breakdown voltage BV first increases and then decreases; when the thickness of the silicon dioxide interposer is 0.7 μm, the breakdown voltage BV reaches a maximum value. 110V, the specific on-resistance R _on,sp is 6.0mΩ·cm ² at this time. The specific on-resistance R _on,sp increases with the increase of the thickness of the silicon dioxide interposer, because the thickness of the silicon dioxide interposer increases, the thickness of the N-type drift region will decrease, which will lead to the effective conductive area decreases, so that the specific on-resistance R _on,sp increases.

FIG. 9 is a current line direction diagram of a new structure SOI-LDMOS device (the structure of which is shown in FIG. 1 ), a conventional SOI-LDMOS device and a conventional superjunction SOI-LDMOS device in a forward conduction state. As shown in Figure 9, the conductive channel of the SOI-LDMOS device with the new structure is in the body, and the current flows to the source through the channel in the body; while the conductive channel of the traditional SOI-LDMOS device and the traditional superjunction SOI-LDMOS device is on the surface, and the current flows to the source. flow to the source through the surface channel.

FIG. 10 is a comparison diagram of the electric field of Y=0.7 μm in the avalanche breakdown state of a new structure SOI-LDMOS device (the structure of which is shown in FIG. 1 ), a conventional SOI-LDMOS device and a conventional superjunction SOI-LDMOS device. As can be seen from Figure 10, the area enclosed by the electric field strength curve and the X axis of the traditional SOI-LDMOS device and the traditional superjunction SOI-LDMOS device is larger than that of the new structure SOI-LDMOS device, because the drift region of the traditional SOI-LDMOS device is The relatively low doping concentration and the presence of P-type pillars in the drift region of conventional superjunction SOI-LDMOS devices can assist in the depletion of the N-type drift region, so their electric field intensity distribution will be more uniform.

FIG. 11 is a distribution diagram of equipotential line pairs of a new structure SOI-LDMOS device (its structure is shown in FIG. 1 ), a conventional SOI-LDMOS device and a conventional superjunction SOI-LDMOS device under avalanche breakdown state. It can be seen from Figure 11 that the equipotential lines of the new structure SOI-LDMOS device, the traditional SOI-LDMOS device and the traditional superjunction SOI-LDMOS device are very uniformly distributed, but the equipotential lines in the middle part of the drift region of the new structure SOI-LDMOS device The distribution is relatively sparse.

A thin-layer SOI-LDMOS device with an internal channel proposed by the present invention, taking schematic diagram 1 as an example, the main process flow of which is shown in FIG. 12 . The specific implementation method includes: first, selecting an SOI substrate, and etching and filling the SOI substrate to form an internal gate. Next, vapor phase epitaxy is performed to grow an N-type drift region, and then ion implantation and diffusion processes are performed to form a source N+ region, a P-body, a source P+ region, and a source N+ region, respectively. Next, the N-type drift region is ion-etched to form a trench, and then chemical deposition is used to deposit silicon dioxide on the etched trench to form a silicon dioxide dielectric region, and the upper part of the silicon dioxide dielectric region and the P - Deposit a layer of SiO ₂ protective layer on the top of the body to form a field oxide layer. Finally, metal is deposited on the source and drain to form good ohmic contacts.

In the process of implementation, according to the design requirements of the specific device, a thin-layer SOI-LDMOS device with an internal channel proposed by the present invention, in the specific production, the substrate material can be silicon carbide SiC material, and silicon carbide can also be used. , gallium arsenide, indium phosphide or silicon germanium and other semiconductor materials instead of bulk silicon carbide.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be Modifications or equivalent replacements, without departing from the spirit and scope of the technical solution, should all be included in the scope of the claims of the present invention.

Claims (4)

1. A thin-layer SOI-LDMOS device having a conductive channel in the body, characterized in that: the field oxide layer is arranged on the silicon dioxide dielectric region (5), and comprises a source electrode contact region (1), a source electrode P + region (2), an N-type drift region (3), a field oxide layer (4), a silicon dioxide dielectric region (5), a drain electrode contact region (6), a drain electrode N + region (7), an oxygen buried layer (8), a substrate (9), an in-body gate oxide layer (10), a P-body (11), an in-body gate contact region (12) and a source electrode N + region (13); the source electrode contact region (1) is positioned above the source electrode N + region (13) and the source electrode P + region (2), and the right side of the source electrode contact region (1) is closely adjacent to the left side of the field oxide layer (4); the upper side of the source P + region (2) is bordered by the lower side of the source contact region (1), the lower side and the left side of the source P + region (2) are contacted with the source N + region (13), and meanwhile, the right side of the source P + region (2) is contacted with a part of the left side of the P-body (11); the upper side of the N-type drift region (3) is adjacent to the lower side of the silicon dioxide dielectric region (5), the left side of the N-type drift region is in contact with the right lower side of the P-body (11), the right side of the N-type drift region is adjacent to the left lower side of the drain electrode N + region (7), and the lower side of the N-type drift region is in contact with the upper side of the buried oxide layer (8); the field oxide layer (4) is positioned on the upper sides of the P-body (11) and the silicon dioxide medium region (5), the right side of the field oxide layer is close to the left side of the drain contact region (6), and the left side of the field oxide layer is in contact with the right side of the source contact region (1); the lower side of the silicon dioxide dielectric region (5) is in contact with the upper side of the N-type drift region (3), the left side of the silicon dioxide dielectric region is adjacent to the upper right side of the P-body (11), the right side of the silicon dioxide dielectric region is adjacent to the upper left side of the drain electrode N + region (7), and meanwhile, the upper side of the silicon dioxide dielectric region is in contact with the lower side of the field oxide layer (4); the drain contact region (6) is positioned right above the drain N + region (7), and the left side of the drain contact region (6) is adjacent to the right side of the field oxide layer (4); the drain electrode N + region (7) is positioned right below the drain electrode contact region (6), meanwhile, the left side of the drain electrode N + region is contacted with the silicon dioxide dielectric region (5) and the right side of the N-type drift region (3), and the lower side of the drain electrode N + region (7) is adjacent to the upper right side of the buried oxide layer (8); the lower side of the buried oxide layer (8) is close to the upper side of the substrate (9), the upper side of the buried oxide layer (8) is adjacent to the drain electrode N + region (7) and the lower side of the N-type drift region (3), meanwhile, the upper left side of the buried oxide layer (8) is close to the lower side of the in-body gate contact region (12), and the upper left side of the buried oxide layer (8) is in contact with the right sides of the in-body gate oxide layer (10) and the in-body gate contact region (12); the upper side of the substrate (9) is in contact with the lower side of the buried oxide layer (8), and the substrate is positioned at the bottom of the device; the lower edge of the internal gate oxide layer (10) is in contact with the upper edge of the internal gate contact region (12), the right side of the internal gate oxide layer is also in contact with the buried oxide layer (8), and meanwhile, the upper edge of the internal gate oxide layer (10) is in contact with the lower edges of the source N + region (13) and the P-body (11); the left side of the P-body (11) is contacted with the right sides of the source N + region (13) and the source P + region (2), meanwhile, the upper side of the P-body is adjacent to the lower left side of the field oxide layer (4), and the lower side of the P-body is contacted with the upper right side of the in-vivo gate oxide layer (10); the in-vivo gate contact region (12) is positioned on the upper left side of the buried oxide layer (8) and the lower side of the in-vivo gate oxide layer (10), and the right side of the in-vivo gate contact region is contacted with the buried oxide layer (8); the upper left side of the source electrode N + region (13) is in contact with the lower side of the source electrode contact region (1), the lower side of the source electrode N + region (13) is in contact with the upper side of the in-vivo gate oxide layer (10), the source electrode N + region is L-shaped, meanwhile, the rightmost side of the source electrode N + region (13) is in contact with the left lower side of the P-body (11), and the source electrode N + region (13) is also in contact with the lower side and the left side of the source electrode P + region (2).

2. The thin-layer SOI-LDMOS device as claimed in claim 1, wherein: the thickness of the silicon dioxide medium area (5) is in the range of 0.2-0.8 μm.

3. The thin-layer SOI-LDMOS device as claimed in claim 1, wherein: the in-body gate contact region (12) is doped polysilicon.

4. The thin-layer SOI-LDMOS device as claimed in claim 1, wherein: the N-type drift region (3) is doped with N-type impurities with a doping concentration range of 5 × 10 ¹⁵ ～5×10 ¹⁶ cm ^-3 。

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