CN108054202A - A kind of semiconductor structure and forming method thereof - Google Patents

A kind of semiconductor structure and forming method thereof Download PDF

Info

Publication number
CN108054202A
CN108054202A CN201810026243.0A CN201810026243A CN108054202A CN 108054202 A CN108054202 A CN 108054202A CN 201810026243 A CN201810026243 A CN 201810026243A CN 108054202 A CN108054202 A CN 108054202A
Authority
CN
China
Prior art keywords
area
region
doping type
type
drift region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201810026243.0A
Other languages
Chinese (zh)
Other versions
CN108054202B (en
Inventor
陆阳
黄必亮
周逊伟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Joulwatt Technology Co Ltd
Original Assignee
Joulwatt Technology Hangzhou Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Joulwatt Technology Hangzhou Co Ltd filed Critical Joulwatt Technology Hangzhou Co Ltd
Priority to CN201810026243.0A priority Critical patent/CN108054202B/en
Publication of CN108054202A publication Critical patent/CN108054202A/en
Application granted granted Critical
Publication of CN108054202B publication Critical patent/CN108054202B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The present invention provides a kind of semiconductor structure and forming method thereof, the forming method includes：Semiconductor substrate is provided, body area is formed in the Semiconductor substrate；Drift region is formed in the body area, the doping type of the drift region is opposite with the doping type in the body area；Channel region is formed in the body area, the channel region portions extend to the direction where the drift region, form at least one raceway groove extension area, interdigital distribution is formed between at least one raceway groove extension area and the drift region, the doping type of the channel region is identical with the doping type in the body area；Isolated area is formed in the drift region, the end of at least one raceway groove extension area is located at the lower section of the isolated area；Gate structure is formed in the semiconductor substrate surface；Source region is formed in the channel region of the gate structure one side, drain region is formed in the drift region, the drain region is located at one side of the isolated area away from the channel region.

Description

A kind of semiconductor structure and forming method thereof
The application for application number 2015100782107, on 2 13rd, 2015 applying date, denomination of invention " semiconductor structure and The divisional application of its forming method ".
Technical field
The present invention relates to field of semiconductor manufacture, and more particularly to a kind of semiconductor structure and forming method thereof.
Background technology
Lateral double diffusion metal oxide semiconductor (LDMOS) device is a kind of MOS device being lightly doped, with CMOS technology With extraordinary compatibility, and with good thermal stability and frequency stability, high gain and durability, low feedback Capacitance and resistance, are widely used in radio circuit.
Drain terminal is usually required in BCD techniques can bear the p-type LDMOS device of high pressure.In the prior art, conventional P The structure of type LDMOS device as depicted in figs. 1 and 2, including：Semiconductor substrate 100, the N traps 101 in Semiconductor substrate； Channel region 102 and drift region 103 in N traps 101；Isolated area 104 in drift region 103；Grid 105 is across raceway groove Area 102, N traps 101 and drift region 103 and part covering isolated area 104；Drain region 106 is located in drift region 103, source region 107 In in channel region 102.It can be obtained from Fig. 2, the surfaces of active regions electricity that the p-type LDMOS drain terminals grid and isolated area of this kind of structure have a common boundary Field is larger, the surfaces of active regions electric field that the breakdown voltage of device is limited to drain terminal grid and isolated area is had a common boundary, and breakdown voltage is relatively low.
To improve the breakdown voltage of p-type LDMOS, current method is to be led by additionally injecting one layer in drain region with drift region The opposite injection region of electric type, the injection region can change device distribution of charges and depletion region, improve the breakdown voltage of device.But In manufacturing process, one layer of mask plate need to additionally be increased by increasing the p-type LDMOS of injection region, not only increase manufacturing process, while Considerably increase manufacture cost.
The content of the invention
The present invention is provided a kind of with high-breakdown-voltage to overcome the problems, such as that existing LDMOS device breakdown potential is forced down Semiconductor structure and its manufacturing process.
To achieve these goals, technical solution of the present invention provides a kind of forming method of semiconductor structure, including：It carries For Semiconductor substrate, body area is formed in Semiconductor substrate；Drift region, doping type and the body area of drift region are formed in body area Doping type it is opposite；Channel region is formed in body area, channel region portions form at least one to the direction extension where drift region A raceway groove extension area forms interdigital distribution, the doping type of channel region between at least one raceway groove extension area and drift region It is identical with the doping type in body area；Isolated area is formed in drift region, the end of at least one raceway groove extension area is located at isolated area Lower section；Gate structure is formed in semiconductor substrate surface；Source region is formed in the channel region of gate structure one side, in drift region Interior formation drain region, drain region are located at one side of the isolated area away from channel region.
In one embodiment of the invention, the forming process of at least one raceway groove extension area is：In semiconductor substrate surface shape The channel region into channel region mask layer, on channel region mask layer at least one direction extension to where drift region injects window Mouthful, it is injected using channel region mask layer as mask, ditch is formed in the body area corresponding at least one channel region injection window Road extension area.
In one embodiment of the invention, at least one raceway groove extension area is contacted with drift region.
In one embodiment of the invention, there is setpoint distance between at least one raceway groove extension area and drift region.
In one embodiment of the invention, when semiconductor structure is p-type LDMOS, the doping type in body area and channel region Doping type is N-type, and the doping type of the doping type of drift region, the doping type of source region and drain region is p-type；When partly leading When body structure is N-type LDMOS, the doping type in body area and the doping type of channel region are p-type, the doping class of drift region The doping type of type, the doping type of source region and drain region is N-type.
In one embodiment of the invention, the implantation concentration of channel region is more than the implantation concentration of drift region, the injection of channel region The implantation concentration of concentration and drift region is 1017cm-3Magnitude.
Technical solution of the present invention also provides a kind of semiconductor structure, including Semiconductor substrate, body area, drift region, channel region, Isolated area, gate structure, source region and drain region.Body area is located in Semiconductor substrate；Drift region is located in body area, and drift region is mixed The doping type in miscellany Xing Yuti areas is opposite；Channel region is located in body area, and channel region portions extend to the direction where drift region, At least one raceway groove extension area is formed, interdigital distribution, channel region are formed between at least one raceway groove extension area and drift region Doping type it is identical with the doping type in body area；Isolated area is located in drift region, the end position of at least one raceway groove extension area In the lower section of isolated area；Gate structure is located at the surface of Semiconductor substrate；Source region is located in the channel region of gate structure one side；Leakage Area is located in drift region and positioned at one side of the isolated area away from channel region.
In one embodiment of the invention, the shape of at least one raceway groove extension area is the rectangle or trapezoidal of strip.
In one embodiment of the invention, at least one raceway groove extension area is in contact with drift region.
In one embodiment of the invention, there is setpoint distance between at least one raceway groove extension area and drift region.
In one embodiment of the invention, when semiconductor structure is p-type LDMOS, the doping type in body area and channel region Doping type is N-type, and the doping type of the doping type of drift region, the doping type of source region and drain region is p-type；When partly leading When body structure is N-type LDMOS, the doping type in body area and the doping type of channel region are p-type, the doping type of drift region, The doping type of source region and the doping type in drain region are N-type.
In one embodiment of the invention, isolated area is local field oxygen isolation area or shallow trench isolation region.
Compared with prior art, technical scheme has the following advantages：
Semiconductor structure provided by the invention and forming method thereof forms channel region and drift region, channel region in body area Part forms at least one raceway groove extension area to the direction extension where drift region.At least one raceway groove extension area and drift region Between formed interdigital distribution.The setting causes longitudinal direction of the semiconductor structure provided by the invention between body area and drift region While PN junction forms depletion region, having lateral depletion area is formed between raceway groove extension area and drift region, which to leak The surface field for the active area that end grid and isolated area are had a common boundary is reduced, so as to improve the breakdown voltage of device.
Further, raceway groove extension area and drift region can be set to contact, form transverse p/n junction between the two, the transverse p/n junction Having lateral depletion can be realized under smaller reverse biased.But since the longitudinal P N knots in body area and drift section are same what is longitudinally exhausted When also can transversely exhaust, therefore, design when raceway groove extension area and drift region can be set to be not directly contacted with, have between the two Setpoint distance.Enter when having lateral depletion is occurring for the longitudinal P N knots in body area and drift section in raceway groove extension area, with additional The increase of voltage, transversely gradually exhausts between drift region and raceway groove extension area, and equally can reach reduces drain terminal grid and isolated area The effect of the surface field of the active area of boundary.For ease of device production and meet design rule, raceway groove extension area is set Shape is the rectangle or trapezoidal of strip.
For above and other objects of the present invention, feature and advantage can be clearer and more comprehensible, preferred embodiment cited below particularly, And coordinate attached drawing, it is described in detail below.
Description of the drawings
Fig. 1 show the structure diagram of existing p-type LDMOS device.
Fig. 2 show cross-sectional view of the p-type LDMOS device along AA ' lines in Fig. 1.
Fig. 3 to Fig. 9 show the structure diagram of the forming process of the semiconductor structure of one embodiment of the invention offer.
Figure 10 show the structure diagram of the semiconductor structure of one embodiment of the invention offer.
Specific embodiment
It please refers to Fig.1 and Fig. 2, wherein Fig. 2 is diagrammatic cross-sections of the Fig. 1 along AA ' lines.The system of existing p-type LDMOS device In work, since the active area of drain terminal grid and isolated area boundary has larger surface field, which limits p-type LDMOS device breakdown voltage.Inventor it has been investigated that, the surface electricity for the active area being had a common boundary by reducing drain terminal grid and isolated area Field can effectively improve the breakdown voltage of LDMOS device.
For this purpose, the present invention provides a kind of semiconductor structure and forming method thereof, by forming interdigital point in body area The channel region of cloth and drift region form having lateral depletion between the raceway groove extension area and drift region on channel region.The having lateral depletion exists The active area that the length direction of gate structure extends to entire drain terminal grid and isolated area is had a common boundary, the setting can effectively reduce drain terminal grid The surface field for the active area having a common boundary with isolated area, so as to achieve the effect that improve semiconductor structure breakdown voltage.
Specific embodiments of the present invention are described in detail below in conjunction with attached drawing.When describing the embodiments of the present invention, it is Convenient for explanation, schematic diagram can disobey general proportion and make partial enlargement, and the schematic diagram is example, should not be limited herein Protection scope of the present invention.In addition, the three-dimensional space of length, width and depth should be included in actual fabrication.
Fig. 3 to Fig. 9 show the structure diagram of the forming process of semiconductor structure provided in this embodiment.Wherein, Fig. 7 Position to the hatching of Fig. 9 is identical with the position of the hatching of Fig. 5.
First, as shown in figure 3, providing Semiconductor substrate 200, body area 201, body area 201 are formed in Semiconductor substrate 200 The doping type of doping type and Semiconductor substrate 200 isolate on the contrary, forming PN junction between the two.In this present embodiment, half The material of conductor substrate 200 be silicon, doping type P.However, the present invention is not limited in any way this.In other embodiments In, semi-conducting material 200 can be germanium, SiGe, carborundum, silicon-on-insulator or germanium on insulator.
In this present embodiment, body area 201 is formed by the way of extension.The body area 201 being epitaxially formed has uniform miscellaneous Matter is distributed, doping concentration 1016cm-3Magnitude.However, the present invention is not limited in any way this.In other embodiments, body area 201, which can be used trap injection technology, forms.Since semiconductor structure provided in this embodiment is p-type LDMOS, N is adulterated in body area 201 Type foreign ion, including the first in phosphonium ion, arsenic ion or antimony ion or several.However, the present invention does not make this any limit It is fixed.In other embodiments, when the semiconductor structure of formation is N-type LDMOS, doped p-type foreign ion in body area 201, bag Include one or more of boron ion, gallium ion or indium ion.
Then, with reference to figure 4 to Fig. 6.Fig. 4 show bowing behind the interior formation drift region 204 in body area 201 and channel region 203 View.Fig. 5 show cross-sectional views of the Fig. 4 along BB ' lines, and Fig. 6 show cross-sectional views of the Fig. 4 along CC ' lines.
First, drift region mask layer is formed in body area 201, there are one drift regions to inject window for tool on the mask layer of drift region Mouthful, by trap implanting p-type foreign ion in drift region injection window, form drift region 204.However, the present invention to this not It is limited in any way.When the semiconductor structure of formation is N-type LDMOS, body area 201 can inject N-type impurity ion come shape by trap Into drift region.To improve breakdown voltage, set drift region 204 that there is relatively low doping concentration, doping concentration 1017cm-3Amount Grade.Preferably, the doping concentration for setting drift region 204 is 1E17cm-3.However, the present invention is not limited in any way this.
Then, channel region 203 is formed in body area 201, specific forming process is as follows：Ditch is formed on 201 surface of body area There is on channel region mask layer road area mask layer the channel region that at least one direction to where drift region 204 extends to inject window Mouthful, trap injection is carried out to channel region 203 by mask of channel region mask layer, the concentration of injection is 1017cm-3Magnitude.Channel region is noted Enter the body area 201 corresponding to window and form raceway groove extension area 205.Preferably, the doping concentration of setting channel region 203 is 5E17cm-3.However, the present invention is not limited in any way this.
In this present embodiment, channel region injection window shape be strip rectangle, the doping type of channel region 203 with The doping type in body area 201 is identical, is N-type impurity ion.However, the present invention does this any restriction.In other embodiments In, the channel region injection window on trench mask layer can be the other figures for meeting design rule, such as trapezoidal；Work as semiconductor junction When structure is N-type LDMOS, the impurity that channel region 203 injects is p type impurity ion.
In this present embodiment, there are one the channel regions extended to the direction where drift region 204 for tool on channel region mask layer Window is injected, corresponding, there are one raceway groove extension areas 205 for tool on channel region 204 after injection.However, the present invention does not make this Any restriction.In other embodiments, there can be more than two raceway groove extension areas 205 on channel region 204.
In this present embodiment, channel region mask layer and drift region mask layer are silica.However, the present invention does not make this Any restriction.In other embodiments, channel region mask layer and drift region mask layer can be silicon nitride.
Since the implantation concentration of channel region 203 is higher than the implantation concentration of drift region 204, raceway groove extension area 205 can make drift 204 transoid of area forms PN junction.Therefore the present invention is not limited in any way the concrete structure of drift region mask layer.Drift region mask layer Concrete structure can be the finger-like to match with channel region mask layer, the strip rectangle or other in traditional LDMOS structure Meet the structure of design rule.
Structure as shown in Figure 4 is ultimately formed after channel region injects.In this configuration to there are 205 institutes of raceway groove extension area Position and there is no raceway groove extension 205 where position to be respectively formed sectional view.Wherein, Fig. 5 is Fig. 4 cuing open along BB ' lines View, Fig. 6 are sectional views of the Fig. 4 along CC ' lines.
In Figure 5, raceway groove extension area 205 is contacted with drift region 204, forms horizontal PN junction between the two, when drain-source it Between plus during reverse phase bias, raceway groove extension area 205 and drift region 204 transversely exhaust and should in the length direction of gate structure 206 The active area that having lateral depletion area extends to entire drain terminal grid and isolated area is had a common boundary.Having lateral depletion causes the surface electricity of drift region 204 , after especially forming isolated area, the surfaces of active regions electric field of drain terminal grid and isolated area boundary is minimized.The drop of surface field It is low breakdown voltage to be improved.
And in figure 6 since its structure is identical with traditional p-type LDMOS structure, when adding forward bias between drain-source, lead The parameters such as resistance that are powered can't change.Therefore, semiconductor structure provided in this embodiment by drain terminal optimization design, makes It obtains and interdigital distribution is formed between channel region 203 and drift region 204, can be obtained in the case where not changing the other characteristics of device To higher breakdown voltage.Further, since drain terminal injection need not be added, one layer of mask plate is reduced at the production moment, significantly Reduce production cost.
In semiconductor structure shown in Fig. 4, in addition to the transverse p/n junction between channel region 203 and drift region 204, also exist Longitudinal P N knots between drift region 204 and body area 201.Therefore, in other embodiments, raceway groove extension area 205 and drift can be set It moves between area 204 with setpoint distance, the longitudinal P N which is less than between drift region 204 and body area 201 is tied transversely Exhaust distance.When applying reverse phase bias between drain-source, longitudinal P N knots exhaust and enter raceway groove extension area 205 in transverse direction When, having lateral depletion is formed between raceway groove extension area 205 and drift region 204, equally reaches reduction drain terminal grid and isolated area 202 is had a common boundary Active area surface field, improve the purpose of breakdown voltage.
With reference to figure 7, isolated area 202 is formed in drift region 204, the end of raceway groove extension area 205 is located at isolated area 202 Lower section.In this present embodiment, isolated area 202 is shallow trench isolation region, and specific forming process is：It is passed through on the surface of drift region 204 The isolation channel that depth is less than the depth of drift region 204 is formed after mask, photoetching and etching, isolated material is filled in isolation channel Shallow trench isolation region is eventually formed, isolated material can be silica, silicon nitride etc..However, specific knot of the present invention to isolated area 202 Structure and its formation order are not limited in any way.In other embodiments, isolated area 202 can be formed in Xian Ti areas 201, then into Row trap injects to form channel region 201 and drift region 204, isolated area 202 or formed after local oxidation in beak-like Local field oxygen isolation area.
Then, with reference to Fig. 8, gate structure is formed in the Semiconductor substrate 200 for forming channel region 203 and drift region 204 206.206 one side of gate structure is located at 203 top of channel region, and opposite side is located at the top of isolated area 205.Gate structure 206 wraps It includes the gate dielectric layer 207 positioned at 200 surface of Semiconductor substrate, the gate electrode 208 on gate dielectric layer 207 and is situated between positioned at grid The side wall (not shown) of 208 both sides side wall of matter layer 207 and gate electrode.In this present embodiment, the material of gate dielectric layer 207 can be Silica, gate electrode 208 can be polysilicon, and side wall includes silica and silicon nitride.However, the present invention does not make this any limit It is fixed.In other embodiments, gate dielectric layer 207 can be high dielectric constant material, and gate electrode 208 can be metal.
Finally, Fig. 9 is refer to, source region 209 is formed in the channel region 203 of 206 one side of gate structure, in gate structure Drain region 210 is formed in the drift region 204 of 206 opposite side, drain region 210 is located at one side of the isolated area 202 away from channel region 203. In this present embodiment, source region 209 and drain region 210 are formed by the way of ion implanting, and the doping type of source region 209 and leakage The doping type in the doping type Jun Yuti areas 201 in area 210 is on the contrary, be p-type.However, the present invention is not limited in any way this. In other embodiments, when semiconductor structure is N-type LDMOS, the doping type of source region 209 and the doping type in drain region 210 It is N-type.
The semiconductor structure formed using the above method, channel region 203 are extended to the direction where drift region 204, raceway groove Interdigital distribution is formed between extension area 205 and drift region 204.When adding reverse phase bias between drain-source, 205 He of raceway groove extension area It is transversely exhausted between drift region 204, which can effectively reduce the table of drain terminal grid and the active area of the boundary of isolated area 205 Face electric field, so as to achieve the purpose that improve breakdown voltage.In addition, in addition to raceway groove extension area 205, using the half of above method formation The structure of conductor structure other parts is identical with the structure of traditional p-type LDMOS, and the electricity that can still retain traditional p-type LDMOS is special Property.
Corresponding with the forming method of above-mentioned semiconductor structure, the present embodiment also provides a kind of semiconductor structure, specifically It refer to Figure 10.Figure 10 show the top view of semiconductor structure provided in this embodiment.Semiconductor junction provided in this embodiment Structure includes：
Semiconductor substrate 200, in this present embodiment, the doping type of Semiconductor substrate is p-type；
Doping type in Semiconductor substrate 200 is NXing Ti areas 201.However, the present invention does not make this any limit It is fixed.In other embodiments, when semiconductor structure is p-type LDMOS, the doping type in body area 201 is p-type, correspondingly, partly leading The doping type of body substrate 200 is N-type.
Drift region 204 in body area 201, the doping type of drift region 204 are opposite with the doping type in body area 201. The doping type of drift region 204 is p-type in this present embodiment.However, the present invention is not limited in any way this.In other embodiments In, when semiconductor structure is p-type LDMOS, the doping type of drift region 204 is N-type.
Channel region 203 in body area, the doping type of channel region 203 is identical with the doping type in body area 201, Yu Ben The doping type of channel region 203 is N-type in embodiment.203 part of channel region to the direction where drift region 204 extend to form to A few raceway groove extension area 205 forms interdigital distribution between at least one raceway groove extension area 205 and drift region 204.Yu Ben In embodiment, there are one raceway groove extension areas 205 for tool on channel region 203.However, the present invention is not limited in any way this.In other In embodiment, there can be more than two raceway groove extension areas 205 on channel region 203.
Isolated area 202 in drift region 204.In this present embodiment, isolated area 202 is less than body area 201 for depth The shallow trench isolation region of depth.However, the present invention is not limited in any way this.In other embodiments, isolated area 202 can be local Field oxygen isolation area.
Gate structure 206 positioned at the surface of Semiconductor substrate 200, the one side of gate structure 206 are located at channel region 203 Top, opposite side are located at the top of isolated area 202.In this present embodiment, gate structure 206 includes being located at Semiconductor substrate 200 The gate dielectric layer 207 on surface, the gate electrode 208 on gate dielectric layer 207 and positioned at gate dielectric layer 207 and gate electrode 208 The side wall of both sides side wall.
Source region 209 in the channel region 203 of 206 one side of gate structure；
In body area 201 and positioned at the drain region 210 of one side of the isolated area 202 away from channel region 203.In the present embodiment In, the doping type of source region 209 is identical with the doping type in drain region 210, is p-type.However, the present invention does not make this any limit It is fixed.In other embodiments, when semiconductor structure is N-type LDMOS, the doping type of source region 209 and the doping class in drain region 210 Type is identical, is N-type.
Compared with prior art, technical scheme has the following advantages：
Semiconductor structure provided by the invention and forming method thereof forms channel region 203 and drift region in body area 201 204,203 part of channel region extends to the direction where drift region 204, forms at least one raceway groove extension area 205.It is at least one Interdigital distribution is formed between raceway groove extension area 205 and drift region 204.The setting causes semiconductor structure provided by the invention While longitudinal P N between body area 201 and drift region 204 ties to form depletion region, channel region extension area 205 and drift region 204 Between form having lateral depletion area, the surface field for the active area which causes drain terminal grid and isolated area is had a common boundary is dropped It is low, so as to improve the breakdown voltage of device.
Further, raceway groove extension area 205 and drift region 204 can be set to contact, form transverse p/n junction between the two, the horizontal stroke Having lateral depletion can be realized under smaller reverse biased to PN junction.But since the longitudinal P N knots between body area 201 and drift region 204 exist Longitudinal direction also can transversely exhaust while exhausting, and therefore, in design raceway groove extension area 205 and drift region 204 can be set not straight Contact, between the two with setpoint distance, when the longitudinal P N between body area 201 and drift region 204 is tied when having lateral depletion occurs Into in channel region 203, with the increase of applied voltage, transversely gradually exhausted between drift region 204 and channel region 203, together Sample can reach the effect of the surface field for the active area for reducing drain terminal grid and isolated area boundary.For ease of device production and meet Design rule, the shape for setting raceway groove extension area are the rectangle or trapezoidal of strip.
Although the present invention is disclosed above by preferred embodiment, the present invention, this any known skill are not limited to Skill person without departing from the spirit and scope of the present invention, can make a little change and retouch, therefore protection scope of the present invention is worked as Subject to claims scope claimed.

Claims (10)

1. a kind of forming method of semiconductor structure, which is characterized in that including：
Semiconductor substrate is provided, body area is formed in the Semiconductor substrate；
Drift region is formed in the body area, the doping type of the drift region is opposite with the doping type in the body area；
Channel region is formed in the body area, the channel region portions are formed at least to the direction extension where the drift region One raceway groove extension area forms interdigital distribution, the ditch between at least one raceway groove extension area and the drift region The doping type in road area is identical with the doping type in the body area；
Isolated area is formed in the drift region, the end of at least one raceway groove extension area is located under the isolated area Side；
Gate structure is formed in the semiconductor substrate surface；
Source region is formed in the channel region of the gate structure one side, drain region is formed in the drift region, the drain region is located at One side of the isolated area away from the channel region.
2. the forming method of semiconductor structure according to claim 1, which is characterized in that at least one raceway groove extension The forming process in area is：Channel region mask layer is formed in semiconductor substrate surface, has at least one on the channel region mask layer The channel region of a direction extension to where the drift region injects window, is noted using the channel region mask layer as mask Enter, raceway groove extension area is formed in the body area corresponding at least one channel region injection window.
3. the forming method of semiconductor structure according to claim 1 or 2, which is characterized in that at least one raceway groove Extension area is contacted with the drift region.
4. the forming method of semiconductor structure according to claim 1 or 2, which is characterized in that at least one raceway groove There is setpoint distance between extension area and the drift region.
5. the forming method of semiconductor structure according to claim 1, which is characterized in that when the semiconductor structure is P During type LDMOS, the doping type in the body area and the doping type of channel region are N-type, the doping type of the drift region, source The doping type in area and the doping type in drain region are p-type；When the semiconductor structure is N-type LDMOS, the body area The doping type of doping type and channel region is p-type, the doping type of the drift region, the doping type of source region and drain region Doping type be N-type.
6. the forming method of semiconductor structure according to claim 1, which is characterized in that the implantation concentration of the channel region More than the implantation concentration of drift region, the implantation concentration of the channel region and the implantation concentration of drift region are 1017cm-3Magnitude.
7. a kind of semiconductor structure, which is characterized in that including：
Semiconductor substrate；
Body area, in the Semiconductor substrate；
Drift region, in the body area, the doping type of the drift region is opposite with the doping type in the body area；
Channel region, in the body area, the channel region portions form at least one to the direction extension where the drift region A raceway groove extension area forms interdigital distribution, the raceway groove between at least one raceway groove extension area and the drift region The doping type in area is identical with the doping type in the body area；
Isolated area, in the drift region, the end of at least one raceway groove extension area is located at the lower section of the isolated area；
Gate structure, positioned at the surface of the Semiconductor substrate；
Source region, in the channel region of the gate structure one side；
Drain region, in the drift region and positioned at one side of the isolated area away from the channel region.
8. semiconductor structure according to claim 7, which is characterized in that at least one raceway groove extension area and the drift Area is moved to be in contact.
9. semiconductor structure according to claim 7, which is characterized in that at least one raceway groove extension area and the drift It moves between area with setpoint distance.
10. semiconductor structure according to claim 7, which is characterized in that when the semiconductor structure is p-type LDMOS, The doping type in the body area and the doping type of channel region are N-type, the doping type of the drift region, the doping class of source region Type and the doping type in drain region are p-type；When the semiconductor structure be N-type LDMOS when, the doping type in the body area and The doping type of channel region is p-type, the doping type of the doping type of the drift region, the doping type of source region and drain region It is N-type.
CN201810026243.0A 2015-02-13 2015-02-13 Semiconductor structure and forming method thereof Active CN108054202B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201810026243.0A CN108054202B (en) 2015-02-13 2015-02-13 Semiconductor structure and forming method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510078210.7A CN104599974B (en) 2015-02-13 2015-02-13 Semiconductor structure and forming method thereof
CN201810026243.0A CN108054202B (en) 2015-02-13 2015-02-13 Semiconductor structure and forming method thereof

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CN201510078210.7A Division CN104599974B (en) 2015-02-13 2015-02-13 Semiconductor structure and forming method thereof

Publications (2)

Publication Number Publication Date
CN108054202A true CN108054202A (en) 2018-05-18
CN108054202B CN108054202B (en) 2020-11-03

Family

ID=53125667

Family Applications (3)

Application Number Title Priority Date Filing Date
CN201810026243.0A Active CN108054202B (en) 2015-02-13 2015-02-13 Semiconductor structure and forming method thereof
CN201510078210.7A Active CN104599974B (en) 2015-02-13 2015-02-13 Semiconductor structure and forming method thereof
CN201811207907.XA Active CN109273364B (en) 2015-02-13 2015-02-13 Semiconductor structure and forming method thereof

Family Applications After (2)

Application Number Title Priority Date Filing Date
CN201510078210.7A Active CN104599974B (en) 2015-02-13 2015-02-13 Semiconductor structure and forming method thereof
CN201811207907.XA Active CN109273364B (en) 2015-02-13 2015-02-13 Semiconductor structure and forming method thereof

Country Status (1)

Country Link
CN (3) CN108054202B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111710723A (en) * 2020-07-16 2020-09-25 杰华特微电子（杭州）有限公司 Lateral double-diffused transistor and manufacturing method thereof

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108054202B (en) * 2015-02-13 2020-11-03 杰华特微电子（杭州）有限公司 Semiconductor structure and forming method thereof
CN109119472A (en) * 2018-07-18 2019-01-01 北京顿思集成电路设计有限责任公司 A kind of LDMOS device structure and preparation method thereof
US20230268436A1 (en) * 2022-02-24 2023-08-24 Globalfoundries Singapore Pte. Ltd. Extended-drain metal-oxide-semiconductor devices with a gap between the drain and body wells

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130069153A1 (en) * 2011-09-17 2013-03-21 Richtek Technology Corporation, R.O.C. High Voltage Device and Manufacturing Method Thereof
CN103077895A (en) * 2012-12-19 2013-05-01 上海宏力半导体制造有限公司 Laterally diffused metal oxide semiconductor (LDMOS) transistor and formation method thereof
CN104599974A (en) * 2015-02-13 2015-05-06 杰华特微电子（杭州）有限公司 Semiconductor structure and forming method thereof
CN204464292U (en) * 2015-02-13 2015-07-08 杰华特微电子（杭州）有限公司 Semiconductor structure

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69509494T2 (en) * 1995-02-24 1999-10-07 Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno, Catania Power device as an integrated structure in MOS technology and method for its production
JP2010045130A (en) * 2008-08-11 2010-02-25 Nec Electronics Corp Semiconductor device and method for producing the same
DE102008051245B4 (en) * 2008-10-10 2015-04-02 Austriamicrosystems Ag High-voltage transistor with high current carrying capacity and method of manufacture
CN103208519B (en) * 2012-01-12 2015-12-09 上海华虹宏力半导体制造有限公司 With NLDMOS structure and the method for making thereof of 5 volts of CMOS technology compatibilities

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130069153A1 (en) * 2011-09-17 2013-03-21 Richtek Technology Corporation, R.O.C. High Voltage Device and Manufacturing Method Thereof
CN103077895A (en) * 2012-12-19 2013-05-01 上海宏力半导体制造有限公司 Laterally diffused metal oxide semiconductor (LDMOS) transistor and formation method thereof
CN104599974A (en) * 2015-02-13 2015-05-06 杰华特微电子（杭州）有限公司 Semiconductor structure and forming method thereof
CN204464292U (en) * 2015-02-13 2015-07-08 杰华特微电子（杭州）有限公司 Semiconductor structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111710723A (en) * 2020-07-16 2020-09-25 杰华特微电子（杭州）有限公司 Lateral double-diffused transistor and manufacturing method thereof
CN111710723B (en) * 2020-07-16 2022-09-16 杰华特微电子股份有限公司 Lateral double-diffused transistor and manufacturing method thereof

Also Published As

Publication number Publication date
CN108054202B (en) 2020-11-03
CN109273364A (en) 2019-01-25
CN109273364B (en) 2021-10-01
CN104599974B (en) 2019-05-03
CN104599974A (en) 2015-05-06

Similar Documents

Publication Publication Date Title
CN105448979B (en) Horizontal dual pervasion field effect pipe and forming method thereof
US8772871B2 (en) Partially depleted dielectric resurf LDMOS
US7233018B2 (en) High voltage MOSFET having Si/SiGe heterojuction structure and method of manufacturing the same
CN103022140B (en) Lateral transistor and method for manufacturing the same
US7816744B2 (en) Gate electrodes of HVMOS devices having non-uniform doping concentrations
CN107093622B (en) Longitudinal super-junction double-diffusion metal oxide semiconductor field effect transistor with semi-insulating polycrystalline silicon layer
CN104599974B (en) Semiconductor structure and forming method thereof
CN105448916A (en) Transistor and method of forming same
US20220359750A1 (en) Transistor structure and manufacturing method of the same
CN107579119B (en) Longitudinal super-junction double-diffusion metal oxide semiconductor field effect transistor with composite dielectric layer and manufacturing method thereof
CN106571388A (en) Crosswise diffusion metal oxide semiconductor field effect tube possessing RESURF structure
CN108565286B (en) high-K dielectric groove transverse double-diffusion metal oxide semiconductor field effect transistor and manufacturing method thereof
CN108198850B (en) high-K dielectric trench transverse super-junction double-diffusion metal oxide wide band gap semiconductor field effect transistor and manufacturing method thereof
CN107546274B (en) LDMOS device with step-shaped groove
KR20100067567A (en) Semiconductor device and method for manufacturing the same
CN104409500B (en) Radio frequency LDMOS and preparation method thereof
US9105721B2 (en) Semiconductor device and manufacturing method thereof
CN104201203B (en) High withstand voltage LDMOS device and manufacture method thereof
CN102694020B (en) Semiconductor device
CN211017082U (en) Super junction type MOSFET device
CN204464292U (en) Semiconductor structure
CN107591450B (en) Semiconductor longitudinal super-junction double-diffusion metal oxide semiconductor field effect transistor with composite dielectric layer wide band gap and manufacturing method thereof
KR20100072405A (en) Semiconductor device, method of fabricating the same and flash memory device
CN106548943A (en) Transistor and forming method thereof
CN111081777A (en) Double-channel transverse super-junction double-diffusion metal oxide semiconductor field effect transistor and manufacturing method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
CB02 Change of applicant information
CB02 Change of applicant information

Address after: Room 901-23, 9 / F, west 4 building, Xigang development center, 298 Zhenhua Road, Sandun Town, Xihu District, Hangzhou City, Zhejiang Province

Applicant after: JOULWATT TECHNOLOGY (HANGZHOU) Co.,Ltd.

Address before: Hangzhou City, Zhejiang province Yuhang District 311121 West Street warehouse before No. 1500 Building 1 room 424

Applicant before: JOULWATT TECHNOLOGY (HANGZHOU) Co.,Ltd.

GR01 Patent grant
GR01 Patent grant
CP01 Change in the name or title of a patent holder
CP01 Change in the name or title of a patent holder

Address after: Room 901-23, 9 / F, west 4 building, Xigang development center, 298 Zhenhua Road, Sandun Town, Xihu District, Hangzhou City, Zhejiang Province, 310030

Patentee after: Jiehuate Microelectronics Co.,Ltd.

Address before: Room 901-23, 9 / F, west 4 building, Xigang development center, 298 Zhenhua Road, Sandun Town, Xihu District, Hangzhou City, Zhejiang Province, 310030

Patentee before: JOULWATT TECHNOLOGY (HANGZHOU) Co.,Ltd.