CN104599974B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN104599974B
CN104599974B CN201510078210.7A CN201510078210A CN104599974B CN 104599974 B CN104599974 B CN 104599974B CN 201510078210 A CN201510078210 A CN 201510078210A CN 104599974 B CN104599974 B CN 104599974B
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channel
doping type
type
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CN104599974A (en
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陆阳
黄必亮
周逊伟
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Joulwatt Technology Co Ltd
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Joulwatt Technology Hangzhou Co Ltd
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Priority to CN201811207907.XA priority patent/CN109273364B/en
Priority to CN201810026243.0A priority patent/CN108054202B/en
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors

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Abstract

The present invention provides a kind of semiconductor structure and forming method thereof, the forming method includes: offer semiconductor substrate, and body area is formed in the semiconductor substrate；Drift region is formed in the body area, the doping type of the drift region is opposite with the doping type in the body area；Channel region is formed in the body area, direction where from the channel region portions to the drift region extends, form at least one channel extension area, interdigital distribution is formed between at least one described channel extension area and the drift region, the doping type of the channel region is identical as the doping type in the body area；Isolated area is formed in the drift region, the end of at least one channel extension area is located at the lower section of the isolated area；Gate structure is formed in the semiconductor substrate surface；Source region is formed in the channel region of the gate structure side, forms drain region in the drift region, the drain region is located at side of the isolated area far from the channel region.

Description

Semiconductor structure and forming method thereof
Technical field
The present invention relates to field of semiconductor manufacture, and in particular to a kind of semiconductor structure and forming method thereof.
Background technique
Lateral double diffusion metal oxide semiconductor (LDMOS) device is a kind of MOS device being lightly doped, with CMOS technology With extraordinary compatibility, and there is good thermal stability and frequency stability, high gain and durability, low feedback Capacitor and resistance, are widely used in radio circuit.
Drain terminal is usually required in BCD technique can bear the p-type LDMOS device of high pressure.In the prior art, conventional P The structure of type LDMOS device is as depicted in figs. 1 and 2, comprising: semiconductor substrate 100, the N trap 101 in semiconductor substrate； Channel region 102 and drift region 103 in N trap 101；Isolated area 104 in drift region 103；Grid 105 is across channel Area 102, N trap 101 and drift region 103 and part covering isolated area 104；Drain region 106 is located in drift region 103, and source region 107 In in channel region 102.It can be obtained from Fig. 2, the surfaces of active regions electricity that the p-type LDMOS drain terminal grid and isolated area of this kind of structure have a common boundary Field is larger, the surfaces of active regions electric field that the breakdown voltage of device is limited to drain terminal grid and isolated area is had a common boundary, and breakdown voltage is lower.
For the breakdown voltage for improving p-type LDMOS, current method is to be led by additionally injecting one layer in drain region with drift region The opposite injection region of electric type, the injection region can be changed device distribution of charges and depletion region, improve the breakdown voltage of device.But In manufacturing process, the p-type LDMOS for increasing injection region need to additionally increase by one layer of mask plate, not only increase manufacturing process, while Considerably increase manufacturing cost.
Summary of the invention
The present invention provides a kind of with high-breakdown-voltage to overcome the problems, such as that existing LDMOS device breakdown potential is forced down Semiconductor structure and its manufacturing process.
To achieve the goals above, technical solution of the present invention provides a kind of forming method of semiconductor structure, comprising: mentions For semiconductor substrate, body area is formed in semiconductor substrate；Drift region, the doping type of drift region and body area are formed in body area Doping type it is opposite；Channel region is formed in body area, the direction where channel region portions to drift region extends, and forms at least one A channel extension area forms interdigital distribution, the doping type of channel region between at least one channel extension area and drift region It is identical as the doping type in body area；Isolated area is formed in drift region, the end of at least one channel extension area is located at isolated area Lower section；Gate structure is formed in semiconductor substrate surface；Source region is formed in the channel region of gate structure side, in drift region Interior formation drain region, drain region are located at side of the isolated area far from channel region.
In one embodiment of the invention, the forming process of at least one channel extension area are as follows: in semiconductor substrate surface shape At channel region mask layer, window is injected at least one channel region extended to the direction where drift region on channel region mask layer Mouthful, it is injected using channel region mask layer as exposure mask, forms ditch in the body area corresponding at least one channel region injection window Road extension area.
In one embodiment of the invention, at least one channel extension area is contacted with drift region.
In one embodiment of the invention, there is set distance between at least one channel extension area and drift region.
In one embodiment of the invention, when semiconductor structure is p-type LDMOS, the doping type in body area and channel region Doping type is N-type, and the doping type of the doping type of drift region, the doping type of source region and drain region is p-type；When partly leading When body structure is N-type LDMOS, the doping type in body area and the doping type of channel region are p-type, the doping class of drift region The doping type of type, the doping type of source region and drain region is N-type.
In one embodiment of the invention, the implantation concentration of channel region is greater than the implantation concentration of drift region, the injection of channel region The implantation concentration of concentration and drift region is 1017cm-3Magnitude.
Technical solution of the present invention also provides a kind of semiconductor structure, including semiconductor substrate, body area, drift region, channel region, Isolated area, gate structure, source region and drain region.Body area is located in semiconductor substrate；Drift region is located in body area, and drift region is mixed The doping type in the area miscellany Xing Yuti is opposite；Channel region is located in body area, and the direction where channel region portions to drift region extends, At least one channel extension area is formed, forms interdigital distribution, channel region between at least one channel extension area and drift region Doping type it is identical as the doping type in body area；Isolated area is located in drift region, the end position of at least one channel extension area In the lower section of isolated area；Gate structure is located at the surface of semiconductor substrate；Source region is located in the channel region of gate structure side；Leakage Area is located in drift region and is located at side of the isolated area far from channel region.
In one embodiment of the invention, the shape of at least one channel extension area is the rectangle or trapezoidal of strip.
In one embodiment of the invention, at least one channel extension area is in contact with drift region.
In one embodiment of the invention, there is set distance between at least one channel extension area and drift region.
In one embodiment of the invention, when semiconductor structure is p-type LDMOS, the doping type in body area and channel region Doping type is N-type, and the doping type of the doping type of drift region, the doping type of source region and drain region is p-type；When partly leading When body structure is N-type LDMOS, the doping type in body area and the doping type of channel region are p-type, the doping type of drift region, The doping type of source region and the doping type in drain region are N-type.
In one embodiment of the invention, isolated area is local field oxygen isolation area or shallow trench isolation region.
Compared with prior art, technical solution of the present invention has the advantage that
Semiconductor structure provided by the invention and forming method thereof forms channel region and drift region, channel region in body area Part extends to the direction where drift region, forms at least one channel extension area.At least one channel extension area and drift region Between formed interdigital distribution.The setting is so that longitudinal direction of the semiconductor structure provided by the invention between body area and drift region While PN junction forms depletion region, having lateral depletion area is formed between channel extension area and drift region, which to leak The surface field for the active area that end grid and isolated area are had a common boundary is reduced, to improve the breakdown voltage of device.
Further, settable channel extension area and drift region contact, form transverse p/n junction, the transverse p/n junction between the two Having lateral depletion can be realized under smaller reverse biased.But since the longitudinal P N knot in body area and drift section is same what is longitudinally exhausted When also can transversely exhaust, therefore, in design, settable channel extension area and drift region are not directly contacted with, and are had between the two Set distance.Enter in channel extension area when the longitudinal P N in body area and drift section is tied when having lateral depletion occurs, with additional The increase of voltage, transversely gradually exhausts between drift region and channel extension area, and equally can reach reduces drain terminal grid and isolated area The effect of the surface field of the active area of boundary.For the production convenient for device and meet design rule, setting channel extension area Shape is the rectangle or trapezoidal of strip.
For above and other objects of the present invention, feature and advantage can be clearer and more comprehensible, preferred embodiment is cited below particularly, And cooperate attached drawing, it is described in detail below.
Detailed description of the invention
Fig. 1 show the structural schematic diagram of existing p-type LDMOS device.
Fig. 2 show in Fig. 1 p-type LDMOS device along the schematic diagram of the section structure of AA ' line.
Fig. 3 to Fig. 9 show the structural schematic diagram of the forming process of the semiconductor structure of one embodiment of the invention offer.
Figure 10 show the structural schematic diagram of the semiconductor structure of one embodiment of the invention offer.
Specific embodiment
Fig. 1 and Fig. 2 are please referred to, wherein Fig. 2 is diagrammatic cross-section of the Fig. 1 along AA ' line.The system of existing p-type LDMOS device In work, since the active area of drain terminal grid and isolated area boundary has biggish surface field, which limits p-type LDMOS device breakdown voltage.Inventor it has been investigated that, pass through the surface electricity for reducing the active area that drain terminal grid and isolated area are had a common boundary Field can effectively improve the breakdown voltage of LDMOS device.
For this purpose, the present invention provides a kind of semiconductor structure and forming method thereof, passes through and form interdigital point in body area The channel region of cloth and drift region form having lateral depletion between the channel extension area and drift region on channel region.The having lateral depletion exists The active area that the length direction of gate structure extends to entire drain terminal grid and isolated area is had a common boundary, the setting can effectively reduce drain terminal grid The surface field for the active area having a common boundary with isolated area, to achieve the effect that improve semiconductor structure breakdown voltage.
Specific embodiments of the present invention are described in detail below in conjunction with attached drawing.When describing the embodiments of the present invention, it is Convenient for explanation, schematic diagram can disobey general proportion and make partial enlargement, and the schematic diagram is example, should not be limited herein Protection scope of the present invention.In addition, the three-dimensional space of length, width and depth should be included in actual fabrication.
Fig. 3 to Fig. 9 show the structural schematic diagram of the forming process of semiconductor structure provided in this embodiment.Wherein, Fig. 7 It is identical as the position of the hatching of Fig. 5 to the position of the hatching of Fig. 9.
Firstly, as shown in figure 3, offer semiconductor substrate 200, forms body area 201, body area 201 in semiconductor substrate 200 Doping type with the doping type of semiconductor substrate 200 on the contrary, between the two formed PN junction be isolated.In this present embodiment, half The material of conductor substrate 200 is silicon, doping type P.However, the present invention is not limited in any way this.In other embodiments In, semiconductor material 200 can be germanium, SiGe, silicon carbide, silicon-on-insulator or germanium on insulator.
In this present embodiment, body area 201 is formed by the way of extension.The body area 201 being epitaxially formed has uniform miscellaneous Matter distribution, doping concentration 1016cm-3Magnitude.However, the present invention is not limited in any way this.In other embodiments, body area 201, which can be used trap injection technology, forms.Since semiconductor structure provided in this embodiment is p-type LDMOS, N is adulterated in body area 201 The first in type foreign ion, including phosphonium ion, arsenic ion or antimony ion is several.However, the present invention does not make any limit to this It is fixed.In other embodiments, when the semiconductor structure of formation is N-type LDMOS, doped p-type foreign ion in body area 201, packet Include one or more of boron ion, gallium ion or indium ion.
Then, with reference to fig. 4 to fig. 6.Fig. 4 show bowing after forming drift region 204 and channel region 203 in body area 201 View.Fig. 5 show Fig. 4 along the schematic diagram of the section structure of BB ' line, and Fig. 6 show Fig. 4 along the schematic diagram of the section structure of CC ' line.
Firstly, forming drift region mask layer in body area 201, on the mask layer of drift region there is a drift region to inject window Mouthful, by trap injecting p-type foreign ion in drift region injection window, form drift region 204.However, the present invention to this not It is limited in any way.When the semiconductor structure of formation is N-type LDMOS, body area 201 can inject N-type impurity ion by trap come shape At drift region.To improve breakdown voltage, setting drift region 204 has lower doping concentration, doping concentration 1017cm-3Amount Grade.Preferably, the doping concentration that drift region 204 is arranged is 1E17cm-3.However, the present invention is not limited in any way this.
Then, channel region 203 is formed in body area 201, specific forming process is as follows: forming ditch on 201 surface of body area Road area mask layer injects window to the channel region that the direction where drift region 204 extends at least one on channel region mask layer Mouthful, trap injection is carried out to channel region 203 using channel region mask layer as exposure mask, the concentration of injection is 1017cm-3Magnitude.Channel region note Enter body area 201 corresponding to window and forms channel extension area 205.Preferably, the doping concentration of setting channel region 203 is 5E17cm-3.However, the present invention is not limited in any way this.
In this present embodiment, channel region injection window shape be strip rectangle, the doping type of channel region 203 with The doping type in body area 201 is identical, is N-type impurity ion.However, the present invention does any restriction to this.In other embodiments In, the channel region injection window on trench mask layer can be the other figures for meeting design rule, such as trapezoidal；Work as semiconductor junction When structure is N-type LDMOS, the impurity that channel region 203 injects is p type impurity ion.
In this present embodiment, the channel region extended on channel region mask layer with the direction where one to drift region 204 Window is injected, it is corresponding, there is on channel region 204 a channel extension area 205 after injecting.However, the present invention does not make this Any restriction.There can be more than two channel extension areas 205 in other embodiments, on channel region 204.
In this present embodiment, channel region mask layer and drift region mask layer are silica.However, the present invention does not make this Any restriction.In other embodiments, channel region mask layer and drift region mask layer can be silicon nitride.
Since the implantation concentration of channel region 203 is higher than the implantation concentration of drift region 204, channel extension area 205 can make to drift about 204 transoid of area forms PN junction.Therefore the present invention is not limited in any way the specific structure of drift region mask layer.Drift region mask layer Specific structure can the finger-like to match with channel region mask layer, the strip rectangle in traditional LDMOS structure or other Meet the structure of design rule.
Structure as shown in Figure 4 is ultimately formed after channel region injects.In this configuration to there are 205 institutes of channel extension area Position and there is no channel extend 205 where position be respectively formed sectional view.Wherein, Fig. 5 is Fig. 4 cuing open along BB ' line View, Fig. 6 are cross-sectional view of the Fig. 4 along CC ' line.
In Fig. 5, channel extension area 205 is contacted with drift region 204, forms lateral PN junction between the two, when drain-source it Between plus when reverse phase bias, channel extension area 205 and drift region 204 transversely exhaust and the length direction of gate structure 206 should The active area that having lateral depletion area extends to entire drain terminal grid and isolated area is had a common boundary.Having lateral depletion makes the surface electricity of drift region 204 , especially after formation isolated area, the surfaces of active regions electric field of drain terminal grid and isolated area boundary is minimized.The drop of surface field It is low to be bound to so that breakdown voltage is improved.
And since its structure is identical as traditional p-type LDMOS structure in Fig. 6, between drain-source plus when forward bias, lead The parameters such as resistance that are powered can't change.Therefore, semiconductor structure provided in this embodiment is made by drain terminal optimization design Interdigital distribution is formed between channel region 203 and drift region 204, can be obtained in the case where not changing the other characteristics of device To higher breakdown voltage.Further, due to reducing one layer of mask plate at the production moment, significantly without adding drain terminal injection Reduce production cost.
In semiconductor structure shown in Fig. 4, in addition to the transverse p/n junction between channel region 203 and drift region 204, there is also Longitudinal P N knot between drift region 204 and body area 201.Therefore, in other embodiments, settable channel extension area 205 and drift Moving has set distance between area 204, which is less than the longitudinal P N knot between drift region 204 and body area 201 transversely Exhaust distance.When applying reverse phase bias between drain-source, longitudinal P N knot exhausts in transverse direction and enters channel extension area 205 When, having lateral depletion is formed between channel extension area 205 and drift region 204, equally reaching reduces drain terminal grid and the boundary of isolated area 202 Active area surface field, improve the purpose of breakdown voltage.
With reference to Fig. 7, isolated area 202 is formed in drift region 204, the end of channel extension area 205 is located at isolated area 202 Lower section.In this present embodiment, isolated area 202 is shallow trench isolation region, specific forming process are as follows: is passed through on the surface of drift region 204 The isolation channel that depth is less than the depth of drift region 204 is formed after exposure mask, photoetching and etching, and isolated material is filled in isolation channel Shallow trench isolation region is eventually formed, isolated material can be silica, silicon nitride etc..However, specific knot of the present invention to isolated area 202 Structure and its formation sequence are not limited in any way.In other embodiments, isolated area 202 can be formed in the area Xian Ti 201, then into Row trap injects to form channel region 201 and drift region 204, and isolated area 202 can also be in beak-like for what is formed after local oxidation Local field oxygen isolation area.
Then, referring to Fig. 8, gate structure is formed in the semiconductor substrate 200 for forming channel region 203 and drift region 204 206.206 side of gate structure is located at 203 top of channel region, and the other side is located at the top of isolated area 205.Gate structure 206 wraps It includes the gate dielectric layer 207 positioned at 200 surface of semiconductor substrate, the gate electrode 208 on gate dielectric layer 207 and is located at grid and be situated between The side wall (not shown go out) of 208 two sides side wall of matter layer 207 and gate electrode.In this present embodiment, the material of gate dielectric layer 207 can be Silica, gate electrode 208 can be polysilicon, and side wall includes silica and silicon nitride.However, the present invention does not make any limit to this It is fixed.In other embodiments, gate dielectric layer 207 can be high dielectric constant material, and gate electrode 208 can be metal.
Finally, please referring to Fig. 9, source region 209 is formed in the channel region 203 of 206 side of gate structure, in gate structure Drain region 210 is formed in the drift region 204 of 206 other side, drain region 210 is located at side of the isolated area 202 far from channel region 203. In this present embodiment, the mode that source region 209 and drain region 210 are all made of ion implanting is formed, and the doping type of source region 209 and leakage The doping type in the area doping type Jun Yuti 201 in area 210 is on the contrary, be p-type.However, the present invention is not limited in any way this. In other embodiments, when semiconductor structure is N-type LDMOS, the doping type of source region 209 and the doping type in drain region 210 It is N-type.
The semiconductor structure formed using the above method, the direction where channel region 203 to drift region 204 are extended, channel Interdigital distribution is formed between extension area 205 and drift region 204.When adding reverse phase bias between drain-source, 205 He of channel extension area It is transversely exhausted between drift region 204, which can effectively reduce the table of the active area of drain terminal grid and the boundary of isolated area 205 Face electric field, to achieve the purpose that improve breakdown voltage.In addition, in addition to channel extension area 205, using the half of above method formation The structure of conductor structure other parts is identical as traditional structure of p-type LDMOS, and the electricity that can still retain traditional p-type LDMOS is special Property.
Corresponding with the forming method of above-mentioned semiconductor structure, the present embodiment also provides a kind of semiconductor structure, specifically Please refer to Figure 10.Figure 10 show the top view of semiconductor structure provided in this embodiment.Semiconductor junction provided in this embodiment Structure includes:
Semiconductor substrate 200, in this present embodiment, the doping type of semiconductor substrate are p-type；
Doping type in semiconductor substrate 200 is the area NXing Ti 201.However, the present invention does not make any limit to this It is fixed.In other embodiments, when semiconductor structure is p-type LDMOS, the doping type in body area 201 is p-type, correspondingly, partly leading The doping type of body substrate 200 is N-type.
The doping type of drift region 204 in body area 201, drift region 204 is opposite with the doping type in body area 201. The doping type of drift region 204 is p-type in this present embodiment.However, the present invention is not limited in any way this.In other embodiments In, when semiconductor structure is p-type LDMOS, the doping type of drift region 204 is N-type.
The doping type of channel region 203 in body area, channel region 203 is identical as the doping type in body area 201, Yu Ben The doping type of channel region 203 is N-type in embodiment.203 part of channel region to the direction where drift region 204 extend to form to A few channel extension area 205 forms interdigital distribution between at least one channel extension area 205 and drift region 204.Yu Ben In embodiment, there is a channel extension area 205 on channel region 203.However, the present invention is not limited in any way this.In other There can be more than two channel extension areas 205 in embodiment, on channel region 203.
Isolated area 202 in drift region 204.In this present embodiment, isolated area 202 is that depth is less than body area 201 The shallow trench isolation region of depth.However, the present invention is not limited in any way this.In other embodiments, isolated area 202 can be part Field oxygen isolation area.
The side of gate structure 206 positioned at the surface of semiconductor substrate 200, gate structure 206 is located at channel region 203 Top, the other side are located at the top of isolated area 202.In this present embodiment, gate structure 206 includes being located at semiconductor substrate 200 The gate dielectric layer 207 on surface, the gate electrode 208 on gate dielectric layer 207 and be located at gate dielectric layer 207 and gate electrode 208 The side wall of two sides side wall.
Source region 209 in the channel region 203 of 206 side of gate structure；
Drain region 210 in body area 201 and positioned at side of the isolated area 202 far from channel region 203.In the present embodiment In, it is p-type that the doping type of source region 209 is identical with the doping type in drain region 210.However, the present invention does not make any limit to this It is fixed.In other embodiments, when semiconductor structure is N-type LDMOS, the doping type of source region 209 and the doping class in drain region 210 Type is identical, is N-type.
Compared with prior art, technical solution of the present invention has the advantage that
Semiconductor structure provided by the invention and forming method thereof forms channel region 203 and drift region in body area 201 204, the direction where 203 part of channel region to drift region 204 extends, and forms at least one channel extension area 205.At least one Interdigital distribution is formed between channel extension area 205 and drift region 204.The setting is so that semiconductor structure provided by the invention While longitudinal P N between body area 201 and drift region 204 ties to form depletion region, channel region extension area 205 and drift region 204 Between form having lateral depletion area, the surface field for the active area which makes drain terminal grid and isolated area have a common boundary is dropped It is low, to improve the breakdown voltage of device.
Further, settable channel extension area 205 and drift region 204 contact, and form transverse p/n junction between the two, the cross Having lateral depletion can be realized under smaller reverse biased to PN junction.But since the longitudinal P N knot between body area 201 and drift region 204 exists Longitudinal direction also can transversely exhaust while exhausting, and therefore, in design, settable channel extension area 205 and drift region 204 be not straight Contact has set distance between the two, when the longitudinal P N between body area 201 and drift region 204 is tied when having lateral depletion occurs Into in channel region 203, with the increase of applied voltage, transversely gradually exhausted between drift region 204 and channel region 203, together Sample can reach the effect for reducing the surface field of active area of drain terminal grid and isolated area boundary.For the production convenient for device and meet The shape of design rule, setting channel extension area is the rectangle or trapezoidal of strip.
Although the present invention is disclosed above by preferred embodiment, however, it is not intended to limit the invention, this any known skill Skill person can make some changes and embellishment without departing from the spirit and scope of the present invention, therefore protection scope of the present invention is worked as Subject to claims range claimed.

Claims (12)

1. a kind of forming method of semiconductor structure characterized by comprising
Semiconductor substrate is provided, forms body area in the semiconductor substrate；
Drift region is formed in the body area, the doping type of the drift region is opposite with the doping type in the body area；
Channel region is formed in the body area, the direction where the channel region portions to the drift region extends, and is formed at least One channel extension area forms interdigital distribution, the ditch between at least one described channel extension area and the drift region The doping type in road area is identical as the doping type in the body area；
Isolated area is formed in the drift region, the end of at least one channel extension area is located under the isolated area Side；
Gate structure is formed in the semiconductor substrate surface；
Source region is formed in the channel region of the gate structure side, forms drain region in the drift region, the drain region is located at Side of the isolated area far from the channel region.
2. the forming method of semiconductor structure according to claim 1, which is characterized in that at least one described channel extends The forming process in area are as follows: form channel region mask layer in semiconductor substrate surface, have at least one on the channel region mask layer The channel region that a direction to where the drift region extends injects window, is infused using the channel region mask layer as exposure mask Enter, forms channel extension area in the body area corresponding at least one channel region injection window.
3. the forming method of semiconductor structure according to claim 1 or 2, which is characterized in that at least one described channel Extension area is contacted with the drift region.
4. the forming method of semiconductor structure according to claim 1 or 2, which is characterized in that at least one described channel There is set distance between extension area and the drift region.
5. the forming method of semiconductor structure according to claim 1, which is characterized in that when the semiconductor structure is P When type LDMOS, the doping type in the body area and the doping type of channel region are N-type, the doping type of the drift region, source The doping type in area and the doping type in drain region are p-type；When the semiconductor structure is N-type LDMOS, the body area The doping type of doping type and channel region is p-type, the doping type of the drift region, the doping type of source region and drain region Doping type be N-type.
6. the forming method of semiconductor structure according to claim 1, which is characterized in that the implantation concentration of the channel region Greater than the implantation concentration of drift region, the implantation concentration of the channel region and the implantation concentration of drift region are 1017cm-3Magnitude.
7. a kind of semiconductor structure characterized by comprising
Semiconductor substrate；
Body area is located in the semiconductor substrate；
Drift region is located in the body area, and the doping type of the drift region is opposite with the doping type in the body area；
Channel region is located in the body area, and the direction where the channel region portions to the drift region extends, and forms at least one A channel extension area forms interdigital distribution, the channel between at least one described channel extension area and the drift region The doping type in area is identical as the doping type in the body area；
Isolated area is located in the drift region, and the end of at least one channel extension area is located at the lower section of the isolated area；
Gate structure, positioned at the surface of the semiconductor substrate；
Source region, in the channel region of the gate structure side；
Drain region in the drift region and is located at side of the isolated area far from the channel region.
8. semiconductor structure according to claim 7, which is characterized in that the shape of at least one channel extension area is The rectangle of strip is trapezoidal.
9. semiconductor structure according to claim 7 or 8, which is characterized in that at least one described channel extension area and institute Drift region is stated to be in contact.
10. semiconductor structure according to claim 7 or 8, which is characterized in that at least one described channel extension area and institute Stating has set distance between drift region.
11. semiconductor structure according to claim 7, which is characterized in that when the semiconductor structure is p-type LDMOS, The doping type in the body area and the doping type of channel region are N-type, the doping class of the doping type of the drift region, source region Type and the doping type in drain region are p-type；When the semiconductor structure be N-type LDMOS when, the doping type in the body area and The doping type of channel region is p-type, the doping type of the doping type of the drift region, the doping type of source region and drain region It is N-type.
12. semiconductor structure according to claim 7, which is characterized in that the isolated area be local field oxygen isolation area or Shallow trench isolation region.
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