CN110021655B - Semi-super-junction lateral double-diffusion metal oxide semiconductor field effect transistor with stepped N-type heavy-doping buried layer - Google Patents
Semi-super-junction lateral double-diffusion metal oxide semiconductor field effect transistor with stepped N-type heavy-doping buried layer Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 230000005669 field effect Effects 0.000 title claims abstract description 16
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 16
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 16
- 238000009792 diffusion process Methods 0.000 title abstract description 5
- 230000015556 catabolic process Effects 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims description 5
- 230000005684 electric field Effects 0.000 abstract description 18
- 230000000694 effects Effects 0.000 abstract description 7
- 238000005457 optimization Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
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- 238000000137 annealing Methods 0.000 description 1
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- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
Abstract
The invention provides a semi-super junction lateral double-diffusion metal oxide semiconductor field effect transistor with a step N-type heavy doping buried layer. The device forms an N-type drift auxiliary region in the middle area of the upper part of a P-type epitaxial layer, the left end of the N-type drift auxiliary region is adjacent to a P-type base region, and the right end of the N-type drift auxiliary region is adjacent to a semi-super junction region; a stepped N-type heavily doped buried layer is arranged inside the P-type epitaxial layer; the distance W between the upper end of the thinner N-type heavily doped buried layer and the half super junction region meets the requirement that the P-type epitaxial layer above the thinner N-type heavily doped buried layer is completely depleted; the step height h of the step N-type heavily doped buried layer is matched with the heavily doped concentration. The invention further optimizes the contradiction relation between the breakdown voltage and the specific on-resistance by adjusting the electric field distribution at the two ends of the drain source while solving the substrate auxiliary depletion effect, and realizes high breakdown voltage and low specific on-resistance.
Description
Technical Field
The invention relates to the technical field of semiconductor power devices, in particular to a semi-super junction lateral double-diffusion metal oxide semiconductor field effect transistor.
Background
Lateral power semiconductor devices LDMOS (Lateral Double-diffused MOSFET) are the key technology for high Voltage Integrated circuits hvic (high Voltage Integrated circuit) and power Integrated circuits pic (power Integrated circuit). The method is mainly characterized in that a relatively long lightly doped drift region is added between a base region and a drain region, and the doping type of the drift region is consistent with that of the drain region. By adding the drift region, the effect of sharing breakdown voltage can be achieved, the breakdown voltage of the LDMOS is improved, the low on-resistance optimization target is achieved, and the conduction loss of the LDMOS is minimized. Because of its advantages of high breakdown voltage, low on-resistance, and easy integration with low-voltage devices, it has been widely used in power integrated circuits and power integrated systems.
The super junction (super junction) structure is an N-type column region and a P-type column region which are alternately arranged, and if the drift region of the LDMOS is replaced by the super junction structure, the super junction LDMOS, which is called SJ-LDMOS for short, is formed. Theoretically, the super-junction structure can obtain high breakdown voltage through charge balance between the N-type column region and the P-type column region, and can obtain very low on-resistance through the heavily doped N-type column region and the heavily doped P-type column region, so that a super-junction device can obtain a good compromise between two key parameters of breakdown voltage and on-resistance.
However, for the SJ-LDMOS, the N-type column region (or the P-type column region) is depleted in an auxiliary mode of the substrate, so that the P-type column region (or the N-type column region) cannot be completely depleted when the device is broken down, the charge balance between the N-type column region and the P-type column region is broken, and the transverse breakdown voltage of the SJ-LDMOS device is reduced.
Compared with the common super junction, the semi-super junction, namely the super junction area occupies half or part of the drift area, an electric field peak is added, so that the breakdown voltage is improved, the process difficulty is low, and the substrate auxiliary effect of the common super junction can be relieved to a certain extent.
The continuous optimization of the breakdown voltage and the specific on-resistance to realize higher breakdown voltage and lower specific on-resistance is always the main content of the research and development work of the technology in the field.
Disclosure of Invention
The invention provides a semi-super-junction transverse double-diffusion metal oxide semiconductor field effect transistor with a stepped N-type heavy doping buried layer, and aims to further optimize breakdown voltage and specific on-resistance and realize higher breakdown voltage and lower specific on-resistance.
The scheme of the invention is as follows:
the half super junction lateral double-diffused metal oxide semiconductor field effect transistor with the step N-type heavy doping buried layer comprises:
a P-type substrate;
the P-type epitaxial layer is positioned on the surface of the P-type substrate;
a P-type base region is formed at the left end of the upper part of the P-type epitaxial layer, and an N-type source region is formed on the partial surface of the P-type base region;
a half super junction area formed at the right end of the upper part of the P-type epitaxial layer comprises an N-type column area and a P-type column area which are arranged at intervals in a transverse period; forming an N-type drain region on the surface of the half super junction region part;
the prior art is different from the prior art:
forming an N-type drift auxiliary region in the middle area of the upper part of the P-type epitaxial layer, wherein the left end of the N-type drift auxiliary region is adjacent to the P-type base region, and the right end of the N-type drift auxiliary region is adjacent to the semi-super junction region;
a stepped N-type heavily doped buried layer is arranged inside the P-type epitaxial layer; wherein, the region close to the source end is a thicker N-type heavily doped buried layer which longitudinally corresponds to the base region; the region close to the drain region is a thin N-type heavily doped buried layer and longitudinally corresponds to the N-type drift auxiliary region and the semi-super junction region;
the distance W between the upper end of the thinner N-type heavily doped buried layer and the half super junction region meets the requirement that the P-type epitaxial layer above the thinner N-type heavily doped buried layer is completely depleted;
the step height h of the step N-type heavily doped buried layer is matched with the heavily doped concentration and determined according to the breakdown voltage requirement.
The surface of the N-type heavily doped buried layer represents the height difference in a step form; it should be appreciated that the stepped form described herein should be understood in a broad sense, i.e., flat steps are not required.
Based on the basic scheme, the invention further optimizes the following steps:
the doping concentration of the stepped N-type heavily doped buried layer is more than 1 x 1017cm3. The width of the thicker N-type heavily doped buried layer is 1/5-1/2 of the width of the device, and is determined according to the requirement of breakdown voltage; preferably, 1/4 times the width of the device may be desirable.
The semi-super-junction area is formed by transversely and periodically arranging an N-type column area and a P-type column area at intervals, the width of each N-type column area is the same, and the width of each P-type column area is the same. Further, the width of each N-type column region is preferably the same as that of each P-type column region.
The cross section of the stepped N-type heavily doped buried layer is circular or rectangular; the longitudinal section of the stepped N-type heavily doped buried layer is also preferably circular or rectangular.
The concentration of the N-type doped buried layer is preferably uniform.
The doping concentration of the N column and the P column injected into the semi-super junction region is 4-5 multiplied by 1016cm3。
The position of the N-type heavily doped buried layer is determined by the distance W between the upper end of the thin N-type heavily doped buried layer and the half super junction region. In order to effectively lead the high potential of the drain terminal to the source terminal, the P-type epitaxial layer above the N-type heavily doped buried layer is completely depleted, and the value of W can be determined according to the charge conservation principle.
The step height h of the N-type heavily doped buried layer needs to be determined according to the specific doping concentration condition, the more uniform the electric field intensity of the adjusted drain end and source end is, the larger the breakdown electric field of the device is, and when the drain end and the source end can be broken down simultaneously, the maximum breakdown electric field of the device is.
The invention further optimizes the contradiction relation between the breakdown voltage and the specific on-resistance by adjusting the electric field distribution at the two ends of the drain source while solving the substrate auxiliary depletion effect, and realizes high breakdown voltage and low specific on-resistance. The method has the following advantages:
compared with the traditional SJ-LDMOS, the invention introduces a new longitudinal electric field peak through the action of the stepped N-type heavily doped buried layer, and improves the longitudinal breakdown voltage. Meanwhile, the electric field of the device body is redistributed, the high voltage born by the drain-lined junction is more uniformly pulled to the source end originally, the potential line density of the source end and the drain end can be uniformly adjusted by the height of the step, and the withstand voltage of the device is further increased.
In addition, the charge imbalance between the N-type column region and the P-type column region in the super junction is compensated by the aid of the N-type drift auxiliary region of the semi-super junction, the substrate auxiliary effect is overcome, and the breakdown voltage is improved; the semi-super junction introduces an electric field peak on the surface, and the breakdown voltage can be improved as well.
According to the structure, the step height of the N-type heavily doped buried layer is optimized, so that electric fields of a drain end and a source end are distributed more uniformly, a surface transverse electric field and an internal longitudinal electric field are practically optimized at the same time, the breakdown voltage of the device is greatly improved, and the performance of the device is effectively improved.
Drawings
Fig. 1 is a three-dimensional schematic view of a semi-super junction lateral double-diffused metal oxide semiconductor field effect transistor structure of a stepped N-type heavily doped buried layer according to the present invention.
Fig. 2 is a right side view of the drift region of fig. 1.
Wherein, the 1-P type epitaxial layer; 2-step N type heavily doped buried layer; a 3-P type base region; 4-N column; a 5-P column; a 6-N + type drain region; a 7-N + type source region; an 8-N type drift auxiliary region; 9-P type substrate.
Detailed Description
The present invention will be described with reference to the drawings by taking an N-channel LDMOS as an example.
As shown in fig. 1 and fig. 2, the semi-super junction lateral double diffused metal oxide semiconductor field effect transistor with a stepped N-type heavily doped buried layer of the present invention comprises:
a P-type substrate 9;
the P-type epitaxial layer 1 positioned on the substrate is used as a buffer layer of the device;
a stepped N-type heavily doped buried layer 2 positioned inside the P-type epitaxial layer;
the P-type base region 3 is positioned on the surface of the P-type epitaxial layer;
an N + type source region 7 positioned on the partial surface of the P type base region;
an N + type drain region 6 positioned on the surface of the half super junction region part;
the half super junction area is formed by arranging N columns 4 and P columns 5 at intervals in a transverse period (only two periods are simplified in the figure, and actually, a plurality of periods are usually arranged), the width of each N-type column area is the same, and the width of each P-type column area is the same; the width of each N-type column region is the same as that of each P-type column region. The doping concentration of the N column and the P column injected into the semi-super junction region is 4-5 multiplied by 1016cm3；
The N-type drift auxiliary region 8 is positioned on the surface of the P-type epitaxial layer, the left end of the N-type drift auxiliary region is adjacent to the P-type base region, and the right end of the N-type drift auxiliary region is adjacent to the semi-super junction region.
The doping concentration of the stepped N-type heavily doped buried layer is more than 1 x 1017cm3(ii) a The width of the thicker N-type heavily doped buried layer is 1/5-1/2 of the width of the device.
The distance W between the upper end of the thinner N-type heavily doped buried layer and the half super junction region is 1-1.5 times of the width of the device.
The step height h of the step N-type heavily doped buried layer is 0.25-0.75 times of the width of the device.
The thickness of the P-type epitaxial layer below the stepped N-type heavily doped buried layer is 0.5-1 times of the width of the device.
The thickness of the thinner N-type heavily doped buried layer is 1-2 um.
The device can be prepared by the following steps:
1) a P-type layer with high resistivity is epitaxially grown on a semi-insulating material (comprising Si, SiC, GaAs and the like) substrate;
2) implanting ions into the N-type heavily doped buried layer and annealing;
3) a P-type base region is formed at the upper left end of the epitaxial layer;
4) forming an N-type source region in the P-type base region;
5) forming an N-type drift auxiliary region at the position where the P-type epitaxial layer is adjacent to the P-type base region;
6) forming a semi-super junction region on the N-type drift auxiliary region, wherein the semi-super junction region comprises an N-type column region and a P column which are arranged at intervals in a transverse period;
7) and forming a heavily doped N-type drain region on the semi-super junction region.
The specific doping process is well-established in the prior art and is not described herein.
The device is characterized in that a semi-super junction is manufactured on a P-type epitaxial wafer layer, and an equipotential stepped N-type heavily doped buried layer is injected into a substrate depletion region. Compared with the traditional SJ-LDMOS, on one hand, the charge imbalance between the N-type column region and the P-type column region in the super junction is compensated by the aid of the N-type drift auxiliary region, the substrate auxiliary effect is overcome, and breakdown voltage is improved; on the other hand, a new longitudinal electric field peak can be introduced into the stepped N-type heavily doped buried layer, so that the longitudinal breakdown voltage is improved. Meanwhile, the electric field of the device body is redistributed, the high voltage born by the drain-lined junction is more uniformly pulled to the source end originally, the potential line density of the source end and the drain end can be uniformly adjusted by the height of the step, and the breakdown voltage is further improved; and because the semi-super junction is adopted, an electric field peak is introduced into the surface, and the breakdown voltage can be improved. The structure solves the substrate auxiliary effect of the traditional SJ-LDMOS, reduces the high electric field in the source end body, practically optimizes the surface transverse electric field and the internal longitudinal electric field at the same time, and greatly improves the breakdown voltage of the device.
ISE TCAD simulation shows that the performance of the device is greatly improved compared with the traditional device, and the breakdown voltage of the device is improved by about 40% under the condition that the lengths of drift regions of the two devices are the same; the specific on-resistance drops by about 30% with the same breakdown voltage of both devices.
Of course, the LDMOS of the present invention may also be a P-channel LDMOS, and its structure is equivalent to that of an N-channel LDMOS, which also belongs to the protection scope of the claims of the present application and is not described herein again.
Claims (8)
1. A half super junction lateral double diffused metal oxide semiconductor field effect transistor with a stepped N-type heavily doped buried layer comprises:
a P-type substrate;
the P-type epitaxial layer is positioned on the surface of the P-type substrate;
a P-type base region is formed at the left end of the upper part of the P-type epitaxial layer, and an N-type source region is formed on the partial surface of the P-type base region;
a half super junction area formed at the right end of the upper part of the P-type epitaxial layer comprises an N-type column area and a P-type column area which are arranged at intervals in a transverse period; forming an N-type drain region on the surface of the half super junction region part;
the method is characterized in that:
forming an N-type drift auxiliary region in the middle area of the upper part of the P-type epitaxial layer, wherein the left end of the N-type drift auxiliary region is adjacent to the P-type base region, and the right end of the N-type drift auxiliary region is adjacent to the semi-super junction region;
a stepped N-type heavily doped buried layer is arranged inside the P-type epitaxial layer; wherein, the region close to the source end is a thicker N-type heavily doped buried layer which longitudinally corresponds to the base region; the region close to the drain region is a thin N-type heavily doped buried layer and longitudinally corresponds to the N-type drift auxiliary region and the semi-super junction region;
the distance W between the upper end of the thinner N-type heavily doped buried layer and the half super junction region meets the requirement that the P-type epitaxial layer above the thinner N-type heavily doped buried layer is completely depleted;
the step height h of the step N-type heavily doped buried layer is matched with the heavily doped concentration and determined according to the breakdown voltage requirement.
2. The half super junction lateral double diffused metal oxide semiconductor field effect transistor with the stepped heavily doped buried N-type layer of claim 1, wherein: the doping concentration of the stepped N-type heavily doped buried layer is more than 1 x 1017cm3(ii) a The width of the thicker N-type heavily doped buried layer is 1/5-1/2 of the width of the device, and is determined according to the requirement of breakdown voltage.
3. The half super junction lateral double diffused metal oxide semiconductor field effect transistor with the stepped heavily doped buried N-type layer of claim 1, wherein: the width of each N-type column region of the half super junction region is the same, and the width of each P-type column region is the same.
4. The half super junction lateral double diffused metal oxide semiconductor field effect transistor with the stepped heavily doped buried N-type layer of claim 3, wherein: each N-type pillar region has the same width as each P-type pillar region.
5. The half super junction lateral double diffused metal oxide semiconductor field effect transistor with the stepped heavily doped buried N-type layer of claim 1, wherein the cross section of the stepped heavily doped N-type layer is circular or rectangular; the longitudinal section of the stepped N-type heavily doped buried layer is circular or rectangular.
6. The half super junction lateral double diffused metal oxide semiconductor field effect transistor with the stepped heavily doped buried N-type layer of claim 1, wherein the doping concentration of the stepped heavily doped N-type layer is uniform.
7. The half super junction lateral double diffused metal oxide semiconductor field effect transistor with the stepped heavily doped buried N-type layer of claim 1, wherein: the doping concentration of the N column and the P column injected into the semi-super junction region is 4-5 multiplied by 1016cm3。
8. The half super junction lateral double diffused metal oxide semiconductor field effect transistor with the stepped heavily doped buried N-type layer of claim 1, wherein:
the value range of the distance W between the upper end of the thin N-type heavily doped buried layer and the half super junction region is 1-1.5 times of the width of the device;
the step height h of the step N-type heavily doped buried layer ranges from 0.25 to 0.75 times of the width of the device;
the value range of the thickness of the P-type epitaxial layer below the stepped N-type heavily doped buried layer is 0.5-1 times of the width of the device;
the thickness range of the thin N-type heavily doped buried layer is 1-2 um.
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